JPH03283081A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable a data processing in a short time by simultaneously execut ing read and write by setting plural data input/output terminals individually for respective two groups at least corresponding to various modes when using the plural data input/output terminals in the various modes. CONSTITUTION:An input/output control circuit 20 is provided between input/ output terminals 11 and buffers 8 and 9. When reading data, the input/output control circuit 20 turns the data-in buffer 8 to an inactive state and turns the data-out buffer 9 to an active state and the selected internal data is read out from the data-out buffer 9 corresponding to respective data input/output signals DQ1-DQ16. When writing data, the data-out buffer 9 is turned to the in-active state and the data-in buffer 8 is turned to the active state reversely. Then, the respective data input/output signals DQ1-DQ16 impressed from an external part to the input/output terminals 11 are stored through the data-in buffer 8 to an internal part. Thus, the data can be processed in a short time by simultane ously executing read and write.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly in a semiconductor memory device having a large capacity and a large number of output terminals, each input/output terminal is operated in a different mode ( The present invention relates to a semiconductor memory device that can be used in an input mode or an output mode.

[Prior Art] FIG. 4 shows, for example, a 4-megabyte system 9.0 having four data input/output terminals. 1 is a block diagram showing a conventional semiconductor memory device using a DRAM having a memory capacity of 1.

In FIG. 4, (1) is a memory cell, (2) is a sense l) fresh amplifier and I10 control circuit, (
3) is the row (ROWI Tekota), (4) is the column (C
OLUMli) decoder, (5) row and column address buffer, (6) clock generator, (7) AND circuit, (8) theta in hasha sofa, (9) the theta out ha sofa, (10) Address input signal A. ~A8
(11) is the data input/output terminal to which the data input/output signals DQ, ~DQ are input/output, (12) is the column address strobe input signal CAS
(13) is an input terminal to which the low address strobe input signal PAS is supplied; (14) is an input terminal to which the write control input signal W is supplied;
(15) is an input terminal to which the output enable input output OE is supplied, (16) is a power supply terminal to which power supply voltage Vcc is applied, and (17) is a ground terminal to which ground voltage Vss is applied.

FIG. 5 is a timing diagram when the operation mode is RMW (read modify write).

Next, the operation shown in FIG. 4 will be explained with reference to FIG. When the signal CAS is at a high level (H) and the signal RAS is changed from a high level to a low level (L), the black and white generator (6)
) Address input signal A from the address input terminal (10) to the callow and column address buffer (5). −
A is sent as a low address and a signal is sent internally to be taken in, and the selected word line (not shown) of the memory cell (1) is brought to a high level by the row decoder (3) selected by the taken-in address. The contents of the memory cell (1) on the selected word line are read out to a bit line (not shown). The read contents of the memory cell (1) are set to low level or low level by the sense reflex amplifier (2).

The above operation is performed inside the circuit, but when the next time the signal CAS is changed from the high level to the low level externally (at this time, the signal W is set to the high level), the clock generator (6) becomes low and low. Address input signal A from address input terminal (10) to column address buffer (5). -Sends a signal to internalize A as a cola, muatres. At this time, when the signal W is set to high level (then it operates as a read node, the column decoder (4) is selected according to the taken column address, and the memory cell (1) that was read out to the bit line earlier is The information is transmitted to the data output terminal (9) via the I10 control circuit (2).Next, when the signal OE is changed from the high level to the low level, the data output signal is transmitted to the data output terminal (9).
9) The information corresponding to the selected address is output from the data input/output terminal (11). In the RMW mode, after this readout, the signal OE is set from low level to high level 1, and after no output data is output, the signal W is set from high level to low level. At this time, the signals DQ, ~DQ, which were applied to the data input/output terminal (11), are used as data input from the data input/output terminal (11) to the cheat-in buffer (8).
). The captured data is written into the selected memory cell (1) via the previously selected I10 control circuit (2). Memory cell (1) selected by row address and column address in this way
The signal R is used to perform operations such as reading and writing.
The mode that is carried out in one cycle from AS KAHI REHEL → LOW LEVEL → NO\I level is called RMW mode.

[Problems to be Solved by the Invention] By the way, in the conventional semiconductor memory device as described above, in order to perform reading and writing separately for each input/output terminal, it is necessary to use RMW mode, and reading and writing are performed separately. Writing cannot be performed simultaneously, and it takes time because it is time-divided, which is a problem, especially in high-speed access modes such as fast mode, fast mode, and static mode.

This invention was made to solve these problems, and the object is to obtain a semiconductor memory device that can process data at high speed without requiring separate times for reading and writing. .

[Means for Solving the yA Problem] A semiconductor memory device according to the present invention is a semiconductor memory device having a plurality of input/output terminals, and an input/output control circuit is provided for the data input/output terminal, and the plurality of input/output terminals are provided with an input/output control circuit. When the data input/output terminals are used in different modes, the plurality of data input/output terminals are individually set for each of two groups in correspondence with the different modes.

[Function] In this invention, when a plurality of data input/output terminals are used in different modes such as input or output, the plurality of data input/output terminals are individually divided into at least two groups corresponding to the different modes. Set. This allows processing in different modes to be performed simultaneously, resulting in high-speed data processing.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of one embodiment of this invention, and (+) ~
(17) is similar to the conventional device described above.

However, here, the input/output terminal (11) is the data input/output (
It is assumed that g-numbers DQ and ~DQ+a are input and output. In this example, the input/output terminal (11) and the sofa (8) (
The difference from the conventional device is that an input/output control circuit (20) is provided between the device and the device. This input/output control circuit (20) is set to determine the mode using signals RAS, CAS, W, and OE.

FIG. 2 is a timing diagram in the write/read mixed mode of the present invention, and the timing etc. for setting the write/read mixed mode are not shown.

Next, the operation shown in FIG. 1 will be explained. Normal read and write operations are performed simultaneously across all data input/output signals DQ, -DQ, @ of the input/output terminal (11) as in the conventional case.

In this case, the input/output control circuit (20) commonly controls the input/output terminal (11) for each data input/output signal DQ, -DQ+s. During reading, the input/output control circuit (20) deactivates the data in buffer (8), activates the data out buffer (9), and outputs each data input/output signal DQ, ~DQ from the data out buffer (9). , e is read out. Conversely, during writing, the data out buffer (9) is inactive, the data in buffer (8) is in the active state, and each externally applied signal is input to the input/output terminal (11) via the data in buffer (8). Data input/output signals DQ, ~DQ, , are stored internally.

Now, in this embodiment, input/output terminals (11
) and the input/output terminal (11) for reading can be shared. This control can be realized by separately controlling the input/output control circuit (20) for each input/output terminal (11). Switching the control of this input/output control circuit (20), that is, switching between the normal mode and the above-mentioned mode (write/continue output mixed mode) that shares the writing input/output terminal and the reading input/output terminal, is performed using a specific mode. Timing combinations may be used, for example, when the signal CAS is set to four levels and the signal RAS is set to a high level, the signal W is set to a low level and the signal OE is set to a low level, or a voltage is set from an external selection terminal (not shown). This may also be done by applying it.

Now, for example, the input/output terminal (11) to which the data input/output signals DQ, ~DQ, are applied is set to be in the write mode, and the input/output terminal (11) to which the data input/output signals DQ, ~DQ, are applied is set to the write mode. 11) is set to be in the read mode, and the input/output control circuit (20) is in the write/read mixed mode. Regarding the selection of row address and column address, the operation is similar to that of the conventional system described above. Conventionally, after the signal CAS becomes low level and an address is selected, reading and writing are performed using the signals OE and W, but in this embodiment, as described above, each input/output terminal (7) According to the information set in , a write operation is performed for data input/output signals DQ, .about.DQ, and a read operation is performed for data input/output signals DQ, .about.DQ, 6. The individual reading and writing operations can be considered to be the same as those of the prior art.

Looking at Figure 2, data input/output signals DQ1-D during writing
Q6 Is the notator valid area (DATA VALID) and the data valid area (DATA VALID) of the data input/output signals DQ, ~DQ, during reading time-shifted so that only writing and reading appear to be simultaneous? In the data valid area of signals DQ, ~DQ, the input/output terminal (1
1) Data is taken into the Luli data buffer (8), and in the right side (mesh-shaped part) of the data valid area of the data input/output signals DQ, ~DQe, the memory cell ( 1), data input/output signals DQo to DQ1 are being written.
In the data valid area 6, data is only read from the input/output control circuit (20) to each input/output terminal (11).
After all, data writing and reading are performed at the same time.

In this way, in this embodiment, the data input/output signal D to be written is
Data input/output signals DQe to D to be read as Q, ~DQs
Since Q, , are processed simultaneously, data processing can be performed at high speed.

Figure 3 shows an example of application of this invention, and Figure 3(a)
is a memory (21a) for data input/output signals DQ, ~DQe.
) and data input/output signals DQ8 to DQ, , memory (2
1b) is installed.

This is a case where it is used by switching between (22 to 25). First, by applying a voltage to an external terminal or using timing to enter a special mode, the memory (218) is read out;
When the memory (21b) is set for writing, that is, when the common terminal C of the switches (22) to (25) is connected to the contact a side, the address is sequentially counted up and data is read from the memory (21a). At the same time memory (2
Write data to 1b). When the address has advanced to the end, connect the common terminal C of the switches (22) to (25) to the contact side to switch the memory (21a) for writing and the memory (21b) for reading. By sequentially counting up the addresses, new data can be written at the same time instead of always reading eight pieces of read data.

FIG. 3(b) shows the semiconductor memory device of the present invention in two CPs.
In this case, the memory (21
a) for CPV (26), and memory (21b
) is used for CPV (27). In this case as well, new data can be written at the same time since data is not read.

[Effects of the Invention] As described above, according to the present invention, in a semiconductor memory device having a plurality of data input/output terminals, an input/output control circuit is provided for the data input/output terminal, and the plurality of data input/output terminals are controlled. When used in different modes, the multiple data input/output terminals are individually set for at least two groups corresponding to the different modes, so reading and writing can be performed simultaneously depending on how the input/output terminals are set. This has the effect that data processing can be performed in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of FIG. 1, and FIG.
4 is a block diagram showing an example of application of the present invention, FIG. 4 is a block diagram showing a conventional semiconductor memory device, and FIG. 5 is a timing chart for explaining the operation of FIG. 4. In the figure, (1) is a memory cell, (11) is an input/output terminal, and (20) is an input/output control circuit. In each figure, the same reference numerals indicate the same or corresponding parts. Figure Figure % ,, ;: □H;-Z
Te=ri fl-h-7-Ct force)

Claims (1)

[Claims] In a semiconductor memory device having a plurality of data input/output terminals, an input/output control circuit is provided for the data input/output terminal, and when the plurality of data input/output terminals are used in different modes, a A semiconductor memory device characterized in that the plurality of data input/output terminals are individually set for at least two groups.