JPS63292491A - Memory device - Google Patents

Abstract

PURPOSE:To execute a memory access at a high speed by a small number of hardwares, by supplying an RAS signal to all memory blocks, at the time point when a chip address signal has been decided definitely. CONSTITUTION:At a timing (a), a chip address and a block address are decided definitely, and this chip address is inputted as a chip address signal to a memory block 8-1 and 8-2. The block 8-1 and 8-2 start an operation in a state that a RAS signal can be inputted. Also, the block address which has been decided definitely is inputted as a block address signal to a block selecting circuit 6. The circuit 6 selects the block corresponding to the address signal and outputs a result of selection. In such a way, CAS inhibiting circuits 7-1, 7-2 operate, a CAS signal is supplied to only the selected block, and information of a read- out data line 9 is decided definitely.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory device that enables high-speed reading and writing of stored information in an information processing device.

(Prior Art) An example of the configuration of a conventional memory device is shown in FIG. 3. This figure shows a case including two memory blocks consisting of dynamic random access memory (DRAM).
The present invention is not limited to this, and any number of memory blocks can be provided.

In FIG. 3, a block selection circuit 6 selects a memory block 8-1 or 8-2 corresponding to a block address signal inputted from a block address line 5, and transmits the selection result to timing suppression circuits 10-1 and 10-2. Output to 2. The timing suppression circuit 10-1 selects the RAS signal lines 3 and C based on the information input from the block selection circuit 6.
Row address strobe (R
The memory block 8-1 is controlled by outputting or inhibiting the output of the AS) signal and the column address strobe (CAS) signal. Timing suppression circuit 10-2
similarly controls memory block 8-2.

Next, a read operation to the memory block 8-1 will be explained.

The timing suppression circuit 10-2, which has been notified of non-selection by the block selection circuit 6, performs RA to the memory block 8-2.
Suppresses the output of the S signal and CAS signal. Furthermore, the timing suppression circuit 10-1 that has been notified of the selection outputs the RAS signal and the CAS signal to the memory block 8-1. The memory block 8 - 1 starts operating upon receiving the RAS signal and the CAS signal, and outputs data corresponding to the address signal input from the chip address line 2 to the read data line 9 .

The timing at this time is shown in FIG.

(Problems to be Solved by the Invention) As shown in FIG. 4, in the conventional memory device described above, even if address information is input from the chip address line at timing a, there is no memory block to be selected at that time. Therefore, the RAS signal is input to the memory block at timing b when the output of the block selection circuit is determined. Therefore, there is a problem that the memory access time is delayed by the operation delay time of the block selection circuit.

(Means for Solving the Problems) In order to solve the above-mentioned problems, a memory device provided by the present invention has a plurality of memory blocks composed of DRAMs, and a chip address signal supplied to the chips of the DRAMs. The memory device also includes a chip address line that supplies the chip address signal to all memory blocks, and a RAS line that supplies the chip address signal to all memory blocks.
A RAS signal line that supplies signals, a block selection circuit that inputs the block address signal, selects a corresponding memory block, and outputs the selection result, and a block address that supplies the block address signal to the block selection circuit. a CAS suppression circuit that outputs a CAS signal only to the memory block selected by the block selection circuit and suppresses output of the CAS signal to other memory blocks;
and a CAS signal line for supplying the RAS to the suppression circuit.
The signal is characterized in that it is input to all memory blocks at the time when the chip address signal is determined.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a memory device according to an embodiment of the present invention.

In the figure, memory blocks 8-1 and 8-2 are connected to write data line 1, chip address line 2 and RAS signal line 3,
Write data, chip address signals and RAS signals are input from each. Block selection circuit 6 selects memory block 8-1 or 8-2 corresponding to the block address signal input from block address line 5, and outputs the selection result to CAS suppression circuits 7-1 and 7-2.

The CAS suppression circuit 7-1 outputs the CAS signal input from the CAS signal line 4 to the memory block 8-1 when the memory block 8-1 is selected by the block selection circuit 6, and when the memory block 8-1 is not selected, outputs the CAS signal input from the CAS signal line 4 to the memory block 8-1. The CAS suppression circuit 7-2, which suppresses the signal and does not output it to the memory block 8-1, also performs the same operation as the CAS suppression circuit 7-1 on the memory block 8-2. Read data obtained by wire-ORing the read outputs of memory blocks 8-1 and 8-2 is output. At this time,
Since the unselected memory blocks 8-1 and 8-2 output logic zero, the read data of the selected one is output as a result.

Next, the timing when reading data in this embodiment will be explained.

Timings a, b, c, and d in FIG. 2 are timing a in the conventional example of FIG. 4, respectively.

Equal to b, c, d.

At timing a, the chip address and block address are determined. The determined chip address is input to memory blocks 8-1 and 8-2 as a chip address signal. At this time, memory blocks 8-1 and 8-2 are RAS
Start operation by making the signal ready for input. Further, the determined block address is input to the block selection circuit 6 as a block address signal. As a result, the block selection circuit 6 starts operating, selects the memory block 8-1 or 8-2 corresponding to the input block address signal, and outputs the selection result. This block selection circuit 6
The CAS suppression circuits 7-1 and 7-2 are activated by the output of the memory blocks 8-1 and 8-2, and the CAS signal is output to the selected one of the memory blocks 8-1 and 8-2, but not to the unselected one. becomes. The memory block 8-1 or 8-2 to which the CAS signal has been input outputs the read data at timing c'1', and the information on the subsequent data line 9 is determined.

Time from RAS signal input to CAS signal input and CA
Since the time from input of the S signal to output of read data remains the same, the timing of outputting read data is earlier than in the conventional example by the amount that the timing of inputting the RAS signal is advanced. That is, in FIGS. 2 and 4, the difference between timings a and b is equal to the difference between timings C and d.

Although the present embodiment shows a case where there are two memory blocks, the same applies to a case where there are two or more memory blocks.

(Effects of the Invention) As explained above, the present invention outputs and activates the RAS signal to all memory blocks without waiting for the output of the block selection circuit, and the CAS signal is output based on the output of the block selection circuit. output only to the target memory block.

Therefore, there is an effect that memory access can be made faster with less hardware.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing a memory device according to an embodiment of the present invention, Fig. 2 is a timing diagram when reading data in the memory device of Fig. 1, and Fig. 3 is a diagram of a conventional example. FIG. 4 is a block diagram showing the memory device, and is a timing diagram when reading data in the memory device of FIG. 3. 1...Write data line, 2...Chip address line, 3
...RAS signal line, 4...CAS signal line, 5...
Block address line, 6...Block selection circuit, 7-
1゜7-2...CAS suppression circuit, 8-1.8-2...
・Memory block, 9... Successive data line, 1G-1,
10-2...Timing suppression circuit.

Claims (1)

[Claims] A memory block comprising a plurality of dynamic random access memory blocks, and determines the data position by using a block address signal for memory block selection together with a chip address signal supplied to the chip of the dynamic random access memory. A memory device comprising: a chip address line that supplies the chip address signal to all memory blocks; a RAS signal line that supplies a row address strobe signal to all the memory blocks; and a device that inputs and responds to the block address signal. a block selection circuit that selects a memory block and outputs the selection result; a block address line that supplies the block address signal to the block selection circuit; a column address only for the memory block selected by the block selection circuit; output strobe signal,
a CAS inhibit circuit that inhibits output of the column address strobe signal to other memory blocks; and a CAS signal line that supplies the column address strobe signal to the CAS inhibit circuit, and the row address strobe signal is A memory device characterized in that a chip address signal is input to all memory blocks when it is determined.