JPS6114583A - Signal tracking device of loran receiver - Google Patents

Abstract

PURPOSE:To stabilize the synchronism with a loran chart signal by calculating the degree of divergence of time difference lines in a loran chart near a ship position from position data on the ship and position data on a loran transmitting station, and controlling the integral constant of an integration circuit according to the arithmetic result. CONSTITUTION:A high-frequency pulse train from a reference oscillator 1 is led to main and slave frequency dividing circuits 2 and 8 directly and through a moving circuit 7 respectively, and main and slave station synchronizing pulses 3, 9 having the same period with the loran signal are phase-compared by main and slave station phase comparing circuits 4 and 10 with main and slave station loran signal from a receiver 5, thereby controlling the frequency of the oscillator 1 through an AFC circuit 6 according to the output of the circuit 4. An integrating meter 11 controls the circuit 7 with the output of the circuit 10 to synchronize its synchronizing signal with the slave station loran signal, and also reads ship data out of a latitude and longitude converter 12 and position data on the main and slave loran transmitting station out of a data memory 13 to increase an integration constant when the degree of divergence of time difference lines in the loran chart is small or decreases the constant when not.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to synchronizing a synchronization signal generated inside the receiver with a received Loran signal in a Loran receiver, and particularly relates to the movement of own ship. The present invention relates to a device for stably synchronizing a Loran signal and a synchronization signal.

(Prior Art) A Loran receiver measures the time difference between an incoming master station Loran signal and a slave station Loran signal. As is well known, this time difference measurement involves synchronizing the master station synchronization signal and the slave station synchronization signal with their respective Loran signals, and then measuring the time difference between the master station synchronization signal and the slave station synchronization signal. To achieve phase synchronization between the synchronization signal and the Loran signal, a phase comparison pulse is generated based on the synchronization signal, the phase comparison pulse is used to compare the phase with the Loran signal, and the comparison result is used to control the phase of the synchronization signal. Do the following.

When the own ship receives the Loran signal without moving, a phase shift between the Loran signal and the synchronization signal occurs quantitatively as the own ship moves, but it also occurs temporarily due to the introduction of noise. When performing phase control on such Loran signals, phase control is not performed on temporary phase shifts such as noise, but only on phase shifts caused by own ship's movement. It is necessary to do this.

Therefore, when performing the above phase control, the phase control is generally performed using an integrating circuit. That is, the phase comparison outputs are integrated, and phase control is performed only when the phase shift is integrated by a certain amount or more.

In this way, the phase shift caused by noise is temporary, and the direction of the phase shift is averaged in the leading phase direction and the phase slowing direction, so that the phase shift is canceled out in the integration circuit. Therefore, phase control is not performed on temporarily occurring phase shifts.

In the above, as the integration constant is increased, the integration circuit can prevent malfunction due to noise and perform stable phase control. However, when the integration constant is increased, the delay time of the phase control action on the detected phase shift increases. Therefore, when the moving speed of the own ship increases beyond a certain speed, it becomes impossible to maintain phase synchronization between the Loran signal and the synchronization signal. Therefore, the integration constant of the integration circuit is determined in consideration of the maximum movement speed of the own ship.

(Problem to be Solved by the Invention) The integration constant of the integration circuit is determined by considering the maximum moving speed of the own ship as described above, but also takes into consideration the own ship position on the Loran chart. Determined by

On the Loran chart in FIG. 3, on the base line BL connecting the master transmitting station M and the slave transmitting station S, the time difference line Tn
The linear density of T... is the highest. That is, the baseline BL
When the own ship moves above, the time difference change with respect to the movement of the own ship is the largest. Therefore, the phase shift between the Loran signal and the synchronization signal for a certain amount of movement of the own ship is maximized.

Conventionally, an integration constant is determined and fixed so that phase synchronization is performed with respect to a phase shift occurring on the base line BL.

However, if the own ship is located relatively far from the base line BL, for example, at point P in Figure 3, the time difference lines Tq to TQ
The divergence of , becomes larger, and the time difference change with respect to own ship's movement becomes smaller. That is, the phase shift between the Loran signal and the synchronization signal is also smaller than when moving on the base line BL. Therefore, when moving near point P, the phase shift can be sufficiently controlled even if the settlement constant is made larger than when moving on the base line BL. Also, time difference line Tl14
to 74. Since the S/N ratio of the Loran signal is also unstable near point P where the degree of divergence of is relatively large, it is desirable to increase the integration constant.

While the conventional integration constant is fixed, this invention
This method attempts to set the integration constant to an optimal value depending on the own ship's position. In other words, on the Loran chart in Figure 3, when the own ship is located near the base line BL, the integration constant is reduced, and when the ship is located at a position where the divergence of the time difference line or Tel is relatively large, the integration constant is compared. Make the target bigger,
To always perform stable synchronization with a Loran chart signal.

(Means for solving the problem) A means for solving the above problem is to calculate the degree of divergence of the time difference line in the vicinity based on the measured position of own ship, and to calculate the degree of divergence of the time difference line in the vicinity of the measured position The purpose is to provide means for controlling the integration constant of the arithmetic unit. Various types of integrator can be used, but for example, it can be composed of a reversible aJ counter, a numerical value setter, and a comparator that compares the counted value of the reversible counter and the set value of the numerical value setter. .

(Function) According to the above means, the calculation means calculates the degree of divergence near the own ship's position, and sets the numerical value of the numerical value setting device based on the calculation result. On the other hand, the reversible counter performs a counting operation corresponding to the phase shift direction every time a phase comparison is made between the Loran signal and the synchronization signal, and the counted value and the setting value of the numerical setting device are compared in the comparator. , when the count value of the reversible counter exceeds a set value, an output is sent from the comparator. and,
Phase control is performed by this output.

(Embodiment) In FIG. 1, a high-frequency pulse train sent out from a reference oscillator 1 is frequency-divided in a main station frequency dividing circuit 2 so that it has the same period as the transmission repetition period of the Loran signal. Based on the frequency division output of the main station frequency divider 2, the main station frequency division pulse generator 3 sends a main station synchronization pulse to the main station phase comparison circuit 4. The main station phase comparison circuit 4 performs a phase comparison between the main station synchronization pulse and the main station Loran signal sent from the receiver 5. This phase comparison is performed for a specific phase of the Loran signal. For example, in the case of the Loran C signal, as shown in FIG. 2, the phase of the synchronizing signal S is compared with the three-cycle phase of the Loran C signal a. This phase comparison result is sent to the AFC circuit 6,
Frequency control of the reference oscillator 1 is performed based on the phase comparison result. That is, when the synchronization signal S is ahead of the three-cycle phase of the Loran C signal a, the oscillation frequency of the reference oscillator 1 is lowered to delay the phase of the synchronization pulse b. Conversely, when the synchronization signal lags behind the three-cycle phase of the Loran C signal a, the oscillation frequency of the reference oscillator 1 is increased to advance the phase of the synchronization pulse b. A known AFC circuit 6 can be used as the AFC circuit 6. For example, when frequency control is performed digitally, the number of pulse trains per unit time can be increased or decreased by extracting a part of the pulse train generated by the oscillation circuit or by adding a new pulse train. This allows the reference oscillator 1
The repetition frequency of the high-frequency pulse train can be controlled based on the Loran signal arriving from the Loran transmitting station.

The high frequency pulse train sent out from the reference oscillator 1 is guided to the slave frequency divider 8 via the moving circuit 7. The slave frequency divider 8 is
In the same way as the main station frequency divider 2, the frequency of the high-frequency pulse train is divided until it becomes the same period as the transmission repetition period of the Loran signal. Based on this frequency-divided output, the slave synchronization pulse generation circuit 9 generates a slave synchronization pulse, and the slave phase comparison circuit 10 compares the phase of the slave synchronization pulse with the slave Loran signal.

Similarly to the master station phase comparison circuit 4, the slave station phase comparison circuit 10 compares the phases of the slave station synchronization pulse and the slave station Loran signal, and sends the comparison output to the integrator 11. The integrator 11 controls the moving circuit 7 to synchronize the slave synchronization signal with the slave Loran signal based on the phase comparison output between the slave synchronization pulse and the slave Loran signal. That is, when the slave station synchronization pulse is in a leading phase with respect to the synchronization position of the slave station Loran signal, the integrating circuit 11 extracts a part of the high frequency pulse train passing through the moving circuit 7 to delay the phase of the synchronization pulse.

Conversely, when the slave synchronization pulse is in a delayed phase with respect to the slave Loran signal, a new pulse train is added to the pulse train passing through the moving circuit 7 to advance the phase of the slave synchronization pulse.

The phase of the slave synchronization pulse generated by the slave synchronization pulse generation circuit 9 is controlled by the moving circuit 7.
The phase also changes when the frequency of the reference oscillator 1 is controlled by the FC circuit 6.

That is, when a phase shift occurs in the main station synchronization pulse, the phase shift is detected by the main station phase comparator circuit 4, and the AF
The number of high-frequency pulse trains of the reference oscillator 1 is temporarily changed by the C circuit 6. As a result, the main station synchronization pulse is transferred in a direction opposite to the direction in which the phase shift occurs, and synchronization is achieved. At this time, the high-frequency pulse train of the reference oscillator 1 is guided to the main station frequency divider 2, and at the same time, is also commonly guided to the slave station frequency divider 8. Therefore, when controlling the number of high-frequency pulse trains of the reference oscillator 1 to transfer the main station synchronization pulse, at the same time,
The slave station synchronization pulse is also transferred in conjunction. This phase causes a phase shift in the slave synchronization pulse. Therefore, the slave station phase comparison circuit 10, the integrator 11, and the moving circuit 7 detect and control the phase shift that occurs independently in the slave station synchronization pulse, and at the same time, they also detect the phase shift that occurs due to the phase shift of the master station synchronization pulse. Control. For example, when own ship moves,
Normally, a phase shift occurs in both the master station synchronization pulse and the slave station synchronization pulse. When the phase shift of the master station synchronization pulse is controlled, the phase shift of the master station synchronization pulse is added to the slave station synchronization pulse. Misalignment occurs. As a result, the phase shift of the master station synchronization pulse is proportional to the amount of movement of own ship, while the phase shift of the slave station synchronization pulse is
As explained in Fig. 3, it differs depending on the own ship's position on the Loran chart.

Based on the above points, as explained in FIG. 3, when the own ship is located near the base line BL on The integration constant is set to increase as the distance from the point increases.

To explain this below, the integrator 11 includes a reversible counter 111, a comparison circuit 112, a numerical value setter 113, and an arithmetic unit
14.

The reversible counter 111 performs addition counting or subtraction counting based on the phase comparison output of the slave phase comparison circuit 10. For example, in FIG. 2, when the synchronization pulse b is ahead in phase with respect to the synchronization position of the Loran signal a, addition counting is performed, and conversely, when the phase is behind, subtraction counting is performed. These addition and subtraction counts are performed by sending a pulse wave from the slave phase comparator circuit 10 to the addition terminal or subtraction terminal of the reversible counter 111.

The count value of the reversible counter 111 is compared with the set value of the value setter 113 in the comparison circuit 112. In this case, the comparator circuit 112 compares the absolute value of the count value of the reversible counter 111 with the set value of the numerical value setter 113, and if the absolute value of the reversible counter exceeds the set value, output pulses are sent to the shift circuit 7. Sending force. At this time, a sign output indicating whether the count value of the reversible counter 111 is an addition value or a subtraction value is sent to the moving circuit 7.

As for the code output, for example, when the count value of the reversible counter l11 is an addition value, a high level output is sent out, and when it is a subtraction value, a low level output is sent out. Each time an output pulse is sent from the comparison circuit 112, the moving circuit 7 controls the increase/decrease of the passing high frequency pulse train according to the sign output of the reversible counter 111, thereby controlling the phase of the slave synchronization pulse. Also, comparison circuit 1
12 is the reversible count value 111 at the same time as sending out the output pulse.
Reset the count value.

As is clear from the above, when comparison pulses are periodically sent out from the slave phase comparison circuit 10, the pulse interval of the output pulses of the comparison circuit 112 changes according to the numerical value set by the numerical value setting device 113. That is, when the set numerical value is small, the pulse interval is small. Therefore, this corresponds to reducing the integration constant.

Then, as the set value increases, the pulse interval increases. This corresponds to increasing the integration constant.

The set numerical value of the numerical value setter 113 is set by the arithmetic unit 114.

The computing unit 114 computes the degree of divergence of the time difference line in the vicinity of point P where the own ship is located, for example in FIG. This degree of divergence is expressed by using the angle φ formed by the master transmitting station M and the slave transmitting station S with respect to the own ship position P. Therefore, by predetermining the set numerical value when positioned on the base line BL,
The set numerical value may be changed based on the set numerical value.

The arithmetic unit 114 changes the set numerical value by calculating the numerical value setting row as described above.

In this case, the angle φ can be calculated from a trigonometric formula by giving the position data of the ship's position P and the position data of the Loran transmitting stations M and S. The position data of the own ship is given by the latitude/longitude converter 12, and the position data of the Loran transmitting stations M and S is given by reading the position data stored in advance in the data memory 13.

The latitude/longitude converter 12 converts own ship position data on the Loran chart sent from the time difference measuring circuit 14 and a time difference measuring circuit that measures the time difference between another pair of Loran signals (not shown) into latitude/longitude data on the map. Convert. This conversion of latitude and longitude data is performed in a known manner by calculating the distance to the Loran transmitting station using the time difference data on the Loran chart and the position data of the Loran transmitting stations M and S. Note that the 1-time difference measuring circuit 14 is
When the master station synchronization pulse and slave station synchronization pulse generated by the master station synchronization pulse generation circuit 3 and the slave station synchronization pulse generation circuit 9 are synchronized with their respective Loran signals, the time difference between the master station synchronization pulse and the slave station synchronization pulse Take measurements.

(Effect of the invention) As is clear from the above explanation, the cumulative number when calculating the detection output of the phase shift between the synchronization pulse and the Loran signal is set to the optimal value corresponding to the own ship's position on the Loran chart. Ru. Therefore, synchronization between the synchronization pulse and the Loran signal will not be delayed due to the movement of the own ship, and the synchronization of the Loran signal will not be delayed.
Even when the /N ratio is relatively poor, it is extremely stable.

(Other Embodiments of the Invention) In FIG. 1, it has been explained that the AFC circuit 6 controls the reference oscillator 1 using the phase comparison output of the master station synchronization pulse and the master station Loran signal, but the slave station synchronization pulse and the slave station Even if the phase comparison output with the Loran signal is sent to the AFC circuit, the same effect as described above can be performed. Therefore, in this case, it is sufficient to send the phase comparison output between the main station synchronization pulse and the main station Loran signal to the integrator 11.

In addition, in FIG. 1, the integrator 11 is a reversible counter 111,
Although the configuration includes the comparison circuit 112, the numerical value setter 113, etc., the configuration is not limited to this and various modifications are possible.

Further, there is no need to use a hardware configuration, and each data can be configured to be processed using software.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, FIG. 2 shows a waveform diagram for explaining its operation, and FIG. 3 shows an example of a Loran chart for explaining its operation. 1...Reference oscillator, 2...Main station frequency divider, 3...
...Main station synchronous pulse generation circuit, 4...Main station phase comparison circuit, 5...Receiver, 6...AFC circuit, 7.
...Movement circuit, 8...Slave station frequency divider, 9...Slave station-synchronous pulse generation circuit, 10...Slave station phase comparison circuit, 11...Integrator, 12... - Latitude and longitude converter, 13... Data memory, 14... Time difference measurement circuit, Ill... Reversible counter, 112... Comparison circuit, 113... Numeric value setter, 114. ...Arithmetic unit

Claims (1)

[Claims] A reference pulse train is frequency-divided until it has the same period as the arrival period of the Loran signal to generate a master station synchronization pulse and a slave synchronization pulse, and each of the master station synchronization pulse and slave synchronization pulse is applied to the master station Loran signal. In the Loran receiver, which is synchronized with the Loran signal of the slave station, a first phase comparison circuit that performs a phase comparison between the master station (slave station) synchronization pulse and the master station (slave station) Loran signal, and the slave station (master station)
a second phase comparison circuit that performs a phase comparison between the synchronization pulse and the slave station (main station) Loran signal; a frequency control circuit that controls the number of pulses of the reference pulse train based on the first phase comparison output; an integrator that integrates the two phase comparison outputs, and a moving circuit that controls the phase of a slave station (main station) synchronization pulse with which the second phase comparison circuit performs the phase comparison based on the integration output of the integrator; and an arithmetic circuit that calculates the degree of divergence of the time difference line of the Loran chart near the own ship's position based on the position data of the own ship and the position data of the Loran transmitting station, and based on the calculation result of the calculation circuit, the above-mentioned A signal tracking device for a Loran receiver, characterized in that the integration constant of an integration circuit is controlled such that the integration constant of an integration circuit increases as the divergence of the time difference line increases with reference to the position where the divergence of the time difference line is the smallest.