JPS61145832A - 低温プラズマ蝕刻方法 - Google Patents

低温プラズマ蝕刻方法

Info

Publication number
JPS61145832A
JPS61145832A JP59269851A JP26985184A JPS61145832A JP S61145832 A JPS61145832 A JP S61145832A JP 59269851 A JP59269851 A JP 59269851A JP 26985184 A JP26985184 A JP 26985184A JP S61145832 A JPS61145832 A JP S61145832A
Authority
JP
Japan
Prior art keywords
etching
semiconductor substrate
etched
plate
temperature plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59269851A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0426536B2 (https=
Inventor
Michio Harashima
原島 迪夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP59269851A priority Critical patent/JPS61145832A/ja
Publication of JPS61145832A publication Critical patent/JPS61145832A/ja
Publication of JPH0426536B2 publication Critical patent/JPH0426536B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices

Landscapes

  • Drying Of Semiconductors (AREA)
JP59269851A 1984-12-20 1984-12-20 低温プラズマ蝕刻方法 Granted JPS61145832A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59269851A JPS61145832A (ja) 1984-12-20 1984-12-20 低温プラズマ蝕刻方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59269851A JPS61145832A (ja) 1984-12-20 1984-12-20 低温プラズマ蝕刻方法

Publications (2)

Publication Number Publication Date
JPS61145832A true JPS61145832A (ja) 1986-07-03
JPH0426536B2 JPH0426536B2 (https=) 1992-05-07

Family

ID=17478076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59269851A Granted JPS61145832A (ja) 1984-12-20 1984-12-20 低温プラズマ蝕刻方法

Country Status (1)

Country Link
JP (1) JPS61145832A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943344A (en) * 1986-10-29 1990-07-24 Hitachi, Ltd. Etching method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52137266A (en) * 1976-05-12 1977-11-16 Nichiden Varian Kk Method of sputter etching

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52137266A (en) * 1976-05-12 1977-11-16 Nichiden Varian Kk Method of sputter etching

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943344A (en) * 1986-10-29 1990-07-24 Hitachi, Ltd. Etching method

Also Published As

Publication number Publication date
JPH0426536B2 (https=) 1992-05-07

Similar Documents

Publication Publication Date Title
US4585517A (en) Reactive sputter cleaning of semiconductor wafer
US3567508A (en) Low temperature-high vacuum contact formation process
US4561168A (en) Method of making shadow isolated metal DMOS FET device
US3911560A (en) Method for manufacturing a semiconductor device having self-aligned implanted barriers with narrow gaps between electrodes
GB1219986A (en) Improvements in or relating to the production of semiconductor bodies
US3663870A (en) Semiconductor device passivated with rare earth oxide layer
US3601888A (en) Semiconductor fabrication technique and devices formed thereby utilizing a doped metal conductor
US3636421A (en) Oxide coated semiconductor device having (311) planar face
US3514845A (en) Method of making integrated circuits with complementary elements
EP0160255A2 (en) Field effect transistor device and method of making same
CN111640797A (zh) 半导体器件的制作方法
CA1096052A (en) Method of manufacturing a gate turn-off thyristor
US5073506A (en) Method for making a self-aligned lateral bipolar SOI transistor
US3271636A (en) Gallium arsenide semiconductor diode and method
JPS61145832A (ja) 低温プラズマ蝕刻方法
US20070117366A1 (en) Contact method for thin silicon carbide epitaxial layer and semiconductor devices formed by those methods
US3577045A (en) High emitter efficiency simiconductor device with low base resistance and by selective diffusion of base impurities
JPS62232142A (ja) 半酸化物分離デバイスを製作するための方法
JPS60219759A (ja) 半導体集積回路装置の製造方法
EP0066675B1 (en) Processes for the fabrication of field effect transistors
US4071378A (en) Process of making a deep diode solid state transformer
US3387192A (en) Four layer planar semiconductor switch and method of making the same
JP2618921B2 (ja) 半導体装置の製造方法
JPS5773969A (en) Manufacture of semiconductor device
JP2000252290A (ja) 半導体装置とその製造方法

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term