JPS6114537B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram controller.

A typical configuration of a conventional microprogram control device, as shown in FIG.
01, a second storage means 102 for storing the address of the microprogram being executed, and a comparison means 103 for comparing the address of the first storage means 101 and the address of the second storage means 102, respectively.

For example, considering a case where a certain microprogram is being executed, the address of the microprogram being executed is stored in the second storage means 102, and the address of the microprogram being executed is stored in the first storage means 102 where it was previously stored.
is compared in the comparison means 103 with the address of
Depending on the result, an error display, a signal for starting or stopping the operation, etc. is output.

As a result, it is effective when sequentially checking microprograms according to addresses. However, in microprograms, routines are usually made extremely common and the number of steps is reduced in order to improve the performance and reduce the cost of the device.

Therefore, a problem occurs in which the contents of the general-purpose register are destroyed without the designer's knowledge.

When such a failure occurs, it is impossible for conventional devices to know the address pointing to the corrupted contents of the general purpose register.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram control device that facilitates finding the cause of failures caused by microprograms.

The apparatus of the present invention includes a first storage means for storing data consisting of a plurality of bits, a detection means for detecting a state change of the bits, and a first storage means for storing data consisting of a plurality of bits, and a first storage means for storing data consisting of a plurality of bits, and a first storage means for storing data consisting of a plurality of bits. A second one that stores the multiple addresses that you plan to use to run the
storage means; a third storage means for storing an address specifying a microinstruction being executed; and an address from the second storage means and the third storage means.
and a comparison means for comparing the address from the storage means, and is characterized in that it is possible to identify whether an error requiring a processing interruption is an error requiring a retry according to the comparison result from the comparison means. do.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

The device of the present invention includes a first register 201 for storing data, a second register 202 for storing mask information of the first register 201, a third register 203 for storing N (N≧1) program addresses,
A fourth register 204 that stores an execution address, a detection circuit 205 that detects changes in data bits or data patterns of the first register 201 that are not masked by the second register 202, N addresses of the third register 203, and a fourth register 204. a comparison circuit 206 that checks for a mismatch with the address of the detection circuit 205, an arithmetic circuit 207 that obtains a signal for displaying an error, starting or stopping an operation, etc. according to the results of the detection circuit 205 and the comparison circuit 206, and this arithmetic circuit 20.
The fifth register 208 stores information such as a program address instruction code or register contents based on the output of No. 7.

For example, if we consider a case where a certain microprogram is being executed, if a data bit or data pattern that is not masked by the mask information of the second register 202 among the data stored in the first register 201 changes, the third When the N microprogram addresses stored in the register 203 and the microprogram address being executed stored in the fourth register 204 do not match, information such as the program address, instruction code, or register contents is stored in the fifth register 208. start or stop doing something.

Next, the detection circuit 205, the comparison circuit 206, and the arithmetic circuit 207 will be explained in more detail.

The detection circuit _{205 shown} in FIG. 3 register 20
Each bit an ₁ -ane of the n-th address of 3 and each bit b ₁ -be of the output of the fourth register 204 are provided. Furthermore, when the contents of the first register change, the detection circuit 205 is configured to store the contents.
JK flip-flops F ₁₁₁ to _{F 11} k, exclusive OR circuits G ₁₁₁ to _{G 11} k, exclusive OR circuits for calculating the exclusive OR of corresponding bits from the flip-flops F ₁₁ k and data dk from the first register. Circuit G ₁₁₁ ~
an OR circuit that performs the logical sum of corresponding bits from the outputs of the NOT circuits I ₁₁₁ to _{I 11} k given the outputs of G ₁₁ k, and the outputs of the NOT circuits I ₁₁₁ to I ₁₁ k and the outputs of the second registers m ₁ to mk; G ₁₂₁ ~ G ₁₂ h, AND circuit G ₁₃₁ and AND circuit G ₁₃₁ which takes the output AND of AND circuit G ₁₂₁ ~ G ₁₂ k
Comparison circuit ₂
06 is the output an ₁ ~anl (n=
1 to n) and the output b ₁ to be of the fourth register 204, an exclusive OR circuit G ₂ n ₁ to G ₂ nl (n=1 to n), Inverting circuit I ₂ n ₁ - I ₂ nl (n=1 - n) of the output of OR circuit G ₂ n ₁ - G ₂ nl (n=1 - n), inverting circuit G ₂ n ₁ - _{G 2} nl
(n = 1 to n) output logical product circuit G ₃₁ n (n = 1
~ n), an OR circuit G 321 of the output of the AND circuit G ₃₁ n (n ₌ 1 _{to n), and a NOT circuit G 331 of} the output of the OR circuit G 321; Output of negation circuit I ₁₂₁ and comparison circuit 2
AND circuit G ₄₁₁ with the output of NOT circuit G ₃₃₁ in 06
have.

When the data dk of the first register 201 is not masked, that is, when the mask bit mk is "0", the detection circuit 205 detects an exclusive signal when the output F ₁₁ k of the JK flip-flop and the output value of the first register dk match. The output of the logical sum G ₁₁ k is “0”, the output of the negative circuit I ₁₁ k is “1”, the logical sum circuit
The output of G ₁₂ k becomes “1”. If the data dk is masked, i.e. mask bit mk
is "1", the output of the OR circuit G ₁₂ k is always "1".

Therefore, if even one bit of unmasked data dk changes, the output of AND circuit G ₁₃₁ becomes "0", the output of NOT circuit I ₁₂₁ becomes "1", and the values of data d ₁ to dk become JK. Flip Flop F ₁₁₁ ~ _{F 11} k
is set to Also unmasked data
If dk does not change, the output of the AND circuit G ₁₃₁ is “1” and the output of the NOT circuit I ₁₂₁ is “0”, and the data
The values of d ₁ -dk are not set in the JK flip-flops F ₁₁₁ -F ₁₁ k. Furthermore, the comparison circuit 206 includes the exclusive OR circuits G ₂ n ₁ to _{G 2} nl (n=1 to n), the NOT circuits I ₂ n ₁ to I ₂ nl (n=1 to n), and the AND circuit G ₃₁₁ ,
It consists of an OR circuit G ₃₂₁ and a NOT circuit G _331. When the address anl and the execution address BL match, the output of the exclusive OR G ₂ nl is “0” and the NOT circuit
The output of I ₂ nl becomes "1".

Therefore, when the corresponding bits of the pre-stored addresses an ₁ to anl and the execution addresses b ₁ to bl all match, the outputs of the AND circuit G ₃₁ n and the OR circuit G ₃₂₁ are “1”, and the output of the NOT circuit G is “1”. The output of ₃₃₁ becomes "0". Conversely, if the n pre-stored addresses (n≧1) and the execution address do not match, the output of the NOT circuit G ₃₃₁ becomes "1".

Therefore, the output of the arithmetic circuit 207 composed of the AND circuit G ₄₁₁ is the unmasked data dk.
(k=1 to k) changes, n prestored addresses an ₁ to anl (n
It becomes "1" only when the corresponding bits of the addresses b ₁ -bl that are being executed do not match with each other (=1 to n), and becomes "0" in other cases.

As explained above, the present invention has the advantage that it is possible to easily find the cause of a failure caused by a microprogram.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a conventional microprogram control device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a detector 205 and a comparator 206 shown in FIG. , computing unit 20
7 is a detailed circuit diagram.

Claims (1)

[Scope of Claims] 1. A first device that stores data consisting of a plurality of bits.
a detection means for detecting a change in the state of the bits constituting the data; and, before executing a microprogram consisting of a plurality of microinstructions, storing an address of a compound instruction to be used for executing the microprogram. Second to do
storage means for storing an address specifying a microinstruction being executed; and a third storage means for storing an address specifying a microinstruction being executed;
and a comparison means for comparing the address from the storage means of the bit, and when the detection means detects a change in the state of the bit, it is determined whether there is an error requiring processing interruption or a retry, depending on the comparison result from the comparison means. A microprogram control device characterized by being able to identify whether an error occurs.