JPS6114534B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that performs microinstruction timing stopping and restarting operations.

When performing some kind of control operation of a microinstruction due to an event that occurs asynchronously with respect to the microinstruction timing (timing for executing a microinstruction), the occurrence of the asynchronous event is detected by some means and the control microinstruction routine is executed. Must be started.

A common method for detecting an asynchronous event is to branch the microinstruction control sequence by executing a conditional microinstruction that uses the occurrence of an asynchronous event as a jump condition.
In this method, it is necessary to detect the occurrence of an asynchronous event.
Requires microinstruction cycles.

This method is fine if there is sufficient time from the occurrence of an asynchronous event to the start of control operations, but a faster response is required in data transfers for magnetic disk drives that require extremely high-speed control operations. Ru.

In such a case, a method can be considered in which the execution of microinstructions is stopped when waiting for an asynchronous event, the occurrence of the asynchronous event is detected by hardware, and the execution of the microinstructions is resumed. The microinstruction address is set so that the microinstruction or microinstruction routine that is immediately resumed is for controlling this asynchronous event.

The execution of a microinstruction may be stopped based on a designation of the microinstruction itself, or may be based on other conditions such as the number of executed microinstructions reaching a predetermined number.

Control of stopping and restarting the execution of microinstructions is realized by stopping and restarting the timing sequence for microinstruction execution control (hereinafter referred to as microinstruction timing).

However, as mentioned above, there is a restriction that the generation of the microinstruction timing signal must be stopped when waiting for an asynchronous event, and depending on the asynchronous event interval and the execution time of one microinstruction, Since the number of microinstructions that can be executed for control is determined automatically, the next asynchronous event is forced to wait a little longer, and a slightly larger number of microinstructions than usual cannot be executed in response to the asynchronous event being controlled.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that eliminates the above-mentioned drawbacks and makes effective use of microinstructions.

A data processing device that executes a microinstruction using an asynchronous signal as a starting condition, comprising: storage means for storing the asynchronous signal; and a display that displays a generation state of a timing signal that is set based on the asynchronous signal and causes the microinstruction to be executed. means, while the generation of the timing signal is displayed by the display means, the generation of the timing signal is continued by the stored asynchronous signal even if a stop instruction signal is given to the microinstruction being executed. It is characterized by being made to do.

Next, the present invention will be explained using a magnetic disk device as an example with reference to the drawings. In the following description, restarting the generation of microinstruction timing is simply referred to as restart. Asynchronous events in a magnetic disk device include a data transmission request signal, an index mark signal, etc. given from the magnetic disk device.

FIG. 1 is a diagram showing a microinstruction timing generation circuit and restart storage circuit according to the present invention.

The restart condition setting register 11 contains mask bits for a plurality of asynchronous events that cause the generation of the microinstruction timing signal to be resumed, and is set by the microinstruction. For example, if a restart condition based on a data transfer request signal is set in the restart condition setting register 11 by a microinstruction, when the signal 111 becomes "1" and the data transfer request signal 121 becomes "1",
A restart signal 122 is generated at the AND gate 12. At this time, even if the index mark signal 131 becomes "1", the signal 112 is "0", so the AND
The restart signal 132 is not output from the gate 13. The restart memory flip-flop 15 is
It is set to "1" when the input signal 141 rises,
When the output signal 201 of the restart signal storage flip-flop preset signal circuit 20 becomes "1", the restart storage flip-flop 15 is generated by the stop signal 191 generated when the microinstruction timing is restarted or specified by a microinstruction. Set to “0”. The flip 18 indicating that the micro-instruction timing is in operation is set to "1" when the input signal 171 is "1" at the rising edge of the basic clock generating circuit 16, which is obtained by dividing one cycle of the micro-instruction timing by N.

Reset signal 192 for flip-flop 18
is the “1” state of the signal 221 obtained by inverting the output signal 151 of the flip-flop 15 by the inverting circuit 22, that is, the output signal 1 of the flip-flop 15.
It becomes "1" only when the signal 51 is "0" and the stop signal 191 generated by the specification of the microinstruction is "1". When the output signal 181 of the flip-flop 18 is "1", the microinstruction timing generation circuit 21 generates microinstruction timing signals 211, 212, 21 from the basic clock 161.
3 and 214 in a defined order and pulse width.

The time chart in FIG. 2 shows the operation when a restart signal is generated while waiting for a restart signal after the microinstruction timing has completely stopped. The operation will be further explained with reference to FIG.

A basic clock 161 having a period corresponding to four divisions of one cycle of microinstruction timing is constantly generated by the basic clock generating circuit 16. Since the basic clock generation circuit 16 needs to generate a basic clock with a stable period, an oscillation circuit using a crystal oscillator is used. The microinstruction timing generation circuit 21 in FIG. 1 operates in synchronization with the basic clock 161, and when the output signal 181 of the flip-flop 18 becomes "1", the microinstruction timing generation circuit 21 from the basic clock 161 generates microinstruction timing signals 211, 212, 213, and 214 in a predetermined order and pulse width. When the output signal 181 of the flip-flop 18 becomes "0", the microinstruction timing 211, 212, 21 that is being generated
3 and 214 are output normally until the end of that cycle, but no microinstruction timing signal is generated for the next new microinstruction cycle. Taking the case of controlling a data transfer request from a magnetic disk device as an example, the microinstruction sets the restart condition setting register 11 so that a restart is possible in response to a data transfer request signal 121 from the magnetic disk device. Then execute an instruction that stops microinstruction timing. When this command is executed, the signal 191 becomes "1". Therefore, the flip-flop 18 indicating that the microinstruction timing operation is in progress due to the execution of the above instruction is an AND
From the signal 192 given through the gate 19,
The restart storage flip-flops 15 are each reset to "0" by a signal 201 applied via the restart storage flip-flop preset circuit 20. Microinstruction timing generation is stopped at the end of the cycle at this reset point.

When the data transfer request signal 121 indicating a data transfer control request from the magnetic disk device becomes "1"
The input signal 122 of the OR gate 14 becomes "1" through the AND gate 12, and then the input signal 122 of the OR gate 14 becomes "1".
input signal 141 of flip-flop 15 via
becomes “1”. When the signal 141 rises, the flip-flop 15 becomes "1", and when the output signal 151 becomes "1", the input signal 171 of the flip-flop 18 becomes "1" via the OR gate 17.

When the input signal 171 of the flip-flop 18 becomes "1", the flip-flop 18 becomes "1" at the rising edge of the basic clock 161, which is obtained by dividing one cycle of the microinstruction timing into four. Once the flip-flop 18 becomes "1", the input signal 1 of the flip-flop 18 is passed through the OR gate 17.
71 is always “1” and flip-flop 18
holds the state of "1". This flip-flop 18 opens the AND gate 19 only when the micro-instruction timing stop signal is received by the micro-instruction.
It is reset to "0" via .

When flip-flop 18 becomes "1", flip-flop 15 is reset to "0" by signal 201 from restart storage flip-flop preset circuit 20. Further, when the flip-flop 18 becomes "1", the micro-instruction timing generation circuit 17 outputs the micro-instruction timing signals 211, 212, 213 and 214 as described above.
are sent sequentially to execute microinstructions.

FIG. 3 is a time chart showing the operation when storing a restart signal, which is a feature of the present invention. Data transfer control request signal 1 from the magnetic disk device when microinstruction timing generation is stopped.
21 is applied, and the restart signal 141 becomes "1". When the input signal 141 of the flip-flop 15 rises, the flip-flop 15 becomes "1", and when the output signal 151 and the input signal 171 become "1", the flip-flop 18 becomes "1" when the basic clock 161 rises, as described above. As a result, the restart memory flip-flop preset signal 201 becomes "1" and the flip-flop 1
5 to "1" and the microinstruction timing generation circuit 21 outputs microinstruction timing signals 211, 212, 213, and 214.
are sent out sequentially to execute microinstructions.

Next restart signal 1 while executing microinstruction
41 is applied, the flip-flop 15 is set to "1" at the rising edge of the restart signal 141. When the instruction to stop the microinstruction is executed in this state, the signal 191 becomes "1", but the output signal 151 of the flip-flop 15 is "1", the output signal 221 of the inverter 22 is "0", and the output signal 151 of the flip-flop 15 is "0". Reset signal 192
does not occur and flip-flop 18 is not reset to "0". As a result, the instruction that stops the microinstruction timing becomes invalid, and the next microinstruction is subsequently executed.

In addition, the microinstruction timing stop signal 191
In response to becoming "1", the signal 201 from the restart storage flip-flop preset circuit 20 becomes "1" at the end of the cycle;
Flip-flop 15 is reset to "0",
Wait for the next restart signal. In the case of this embodiment, by having one restart memory flip-flop 15, only one restart can be stored, but by having two or more restart memory flip-flops, two restarts can be stored. More than 1 restart signal can be stored. however,
It goes without saying that the optimum number should be selected depending on the operating speed of the circuit elements used, the object to be controlled, etc.

As described above, according to the present invention, by using a restart memory circuit at the start of a microinstruction control operation for an asynchronous event, it is possible to provide flexibility in limiting the microinstructions that can be executed between asynchronous events.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG.
3 and 3 are diagrams for explaining the operation of FIG. 1. 1 to 3, 11...Restart condition setting register, 12, 13...AND gate, 14, 17...OR gate, 15...Restart, memory flip-flop, 16...Basic clock generation circuit , 18...Flip-flop indicating microinstruction timing operation, 19...AND
Gate, 20... Restart memory flip-flop preset circuit, 21... Micro instruction timing generation circuit, 22... Inverter.

Claims (1)

[Claims] 1. A basic clock generation circuit that generates a basic clock obtained by dividing one cycle of microinstruction timing into N, a restart condition setting register in which a restart condition is set by the microinstruction, and an asynchronous signal corresponding to the restart condition. a restart storage flip-flop that is set by a restart signal generated when the basic clock is applied, and a restart storage flip-flop that is reset by a reset signal; a microinstruction timing active instruction that is reset when a stop signal is provided that is generated in response to execution of a microinstruction for stopping the microinstruction timing while the restart memory flip-flop is being reset; a flip-flop, a restart storage flip-flop preset circuit for generating the reset signal when the micro-instruction timing active instruction flip-flop is set and when the stop signal is provided; and a micro-instruction timing active instruction circuit; A data processing device comprising: a microinstruction timing generating circuit that restarts the microinstruction timing when a flip-flop is set and stops the microinstruction timing at the end of the microinstruction timing when the flipflop is reset.