JPS61144862A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To contrive to reduce occupied area of a memory cell connecting without necessity of mask alignment by a method wherein a conductive layer of a capacity element and prescribed semiconductor region of MISFET for switching are connected with a conductive layer which is different from the above-stated layer. CONSTITUTION:A capacity element to constitute a memory cell is constituted by P<+> type semiconductor region 7, an insulated film 8 and a conductive layer 9. MISFETQ used as a switching element of the memory cell is constituted of a gate insulated film 4, a gate electrode 5 and a semiconductor region 6. The region 6 and the layer 9 are connected with a conductive layer 11 which is provided on the upper face of the region 6 and at the prescribed upper face and the side section of the layer 9. The end section on the region 6 of the layer 11 is prescribed by a side wall 10. By this fact, the layer 11 can be formed on the layer 9 and the layer 6 without the use of a mask. Accordingly, margin of mask alignment between the layer 11 and the electrode 5 and between the layer 9 and the layer 11 are unnecessary.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor memory device, and particularly to a technique effective when applied to a dynamic random access memory (D-RAM).

[Background technology]

A capacitive element constituting a memory cell of a DRAM stores electric charges that serve as information by accumulating minority carriers in an inversion layer formed on the surface of a semiconductor substrate. When unnecessary minority carriers generated due to alpha resistance etc. enter the inversion layer, the amount of charge serving as information changes.゛In order to prevent the influence of unnecessary minority carriers, a highly concentrated p-type semiconductor region is provided on the surface of a semiconductor substrate, and a capacitive element is composed of the semiconductor region, an insulating film provided thereon, and a conductive layer on the insulating film. has been proposed (patent application 1982-21)
No. 0825). The conductive layer needs to be made independent for each memory cell and connected to one semiconductor region of the switching MISFET.

In the capacitive element according to the above proposal, the inventor further found that the DRA
We have discovered a problem in that it is difficult to achieve high integration of M.

The memory cell according to the above proposal connects the conductive layer of the capacitive element and the semiconductor region of the MI 5FET through a connection hole formed by selectively removing the insulating film on the half-structure region of the MISFET. The connection hole needs to be separated from the gate electrode by a distance greater than the mask alignment margin in order to prevent the gate electrode of the MISFET from shorting with the conductive layer of the capacitive element. Furthermore, the connection hole needs to be sufficiently separated from the p-type semiconductor region provided on the surface of the semiconductor substrate to constitute the capacitive element by a distance greater than the mask alignment margin. This is to prevent the conductive layer forming the capacitive element from being unnecessarily connected to the p-type semiconductor region.

In other words, it is difficult to achieve high integration of DRAMs due to mask alignment margins between the connection hole and the gate electrode, and between the connection hole and the p-type semiconductor region.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a technology that enables high integration of DRAM.

Another object of the present invention is to provide a technique that allows a conductive layer provided on a semiconductor substrate to be connected to a predetermined semiconductor region of a MISFET without requiring a mask alignment margin in order to configure a capacitive element. It is in.

Another object of the present invention is to provide a technique that enables good electrical connection between a conductive layer provided on a semiconductor substrate to constitute a capacitive element and a predetermined semiconductor region of a MISFET. be.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the conductive layer of a capacitive element including a p-type semiconductor region, an insulating film provided on the semiconductor region, and a conductive layer provided on the insulating film, and a predetermined semiconductor region of a switching MISFET are different from those described above. The conductive layer eliminates the need for a mask alignment margin and connects the memory cell at 0.degree. C., thereby reducing the area occupied by the memory cell and improving the degree of integration of the DRAM.

Next, the configuration of the present invention will be explained together with examples.

In all the drawings for detailed explanation of the present invention, parts having the same functions are denoted by the same reference numerals, and repeated explanation thereof will be omitted.

[Example I]

In this embodiment, seven structures and manufacturing methods of DRAM memory cells will be explained.

FIG. 1 shows a DRAM for explaining Embodiment I of the present invention.
FIG. 2 is an equivalent circuit diagram showing a main part of a memory cell array of FIG.

In FIG. 1, SA, SA, . . . are sense amplifiers for amplifying a minute potential difference between a predetermined memory cell and a predetermined dummy cell, which will be described later. BL+t - BL+t is a bit line extending from one end of the sense amplifier SA in the row. BL□, BL
□ is a bit line extending in the row direction from one end of the sense amplifier SAt. These pics! The BL is for transmitting charges that serve as information. WL,,WL,
is a word line extending in the column direction, which is connected to a predetermined gate electrode constituting a switching MISFET of a dummy cell to be described later, and is used to turn on and off the MISFET. Word lines WL, . . . WL4 extend in the column direction, and are connected to predetermined gate electrodes constituting switching MISFETs of memory cells, which will be described later, to turn on and off the MISFETs.

JI, Mll, MH, MH... songs are memory cells that hold electrical charges that serve as information.

Memories/L/M is MI SF ETQ++, Q
tt -Q□, Qo,..., and capacitive element CII
+ ct*p C□.

C! ! It consists of... MISFET
One end of Q is connected to a predetermined pin line BL, and the gate electrode is connected to a predetermined word @WL. The capacitive element C is
One end is connected to a different end of MISFETQ,
The other end is at ground potential (0 (V)) or substrate bias potential (-
It is connected to a fixed potential v8s terminal such as 2,5 to -3,o[:V]).

D,,,D,! ,D,,,D,,...The song is a dummy cell, and it is designed to hold a charge that can determine the information of the memory cell M, 1'', ''0''.The dummy cell D is , MISFETQD, ,IQD121 QD
2□+ QD22 +... and capacitive element CD
1llC, C, C... and MID1 for clearing
2 D21 D22%5FETCQ. MISFETQD has one end connected to a predetermined bit line BL6C and a gate electrode connected to a predetermined word line WL. One end of capacitive element CD is MISF
It is connected to one end of the ETQD different from the above, and the other end is connected to the fixed potential vss terminal. MI 5FET for clear
CQ is for clearing the charge accumulated in the capacitive element CD.

φ0 is a terminal connected to the gate electrode of the clear MI 5FETCQ.

Next, a specific structure of Example I of the present invention will be explained.

2 to 4 are diagrams for explaining the structure of the DRAM of Example 1117. The second cause is a plan view of the memory cell of the DRAM, and FIG. FIG. 4 is a sectional view taken along the section line m--KV in FIG. 2.

Note that, in order to make the configuration of the memory cell easier to see, FIG. 2 does not illustrate the insulating film provided between the conductive layers.

2 to 4, 1 is a semiconductor substrate made of p-type single crystal silicon, and a field insulating film 2 is provided on a predetermined surface portion in a pattern as shown by dotted lines in FIG. A p+ type channel stopper region 3 is provided below this.

Q is a MISFET, which is used as a switching element of a memory cell. MISFETQ has a gate insulating film 4. Gate electrode5. It consists of a semiconductor region 6 used as a source region or a drain region and a channel region.

The gate insulating film 4 is provided on the semiconductor substrate l between the field insulating films 2. Gate insulating film 4 is made of silicon oxide film. The gate electrode 5 consists of five conductive layers provided on the gate insulating film 4 and a conductive layer 5B thereon. The five conductive layers are made of polycrystalline silicon, and the conductive layer 5B is made of an alloy (silicide) of silicon and a high melting point metal such as titanium.

The gate electrode 5 is formed integrally with a word line WL extending on an insulating film 12, which will be described later (hereinafter, the direction in which the word line WL extends is referred to as a row direction). In this embodiment, the conductive layer 5B made of silicide is provided in order to lower the resistance of the word class WL, but it is not necessarily necessary to provide it. The semiconductor region 6 consists of an n − type semiconductor region 6A and an n + type semiconductor region 6B.

The six semiconductor regions are for relaxing the electric field near the drain region and reducing the generation of hot electrons. A predetermined semiconductor region 6B extending in the column direction and to which the conductive layer 15 used as the bit line BL is electrically connected is a MISF to which the conductive layer 15 is connected through the same connection hole 14.
It has an integral structure with the semiconductor region 6B of ETQ.

The remaining capacitive element C constituting the memory cell M is composed of a p+ type semiconductor region 7, an insulating film 8 used as a dielectric, and a conductive layer 9. The semiconductor region 7 is a capacitive element C
It is provided near the surface of the semiconductor substrate 10 in the formation portion and is integrally configured with the capacitive element C adjacent in the column direction. The semiconductor region 7 has a high concentration in order to obtain as much charge as possible to be stored in the capacitive element C. The semiconductor region 7 is for electrically isolating capacitive elements C adjacent in the column direction. p+ type semiconductor region 7
It is preferable to provide it separately from the n+ type semiconductor region 6B in order to avoid a decrease in the junction breakdown voltage. The insulating film 8 includes eight insulating films provided on the semiconductor substrate 1 and an insulating film 8B thereon.
It consists of

The eight insulating films are made of silicon oxide films, and the insulating film 8B is made of a silicon nitride film. Note that a thin silicon oxide film (not shown) is provided on the upper surface of the insulating film 8B. This silicon oxide film improves dielectric breakdown voltage by blocking pinholes in the insulating film 8B. The conductive layer 9 is provided on the insulating film 8 in a pattern as shown by solid lines in FIG.

As shown in FIG. 3, the conductor is formed so that its periphery is tapered. This is to prevent an unnecessary insulating film from being formed on the side of the conductive layer 9 during the process, which will interfere with the formation of the conductive layer 11, which will be described later. There is no particular need for the portion to be tapered because the thickness of the insulating film 8 is extremely thin.

A conductive layer 11 is provided on the upper surface of the semiconductor region 6B and a predetermined upper surface and side portion of the conductive layer 90 so that the semiconductor region 6B and the conductive layer 9 can be electrically connected well.

The conductive layer 11 is formed by reacting the semiconductor region 6B and the conductive layer 9 with a high melting point metal provided on the upper surfaces thereof. The end of the conductive layer 11 on the semiconductor region 6B is defined by the sidewall 10. Further, an end portion of the conductive layer 11 on the conductive layer 9 is defined by an insulating film 12 described later. From these facts, the conductive layer 1
1 can be formed on conductive layer 9 and semiconductor region 6B without using a mask. Mask alignment margins between conductive layer 11 and gate electrode 5 and mask alignment margins between conductive layers 9 and 11 can be made unnecessary. Therefore, since the distance between the gate electrode 5 and the conductive layer 9 (capacitive element C) can be reduced, the area occupied by the memory cell can be reduced.

When MISFETQ becomes conductive by setting the gate electrode 5 to "H" level (for example, s, o (V)),
The potential of conductive layer 15 (BL) is applied to conductive layer 9 through conductive layer 11 . At this time, if the conductive layer 15 is at the "H" level, for example, s, 0 (V), the "H" potential is stored in the conductive layer 9 as information. When the conductive layer 15 is at the 'L' level (eg, ocV), the 'L' potential is stored in the conductive layer 9.

On the other hand, the conductive layer 11 is also provided on the semiconductor region 6B to which the conductive layer 15 is electrically connected. This conductive layer 11 is
This is for reducing the sheet resistance on the upper surface of the semiconductor region 6B.

Reference numeral 12 denotes an insulating film, which is provided on the semiconductor substrate 1 to cover the conductive layer 9. Note that the insulating film 12 is selectively removed in the area where the MISFETQ is formed.

The insulating film 12 is for insulating the word line WL and the conductive layer 9.

Reference numeral 13 denotes an insulating film, which is provided over the entire surface of the semiconductor substrate 1. The conductive layer (BL) 15 is electrically connected to a predetermined semiconductor region 6B through the connection hole 14.

16 is a protective film that covers the conductive layer 15 and protects the semiconductor substrate 1.
It is provided at the top.

Next, a specific manufacturing method of this example will be explained.

5 to 12 are diagrams for explaining the method of manufacturing the DRAM of this embodiment, and FIGS.
The figure is a plan view of a DRAM memory cell in the manufacturing process, FIG. 7 is a sectional view taken along the cutting line ■-■ in FIG. 6, and FIGS. 9, 10, 11 and 12 are FIG. 3 is a cross-sectional view of a main part of a DRAM memory cell in a process.

First, a p-type impurity, such as boron, for forming the p+-type channel stopper region 3 is introduced into a region where a field insulating film 2, which will be described later, is provided.

Next, as shown in FIG. 5, the surface area shown on the actual boat is selectively oxidized by a thermal oxidation technique to form a field insulating film 2 having a thickness of about 1000 to 2000 angstroms (A). The thermal oxidation mask used when forming the field insulating film 2 is composed of a silicon oxide film and a silicon nitride film provided thereon. The silicon oxide film constituting the mask is formed by oxidizing the surface of the semiconductor substrate 10. A silicon nitride film formed by, for example, CVD technology is used. In a thermal oxidation step for forming field insulating film 2, the p-type impurity introduced into the surface of semiconductor substrate 1 is diffused to form channel stopper region 3.

Next, a p-type impurity, such as poron, for forming the semiconductor region 7 is introduced into the surface other than the region surrounded by the dashed line in FIG. This p-type impurity is introduced by ion implantation using a silicon oxide film obtained by oxidizing the semiconductor substrate 1 and a resist film formed thereon as a mask. p
The type impurity is the semiconductor region 7 that constitutes the capacitive element C.
10'' [atoms/c+
Introduce at a dose of about 4]. Note that the area surrounded by the one-dot chain line is an area where MISFETQ is provided.

A dedicated heat treatment process for activating and diffusing the p-type impurity introduced into the semiconductor substrate 1 is not provided. This is because it is sufficiently diffused during the heat treatment process for forming the insulating film 4, the gate insulating film 4, or the source region and drain region, which will be described later.

After the step of introducing the p-type impurity shown in FIG.
As shown in the figure and FIG. 7, an insulating film 8A is formed over the entire surface of the semiconductor substrate 1. As shown in FIG. These eight insulating films are used as a melting body of the capacitive element C. The insulating film 8 uses a silicon oxide film obtained by thermally oxidizing the upper surface of the semiconductor substrate 1.
[:A] Form to a certain thickness. Next, in order to form an insulating film 8B, a silicon nitride film is formed over the entire surface of the insulating film 8. This silicon nitride film is formed to have a thickness of about 200 mm (A3) by CVD technology, for example. The insulating film 8B is mainly used to increase the dielectric constant of the insulating film 8. Next, the pins of the insulating film 8B In order to improve the dielectric breakdown voltage by blocking the holes, the insulating film 8B is oxidized to form a silicon oxide film.This silicon oxide film is formed to a thickness of about 30 (A).Insulating The film 8 consists of an insulating film 8A, an insulating film 8B thereon, and a silicon oxide film formed by oxidizing the insulating film F8B. Not shown.

Next, in order to form a conductive layer 9, a polycrystalline silicon layer obtained by CVD technology is applied over the entire surface of the semiconductor substrate 1.
The polycrystalline silicon layer is formed to a thickness of approximately 3000 (A). An n-type impurity, such as phosphorus, is introduced into this polycrystalline silicon layer. This n-type impurity reduces the resistance value. Introduced by heat diffusion technology.

Furthermore, arsenic (As) is added to the upper surface of the polycrystalline silicon layer.
) or argon (Ar) is introduced at a dose of about 10'' (atoms/di) or more by ion implantation technology.

This is to make the etching rate of the upper part of the polycrystalline silicon layer higher than that of the lower part in the step of patterning the polycrystalline silicon layer. That is, arsenic or argon introduced into the polycrystalline silicon layer is used to make the tapered portion of the conductive layer 9 as gentle as possible.

Next, unnecessary portions of the polycrystalline silicon layer are etched to form a conductive layer 9 having a pattern as shown in FIG.

In the etching process, an isotropic dry etching technique is used to form the periphery of the conductive layer 90 into a tapered shape, as shown in FIG. For example, a resist is used as a mask for the etching process for forming the conductive layer 9.

Since arsenic or argon is introduced into the upper surface of the polycrystalline silicon layer for forming conductive layer 9, the etching rate of the upper part of the polycrystalline silicon layer is higher than that of the lower part. The concentration of arsenic or argon inside the polycrystalline silicon layer is
It decreases as it gets deeper from the top. As the impurity concentration decreases, the etching rate decreases. On the other hand, in the isotropic etching technique, etching also progresses in the planar direction. Since the impurity concentration decreases in the deeper part of the polycrystalline silicon layer, the etching rate in the planar direction becomes slower in the deeper part of the polycrystalline silicon layer.

From the above, by introducing arsenic or argon into the upper surface of the polycrystalline silicon layer and etching it using an isotropic etching technique, it is possible to form a tapered shape around the conductive layer 90.

The reason why the peripheral portion of the conductive layer 90 is formed into a tapered shape is to prevent unnecessary sidewalls from being formed on the sides of the conductive layer 9, especially in the portion where the conductive layer 11 is provided, during the process of forming the sidewall 10. This is to prevent

By forming the periphery of the conductive layer 90 into a tapered shape, the flatness of the insulating film 12 provided thereon can be improved. This can reduce the constriction at the stepped portion of the word line WL extending on the insulating film 12 and prevent disconnection.

After forming the conductive layer 9 shown in FIGS. 6 and 7, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 in order to form an insulating film 12, as shown in FIG. This silicon oxide film can be formed with a thickness of 3000 nm by, for example, CVD technology.
It is formed to a film thickness of about (A). Next, 10" (atoms/ad
) should be introduced at a dose of at least about The purpose of this impurity is to make the etching rate of the upper part of the silicon film higher than that of the lower part in an etching process for forming openings 17, which will be described later. Next, the silicon oxide film in the region where the MISFETQ is to be provided is selectively removed to form openings 17 in a pattern as shown by solid lines in FIG. In particular, the opening 17 is formed so that a predetermined end of the conductive layer 9 is exposed. One semiconductor region 6 of MISFETQ
This is because a conductive layer 11 that electrically connects B and capacitive element C is deposited and formed. In the etching process for forming the opening 17, the peripheral portion of the insulating film 12 in the opening 17 is formed into a tapered shape. This is to prevent or at least reduce the constriction or disconnection of the word line WL at the boundary between the opening 17 and the insulating film 12. The etching process for forming the openings 17 uses, for example, an isotropic dry etching technique.

Further, as a mask for etching, for example, a resist is used.

Since arsenic or argon is introduced into the upper surface of the silicon oxide film for forming the insulating film 12, the etching rate of the upper part of the silicon oxide film is higher than that of the lower part. The concentration of arsenic or argon inside the silicon oxide film decreases as the depth increases from the top surface. As the impurity concentration decreases, the etching rate decreases. On the other hand, in the isotropic etching technique, etching also progresses in the planar direction. Since the impurity concentration decreases in the deeper part of the silicon oxide film, the etching rate in the planar direction also becomes slower in the deeper part of the silicon oxide film.

In view of the above, by introducing arsenic or argon into the upper surface of the silicon oxide film and etching it using an isotropic etching technique, a tapered shape can be formed around the insulating film 12 in the opening 17.

Note that the opening 17 can also be formed by removing unnecessary portions of the silicon oxide film using an anisotropic etching technique. Insulating film 1 using anisotropic etching technology
The peripheral portion 20 is perpendicular to the semiconductor substrate 1 .

Next, the insulating film 8 exposed by forming the opening 17 is etched to expose the surface of the semiconductor substrate 10.

As the mask for the etching step, the mask used when forming the openings 17 is used. This is to eliminate the need for a dedicated mask.

Next, in order to form the gate insulating film 4, the exposed surface of the semiconductor substrate 10 is thermally oxidized to form a silicon oxide film. This silicon illumination film is 200 to 350 CA
) to a film thickness of approximately During the thermal oxidation process for forming the gate insulating film 4, a silicon oxide film is formed on the upper surface of the exposed predetermined end of the conductive layer 90. This silicon oxide film is actively removed using an etching process for forming sidewalls 10, which will be described later.

Note that in FIG. 8, the gate insulating film 4 is not shown. After the step of forming the gate insulating film 4, a polycrystalline silicon layer is formed on the semiconductor substrate 1 in order to form the conductive layer 5A shown in FIG. Formed on the entire surface. The five conductive layers are for forming the gate electrode 5 and the word line WL. The polycrystalline silicon layer is formed using, for example, CVD technology to have a thickness of about 3000 Å in the flat portion.

In order to reduce the resistance value of the conductive layer 5A, an n-type impurity such as phosphorus is introduced into the polycrystalline silicon layer. This n-type impurity is introduced, for example, by thermal diffusion technology. next,
Five conductive layers are formed by selectively removing unnecessary portions of the polycrystalline silicon layer. The etching process for removing unnecessary polycrystalline silicon layers uses, for example, an anisotropic dry etching technique. In the etching technique described above, over-etching is performed in order to prevent unnecessary polycrystalline silicon layers from remaining in the recesses on the semiconductor substrate 1.

Due to this over-etching, the exposed predetermined end portion of the conductive layer 90 in the opening 17 is not unnecessarily etched. This is because a silicon oxide film is formed on the exposed upper surface of the conductive layer 9 using a thermal oxidation process for forming the gate insulating film 4.

The conductive layer 5A has reduced constriction by forming the side portions of the conductive layer 9 and the insulating film 12 into a tapered shape.

After forming the five conductive layers, an n-type impurity such as phosphorus is added to the semiconductor substrate 10 to form the n-type semiconductor region 6A.
Introduce it to the surface. This n-type impurity is introduced at a dose of about 10'' (atoms/d) using ion implantation technology.The mask used when introducing the impurity is a conductive layer with 5 layers in order to introduce the impurity by self-line. use

After the step of introducing impurities shown in FIG. 9, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 in order to form the sidewall 10 shown in FIG. This silicon oxide film is formed to have a thickness similar to that of the five conductive layers by, for example, CVD technology. The silicon oxide film is a conductive layer 5.
It is thicker on the sides than on the top of A. Next, using, for example, reactive ion etching (RIE) technology, the upper surface of the silicon oxide film is removed to such an extent that the upper surface of the conductive layer 5A is exposed. Since the silicon oxide film remains on the sides of the five conductive layers, sidewalls 10 can be formed. Using an etching process for forming sidewalls N10, unnecessary gate insulating film 4 on the upper surface of the region where semiconductor region 6B is provided is removed. Furthermore, the silicon oxide film on the conductive layer 9 exposed in the opening 17, which was formed when forming the gate insulating film 4, is actively removed.

Since the periphery of the conductive layer 90 is formed in a tapered shape, the conductive layer 11
No silicon oxide film for forming the sidewall 10 remains in a predetermined peripheral portion of the conductive layer 90 on which the conductive layer 90 is deposited. The silicon oxide film formed on the tapered portion of the conductive layer 9 has a thickness comparable to that of the silicon oxide film formed on the flat portion.

Therefore, it can be sufficiently removed in the etching process for forming the sidewall 10.

One feature of the present invention is that at least the portion of the conductive layer 9 over which the conductive layer 11 is provided is formed into a tapered shape.

゛Next, in order to form the n+ type semiconductor region 6B,
A type impurity, such as arsenic, is introduced into the surface of the semiconductor substrate 10. This n-type impurity is produced using ion implantation technology.
The impurity is introduced at a dose of about By performing annealing, the phosphorus and arsenic are diffused to form semiconductor regions 6A and 6B.

After forming semiconductor regions 6A and 6B shown in FIG. 10, a conductive layer 11 different from conductive layer 9 is formed to connect semiconductor region 6B and conductive layer 9.

Conductive layer 1 for connecting semiconductor region 6B and conductive layer 9
1. Compound of high melting point metal and silicon (silicide)
The use of layers is a feature of the invention.

In order to form the silicide layer, a high melting point metal layer 18 is formed over the entire surface of the semiconductor substrate 1, as shown in FIG. Specifically, the high melting point metal layer 18 uses a titanium (Ti) layer obtained by sputtering technology,
It is formed to a film thickness of about 3 mm. Moreover, the high melting point metal layer 18 is
It is used to form the conductive layer 11 on the semiconductor region 6B to which the conductive layer 15 (BL) is connected. Furthermore, the high melting point metal layer 18 is a conductive layer 5 that constitutes the gate electrode 5 (WL).
This is for forming B. After forming the high melting point metal layer 18, the entire semiconductor substrate 1 is heated to a temperature of 600 to 850°C.
]Apply a moderate amount of heat treatment. Through this heat treatment step, the silicon of the semiconductor region 6B and the conductive layer 9 is removed from the high melting point metal layer 18.
The conductive layer (silicide layer) 11 is formed by diffusing into the inside of the silicide layer. In particular, the high melting point metal layer 18 on the side of the insulating film 8 forming the capacitive element C is well converted into 7-recidation because silicon diffuses from the semiconductor region 6B and the conductive layer 9.

It is also possible to form a contact hole in the insulating film to be provided on the semiconductor region 6B, and to connect the semiconductor region 6B and the conductive layer 9 through the contact hole by a conductive layer different from the conductive layer 9. However, in such a method, the semiconductor region 6
Mask alignment allowance is required between the connection hole provided on B and the gate electrode 5, and between the connection hole and the conductive layer 9.

However, in the present invention, since the silicide layer on the semiconductor region 6B is formed by diffusing silicon from the semiconductor region 6B as described above, the silicide layer is not formed off the top surface of the semiconductor region 6B. Furthermore, the silicide layer on the side of the gate electrode 5 can be defined by the sidewall 10.

Therefore, in the present invention, no mask alignment allowance is required when forming the silicide layer.

On the other hand, silicon is diffused from the conductive layer 5 for forming the gate electrode 5 (WL) tt into the high melting point metal layer 18 thereon to form a conductive layer 5A made of silicide. Gate electrode 5 and word line WL are constituted by conductive layer 5A made of polycrystalline silicon and conductive layer 5B made of silicide.

Note that unnecessary silicide j- is not formed between the gate electrode 5 on the semiconductor substrate 1 and the semiconductor regions 6B on both sides thereof. The height difference of sidewall 10 is 300
0 (A) This is because silicon cannot be diffused into the high melting point metal layer to some extent.Also, an unnecessary silicide layer is not formed between the conductive layer 9 and the word MjWL thereon.Side This is because the wall 10 and the insulating film 12 provide sufficient separation.

After the process shown in FIG. 11, as shown in FIG. 12,
The refractory metal 18 that is no longer needed is removed by etching. The etching step may include, for example, H, O, :NH,
:H,O: Use an etching solution of 1:1:5. This etching step allows the conductive layers 5B and 11 to be separated well.

As described above, conductive layer 11 can be formed on the upper surface of conductive layer 9 and semiconductor region 6B without using a mask. Therefore, the conductive layer 11 is not formed particularly at a deviation from the upper surface of the semiconductor region 6B.

Conductive layer 11 does not require a mask alignment margin between it and gate electrode 5 and p + -type semiconductor region 7 .

That is, the conductive layer 9 and the semiconductor region 6 are connected by the conductive layer 11.
By connecting the memory cell M to the memory cell M, the area occupied by the memory cell M can be reduced.

After the step of removing the unnecessary high melting point metal layer 18 shown in FIG. 12, the insulating film 13 shown in FIG. 3 is formed. For the insulating film 13, a phosphor silicate glass film obtained by, for example, CVD technology is used. Next, the insulating film 13 on a predetermined semiconductor region 6B is selectively removed to form a connection hole 14.

The connection hole 14 is formed using, for example, an anisotropic etching technique. Next, in order to form a conductive layer 15 (BL), an aluminum layer containing silicon is formed over the entire surface of the insulating film 13. This aluminum layer is formed using, for example, a vapor deposition technique.

Further, the aluminum layer is electrically connected to the conductive layer 11 on the semiconductor region 6B through the connection hole 14.

Next, unnecessary portions of the aluminum layer are selectively removed to form a conductive layer 15 (BL) having a pattern as shown by the dashed line in FIG. Next, in order to form the protective film 16 shown in FIG. 3, a silicon oxide film obtained by, for example, CVD technology is formed over the entire surface of the semiconductor substrate 1.

Through the above manufacturing steps, the DRAM of this embodiment is completed.

In this embodiment, a predetermined semiconductor region 6B of MISFETQ
Titanium was used to form a conductive layer 11 connecting the conductive layer 9 and the conductive layer 9 constituting the capacitive element C. The refractory metal for forming the conductive layer 11 is not limited to titanium, but may be other refractory metals such as molybdenum, tungsten, or tantalum.

[Example ■]

Embodiment 2 describes a DRAM memory cell that eliminates the need for a mask alignment margin between a conductive layer 9 for forming a capacitive element C and an insulating film 12 provided thereon.

First, the structure of the memory cell of the DRAM of this embodiment will be explained.

FIG. 13 is a sectional view of a main part for explaining the configuration of a DRAM memory cell of Example 2.

In FIG. 13, nine conductive layers are used as one electrode constituting a capacitive element C.

The conductive layer 9A is tapered only at a predetermined end portion to which the conductive layer 11 is attached. Similar to the actual flow side I, this is because the conductive layer 11 is formed during the process of forming the sidewall 10.
Unnecessary sidewall 10 on the part where the
This is to prevent the formation of

In this practical example, the side surfaces of the nine conductive layers other than the portion where the conductive layer 11 is deposited are formed perpendicularly to the semiconductor substrate 1.

The insulating film 12A is formed so that the periphery of the opening 17 described in Example I is tapered. This is for the same purpose as in the first embodiment.

A feature of this embodiment is that no mask alignment allowance is provided between the tapered portion of the conductive layer 9A and the tapered portion of the 12 insulating films.

A word extending over the insulating film 12A? IIWL needs to be spaced apart from the tapered portion of the insulating film 12A with a margin for mask alignment. This is because if the word line WL is arranged in the tapered portion, the processing accuracy of the etching process when forming the word #WL will be reduced.

In the DRAM on this side, the distance between word lines WL can be reduced by eliminating the need for a mask alignment margin between the tapered portion of the nine conductive layers and the side surface of the insulating film 12A. Therefore, the area occupied by the memory cell can be reduced.

The configuration other than the 9 conductive layers and the 12 insulating layers is the same as in Example I, so the explanation will be omitted.

Next, a method for manufacturing the DRAM of this embodiment will be explained.

14 to 16 are diagrams for explaining the DRAM manufacturing method of this embodiment, and FIGS. 14 and 15 are plan views of important parts in the DRAM manufacturing process, and FIG. 15 is a sectional view taken along the line XVI-XVI in FIG. 15. FIG.

A feed insulating film 2, a channel stopper region 3. p+ for forming capacitive element C
A type semiconductor region 7 and an insulating film 8 are sequentially formed in the same manner as in Example I.Furthermore, in order to form nine conductive layers constituting the capacitive element C, a polycrystalline silicon layer is formed in the same manner as in Example I. It is formed over the entire surface of the semiconductor substrate 1.

After forming the polycrystalline silicon layer, as shown in FIG. 14, unnecessary portions of the polycrystalline silicon layer are selectively removed to form a conductive layer 9A. These nine conductive layers are formed integrally with the conductive layer 9A of the capacitive element C of the memory cell M connected to the same bit line 15 through the same connection hole 14 in the column direction. This is because the nine conductive layers integrally formed by self-alignment are patterned again using an etching process for forming an insulating film 12A, which will be described later. The etching process for integrally forming the nine conductive layers of the two capacitive elements C uses an anisotropic etching technique so that the sides of the nine conductive layers are perpendicular to the semiconductor substrate 1.

Note that an isotropic etching technique may be used in the etching process for forming the conductive layer 9A. By using the isotropic etching technique, the flatness of the insulating film 12A provided on the conductive layer 9A can be improved. Furthermore, by improving the flatness of the insulating film 12A, it is possible to reduce the constriction of the word line WL extending on the insulating film 12A, or to prevent disconnection.

After forming the conductive layer 9A shown in FIG. 14, in order to form the insulating film 12A shown in FIGS. 15 and 16,
A silicon oxide film is formed over the entire surface of semiconductor substrate 1. This silicon oxide film is made by, for example, CVD technology,
It is formed to a film thickness of approximately 00 CAI. Next, arsenic or argon is introduced near the surface of the silicon oxide film.

This impurity is used to form the insulating film around the opening 17 into a tapered shape in an etching process for forming the opening 17, which will be described later. The impurities may be added to a concentration of 10" [atoms/c] by, for example, ion implantation technology.
It is introduced at a dose of about A].

Next, an opening 17 is formed by selectively removing unnecessary portions of the insulating film 12A made of the silicon oxide film. M.I.S.
Unnecessary polycrystalline silicon layer 9 in the region where FETQ is provided
This is to expose people.

The etching process for forming the opening 17 is performed to form the opening 17.
The periphery of the insulating film 12A is formed into a tapered shape. Word line WL at the boundary between the opening 17 and the insulating film 12A
This is to reduce the constriction of the wire and prevent wire breakage. Opening hole 1
The etching step for forming 7 uses, for example, an isotropic dry etching technique. Further, as a mask for etching, for example, a resist is used.

Since arsenic or argon is introduced near the surface of the silicon oxide film for forming the insulating film 12A, the etching rate of the upper part of the silicon oxide film is higher than that of the lower part. However, the concentration of arsenic or argon inside the silicon oxide film decreases as it goes deeper from the top surface. On the other hand, in the isotropic etching technique, etching also progresses in the planar direction. Since the impurity concentration decreases in the deeper part of the silicon oxide film, the etching rate in the planar direction also becomes slower in the deeper part of the silicon oxide film.

From the above, by introducing arsenic or argon into the upper surface of the silicon oxide film and etching it using an isotropic etching technique, the insulating film 12A in the opening 17 can be etched.
The periphery of the can be formed into a tapered shape.

Note that the periphery of the insulating film 12A in the opening 17 does not necessarily need to be formed in a tapered shape. The insulating film 1 is formed by forming the openings 17 using an anisotropic etching technique.
It can also be formed so that the side surface of 2A is perpendicular to the semiconductor substrate 1.

Next, the polycrystalline silicon layer 9A exposed through the opening 17
is removed using an isotropic etching technique. In this etching step, the mask used in the step of forming the openings 17 is used in order to eliminate the need for a mask alignment margin for the nine conductive layers and the insulating film 12A.

By removing nine unnecessary polycrystalline silicon layers in the openings 17, nine independent conductive layers are formed for each capacitive element C. Furthermore, unnecessary polycrystalline silicon layer 9A)Q
By removing the insulating film 8, the insulating film 8 is exposed in the opening 17.

The following manufacturing steps are the same as the steps after the etching step for removing the insulating film 8 exposed by the opening 17 in Example I, and will therefore be omitted.

[Example ■]

Example (2) is a DRA in which pores are formed in the depth direction from the surface of a semiconductor substrate 10 and a capacitive element C is configured using these pores.
Memory cell 9 of M will be explained.

In this embodiment, the configuration will be explained first, and then the manufacturing method will be explained.

17 to 19 are diagrams for explaining the DRAM of this embodiment. FIG. 17 is a plan view of a memory cell of the DRAM, and FIG.
The sectional view taken along the cutting line, FIG. 19, is XIX in FIG. 17.
It is a sectional view taken along the -XIX cutting line.

Note that FIG. 17 does not illustrate the insulating film provided between the conductive layers in order to make it easier to see the configuration of the memory cell of the DRAM.

In Figures 17 to 19, 19 is a pore (, u*)
It is provided in the depth direction from the surface of the region where the capacitive element C of the semiconductor substrate 1 is formed.

In FIG. 17, the pores 19 are indicated by two-dot chain lines.

The pore 19 is located in the p+ type semiconductor region 7. By increasing the surface area of the semiconductor substrate 10 on which the insulating film 8 and the conductive layer 9 are provided, the capacitance value of the capacitive element C is increased.

In this embodiment, the p4 type half region 7 is provided extending along the pore 19 in the depth direction of the semiconductor substrate 1 as well.

The insulating film 8 is provided to cover the upper surface of the semiconductor substrate 1 and the inner wall of the pore 19 . The conductive layer 9 fills the pores 19 and is provided on the semiconductor substrate 1 .

Next, using FIGS. 17 to 19, the DRA of this embodiment will be explained.
The manufacturing method of M will be explained.

First, field insulating film 2. Channel stopper region 3 is formed in the same manner as in Example I.

Next, a mask for an etching process to form the pores 19 is formed on the semiconductor substrate 1. This mask uses, for example, a silicon oxide film formed by oxidizing the surface of the semiconductor substrate 10 and a resist film formed thereon. Next, the resist film on the surface of the semiconductor substrate 1 where the pores 19 are formed is selectively removed.

Next, using an anisotropic etching technique, the silicon oxide film in the area where the resist film has been removed is etched, and the semiconductor substrate 1 is further etched in the depth direction from the surface. Through this etching step, pores 19 having a depth of about 3 to 5 [μm] are formed.

Next, in order to form the semiconductor region 7, a p-type impurity, for example, boron, is introduced into the semiconductor substrate 1 around the pore 19. This p-type impurity is 1, for example, using thermal diffusion technology,
The impurity concentration of the semiconductor region 7 is 10'' [atoms
/aA). The silicon oxide film used in the step of forming the pores 19 is used as a mask for the thermal diffusion step.

Next, p-type impurities are introduced into the vicinity of the upper surface of the semiconductor substrate 1 where the capacitive element C is provided by ion implantation technology. This ion implantation step is not always necessary.

The p-type impurities introduced into the semiconductor substrate l around the pores 19 are exposed to heat treatment during the manufacturing process, such as gate insulating film 4.
This is because sufficient diffusion can be achieved by forming the semiconductor regions 6A and 6B of MISFETQ.

Next, the silicon oxide film used as a mask is removed, and a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 in order to newly form eight insulating films of the capacitive element C. This silicon oxide film is formed by oxidizing the surface of the semiconductor substrate 10 to
(A) It is formed to a certain thickness.Next, in order to form the insulating film 8B, a silicon nitride film is formed on the inner wall of the pore 19 and the upper surface of the semiconductor substrate 1. For example, 200 (
It is formed to have a film thickness similar to that of Al. Furthermore, the surface of the silicon nitride film is oxidized to form a silicon oxide film. This silicon oxide film improves the dielectric breakdown voltage of the insulating film 8B by blocking pinholes in the silicon nitride film.

Note that FIGS. 18 and 19 do not illustrate the silicon oxide film on the insulating film 8B.

Next, in order to form the conductive layer 9 inside the pores 19, a polycrystalline silicon layer obtained by CV and D techniques is formed over the entire surface of the semiconductor substrate 1.

This polycrystalline silicon layer is formed to be sufficiently thick so that the inside of the pore 19 can be sufficiently filled. This polycrystalline silicon layer is gradually removed from the upper surface to expose the upper surface of the insulating film 8B. Thereby, it is possible to prevent a recess from being formed between the pore 19 and the semiconductor substrate 1, and it is possible to make the top of the semiconductor substrate l flat. Next, a polycrystalline silicon layer is formed again on the entire surface of the semiconductor substrate 1.

This polycrystalline silicon layer is formed by three layers, for example, by CVD technology.
The film thickness is approximately 000 CA).

The following manufacturing steps are the same as those described in Example I after the step of patterning the polycrystalline silicon layer to form the conductive layer 9.

Incidentally, in order to reduce the area occupied by the memory cell M, the following step of forming a polycrystalline silicon layer on the semiconductor substrate 1 may be performed in the same manner as the step of forming the conductive layer 9A in Example 2. You can do it. That is, first, the polycrystalline silicon layer formed on the semiconductor substrate l is integrally formed with the conductive layers 9 of two memory cells M connected to the same connection hole 14. After this, MISFETQ of the silicon oxide film which becomes the insulating film 12
Using an etching process to remove the part where the
The integrally formed conductive layer 9 is made into an independent conductive layer 9 for each memory cell M.

〔effect〕

According to the new technology disclosed in this application, the following effects can be obtained.

(1) After removing the insulating film on the semiconductor region of the MISFET, a second conductive layer defined by a first conductive layer and a sidewall for forming a capacitive element is deposited on the semiconductor region, Further, one end of the second conductive layer is connected to a predetermined portion of the first conductive layer.

Thereby, the first conductive layer and the semiconductor region can be electrically connected by the second conductive layer without the need for a connection hole.

(2) According to (1) above, the second conductive layer and the MIS
It is possible to eliminate the need for a mask alignment margin between the gate electrode of the FET and a mask alignment margin between the second conductive layer and the p-type semiconductor region for forming the capacitive element.

(3) According to (2) above, the area occupied by the memory cell can be reduced, so the degree of integration of the DRAM can be improved.

(4) After removing the insulating film on the semiconductor region constituting the MISFET, silicide, which is a compound of a high melting point metal and silicon, is deposited on the semiconductor region to form a first capacitive element. The silicide layer is defined by a conductive layer and a sidewall, and an end of the silicide layer is connected to a predetermined portion of the first conductive layer. The first conductive layer and the semiconductor region can be electrically connected by the silicide layer without using a connection hole.

(5) According to (4) above, the silicide layer and MI
The area of the memory cell can be reduced because the margin for mask alignment with the gate electrode of the SFET and the margin for mask alignment between the silicide layer and the p-type semiconductor region for forming the capacitive element can be eliminated.

(6) Since the first conductive layer and the semiconductor region are connected by the silicide layer, the sheet resistance value of the silicide layer is sufficiently small at about 2 to 10 [Ω/hole], so that the first conductive layer and the semiconductor region are connected to each other by the silicide layer. An increase in connection resistance between the regions can be suppressed.

(7) According to the above (6), the drowsy operation time of the DRAM can be improved.

(8) In the first conductive layer provided on the semiconductor substrate to constitute the capacitive element, the peripheral portion where the second conductive layer for connecting at least a predetermined semiconductor region of the MISFET is deposited is tapered. The thickness of the insulating film used for forming the sidewall in the peripheral portion of the first conductive layer can be made to be approximately the same as the thickness in the flat portion.

Therefore, during the process of forming the sidewall, the first
It is possible to prevent an unnecessary insulating film from remaining in the periphery of the conductive layer.

(9) According to (8) above, the insulating film on the semiconductor region of the MISFET can be removed using the step of forming a sidewall without leaving an unnecessary insulating film in a predetermined portion of the first conductive layer.

αQ According to (9) above, the first conductive layer and the semiconductor region can be connected through the second conductive layer without using a connection hole.

συ According to (8) above, disconnection of the second conductive layer at a predetermined peripheral portion of the first conductive layer can be prevented.

α2 The above αυ makes it possible to improve the electrical reliability of the DRAM.

13 In two memory cells connected to the same bit line through the same connection hole, after the first conductive layers of the two capacitive elements are integrally formed, an etching process is performed to form an insulating film provided on the first conductive layer. Since the integrally formed first conductive layer is divided for each memory cell by the self-alignment of the insulating film, a margin for mask alignment between the first conductive layer and the overlying insulating film can be eliminated.

αa Since α4 allows the area of the memory cell to be reduced, the degree of integration of the DRAM can be improved.

a5 By forming the periphery of the first conductive layer for forming the capacitive element into a tapered shape, the flatness of the insulating film provided on the first conductive layer can be improved.

翰 Due to the above-mentioned Q, it is possible to prevent, or at least reduce, the constriction or disconnection of the word line at the step portion of the insulating film.

(17) Since impurities such as arsenic have been introduced near the top surface of the insulating film for insulating the first conductive layer m and the word line extending thereon, a step of selectively etching the insulating film. Therefore, it can be formed in a tapered shape around the insulating film.

fi seconds According to (I7) above, it is possible to prevent, or at least reduce, the constriction or disconnection of the word line at the stepped portion of the insulating film.

al A pore provided in the depth direction from the surface of the semiconductor substrate, a p-type semiconductor region provided inside the semiconductor substrate around the pore, and an isolated film provided on the inner wall of the pore and the top surface of the semiconductor substrate. Since the capacitive element is formed by the inside of the pore and the conductive layer provided on the insulating film on the semiconductor substrate, the capacitance value of the capacitive element can be increased without increasing the area occupied on the top surface of the semiconductor substrate. .

As mentioned above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be carried out without departing from the gist thereof.
・It goes without saying that the name can be changed from time to time.

For example, although titanium was used as the high melting point metal for forming the silicide in the above embodiments, other high melting point metals such as molybdenum, tungsten, and tantalum may be used.

In addition, in the embodiment described above, the memory cell was constructed using an n-channel type MI 5FET, but a p-channel type MISFET was used to configure the memory cell.
Memory cells can also be constructed using ET. A p-channel type MISFET is formed by forming an n-type well region in a p-type semiconductor substrate, and is configured in this n-type well region, or is configured in an n-type semiconductor substrate. The p medium type source region and drain region for configuring the p channel type MISFET are formed by introducing, for example, poron in the step of forming the n + type semiconductor region of Example I.

This p+ type semiconductor region is formed to reach the channel region.

[Brief explanation of the drawing]

FIG. 1 shows a DRAM for explaining Embodiment I of the present invention.
FIG. 2 is an equivalent circuit diagram showing a main part of a memory cell array of FIG. 2 to 4 are diagrams for explaining the configuration of the DRAM of Example I of the present invention, and FIG.
FIG. 3 is a cross-sectional view taken along the line II/-IV in FIG. 2, and FIG. 4 is a cross-sectional view taken along the line II/-IV in FIG. 5 to 12 are diagrams for explaining the DRAM manufacturing method of Example I of the present invention, and FIGS. A plan view, FIG. 7 is a cross-sectional view taken along the line ■-■ in FIG. 6, and FIGS. 9, 10, 11, and 12 are cross-sectional views of main parts of a DRAM memory cell in the manufacturing process. It is. FIG. 13 is a sectional view of a main part for explaining the configuration of a DRAM memory cell according to Example 2 of the present invention. 14 to 16 are diagrams for explaining the manufacturing method of the embodiment (2) of the present invention, and FIGS. 14 and 15 are plan views of main parts in the manufacturing process of the DRAM, The figure is a sectional view taken along the line XK-XIX. FIGS. 17 to 19 show a DRAM according to the embodiment (2) of the present invention.
FIG. 17 is a plan view of the memory cell of the DRAM, FIG. 18 is a sectional view taken along the line X--X in FIG. 17, and FIG. It is a sectional view taken along the line XIX-XIK in the figure. In the figure, 1... Semiconductor substrate, 2... Field insulating film, 3... Channel stopper region, 4... Gate insulating film, 5.5A, 5B... Gate electrode, 6, 6A, 6B
. 7... Semiconductor region, 8, 8A, 8B, 12, 12A. 13... Insulating film, 9,9A, 11.15... Conductive layer, 10... Side wall, 14... Connection hole, 16
... Protective film, 17 ... Opening, 18 ... High melting point metal layer, 19 ... Pore, SA ... Sense amplifier, WL.
...Word line, BL...Bit line, M...Memory cell, Q, QD...MI 5FET, C, CD...Capacitive element, D...Dummy cell, CQ...MI for clearing
SFET, φ0...terminal. Figure 1 Figure 2 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12

Claims (1)

[Claims] 1. A first conductive layer provided on a semiconductor substrate via an insulating film, and a first conductive layer provided near the surface of the semiconductor substrate below the first conductive layer.
a capacitive element having a semiconductor region; a second conductive layer provided on the semiconductor substrate near the capacitive element via an insulating film; and a pair of conductive layers provided near the surface of the semiconductor substrate on both sides of the second conductive layer. A semiconductor memory device comprising a plurality of series circuit elements each including a second semiconductor region and a MISFET having a side insulating film deposited on both sides of the second conductive layer, 1. A semiconductor memory device, wherein a first conductive layer and a second semiconductor region of one of the MISFETs are electrically connected by a third conductive layer provided on a semiconductor substrate. 2. The semiconductor memory device according to claim 1, wherein the first semiconductor region constituting the capacitive element has the same conductivity type as the semiconductor substrate and has a higher impurity concentration than the semiconductor substrate. 3. The third conductive layer is connected to the first conductive layer of the capacitive element and the MIS.
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to the second semiconductor region of the FET without passing through a connection hole. 4. The side insulating film provided on both sides of the second conductive layer constituting the MISFET is for insulating the second conductive layer and the third conductive layer. A semiconductor memory device according to any one of the ranges 1 to 3. 5. A first conductive layer provided on the semiconductor substrate via an insulating film, and a first conductive layer provided near the surface of the semiconductor substrate under the first conductive layer.
a capacitive element having a semiconductor region; a second conductive layer provided on the semiconductor substrate near the capacitive element via an insulating film; and a pair of conductive layers provided near the surface of the semiconductor substrate on both sides of the second conductive layer. A MISFET having a second semiconductor region and a side insulating film provided on both sides of the second conductive layer, one end of the third conductive layer provided on the semiconductor substrate is connected to the side surface of the capacitive element. A semiconductor memory device comprising a plurality of series circuit elements configured by connecting one end to a predetermined part of one conductive layer and the other end to one second semiconductor region of a MISFET,
A semiconductor memory device characterized in that the conductive layer is a compound of metal and silicon. 6. The semiconductor memory device according to claim 5, wherein the first conductive layer is a polycrystalline silicon layer. 7. The compound is used in the first conductive layer of the capacitive element and the MIS
Claim 5 or 6 is characterized in that it is a compound formed by reacting the second semiconductor region of the FET with the metal provided on the first conductive layer and the second semiconductor region. semiconductor storage device. 8. The semiconductor memory device according to any one of claims 5 to 7, wherein the metal is a high melting point metal such as titanium, tantalum, tungsten, or molybdenum. 9. According to any one of claims 5 to 8, the first semiconductor region constituting the capacitive element is a p-type semiconductor region and has a higher impurity concentration than the semiconductor substrate. semiconductor storage device. 10. A capacitive element having a first conductive layer provided on a semiconductor substrate via an insulating film, and a first semiconductor region provided near the surface of the semiconductor substrate under the first conductive layer; a second conductive layer provided on a semiconductor substrate with an insulating film interposed therebetween; a pair of second semiconductor regions provided near the surface of the semiconductor substrate on both sides of the second conductive layer; and both side surfaces of the second conductive layer. a MISFET having a side insulating film deposited on the semiconductor substrate, one end connected to a predetermined portion of the capacitive element, and the other end connected to one second semiconductor region of the MISFET. A semiconductor memory device comprising a plurality of circuit elements connected in series through a third conductive layer, wherein the second conductive layer has a tapered shape at least at a peripheral portion connected to the third conductive layer. Characteristic semiconductor memory device. 11. The semiconductor memory device according to claim 10, wherein the first semiconductor region constituting the capacitive element is a p-type semiconductor region and has a higher impurity concentration than the semiconductor substrate. 12. The semiconductor memory device according to claim 9 or 11, wherein the tapered portion of the first conductive layer is tapered to prevent disconnection of the third conductive layer. . 13. The semiconductor memory device according to any one of claims 9 to 12, wherein the first conductive layer is a polycrystalline silicon layer.