JPS61144847A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS61144847A
JPS61144847A JP26620284A JP26620284A JPS61144847A JP S61144847 A JPS61144847 A JP S61144847A JP 26620284 A JP26620284 A JP 26620284A JP 26620284 A JP26620284 A JP 26620284A JP S61144847 A JPS61144847 A JP S61144847A
Authority
JP
Japan
Prior art keywords
alloy
wiring
film
semiconductor device
wiring film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26620284A
Other languages
Japanese (ja)
Inventor
Yasushi Kawabuchi
靖 河渕
Hitoshi Onuki
仁 大貫
Masahiro Koizumi
小泉 正博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP26620284A priority Critical patent/JPS61144847A/en
Publication of JPS61144847A publication Critical patent/JPS61144847A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize an Al wiring equipped with moisture-proof and electromigration resistance by a method wherein an Al alloy is employed containing 0.1-0.2wt% of Pd or Pt and the Pd or Pt is precipitated as a simple substance or as a intermetallic compound. CONSTITUTION:The percentage of Pd should be 0.005-23% for corrosion resistance and not less than 0.1% for electromigration resistance. An alloy is therefore to be preferably composed of 0.1-2% of Pd, 0.1-3wt% of Si, and the rest Al. The alloy of Al-Pd or Al-Si-Pd is attached by spattering to a thermal Si oxide film. Next, solution annealing is accomplished by a 10-30min process at 480-530 deg.C, to be followed by a 20-60min process accomplished at 380-480 deg.C for the precipitation of Pd along the Al grain boundary. A 60-180min process is further accomplished at 330-380 deg.C for the precipitation of an Al-Pd intermetallic compound. By this method, a highly reliable Al alloy wiring is obtained. The same procesure is to be followed when Pt is used instead of Pd.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は主に樹脂封止半導体装置に係り、特に耐湿性と
耐エレクトロマイグレークヨン特性を兼ね備えたアルミ
ニウム合金配線膜を有する半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention mainly relates to a resin-sealed semiconductor device, and particularly to a semiconductor device having an aluminum alloy wiring film having both moisture resistance and electromigration resistance.

〔発明の背景〕[Background of the invention]

半導体素子上のアルミニウム配線膜のエレクトロマイグ
レーションを抑制するためにAt−Cu合金、At−3
i−Cu合金などによシ配線膜を形成することが知られ
ている。しかしこれらは耐食性カ低く、パッケージによ
っては腐食を起こす。
At-Cu alloy, At-3, to suppress electromigration of aluminum wiring film on semiconductor elements.
It is known to form a wiring film using an i-Cu alloy or the like. However, these have low corrosion resistance and may corrode depending on the package.

そこで特開昭57−170549号公報に開示されてい
るように、At Cu  Mn合金を使い腐食、’sv
クトロマイグレーション共に信頼性を満足する方法が知
られている。
Therefore, as disclosed in Japanese Unexamined Patent Publication No. 57-170549, an At Cu Mn alloy is used for corrosion, 'sv
A method is known that satisfies the reliability of both chromatography and migration.

At−Pdに関しては特開昭57−1241号公報に開
示されているようにpdを0.1%以上添加する事によ
ってAtの耐食性を改善できる事が知られている。
Regarding At-Pd, it is known that the corrosion resistance of At can be improved by adding 0.1% or more of PD, as disclosed in JP-A-57-1241.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、従来のAt−8i−Cu合金。 The object of this invention is the conventional At-8i-Cu alloy.

At−Pd合金に代わり、耐食性と耐エレクトロマイグ
レーション特性をあわせ持つAt合金配線膜を有する半
導体装置およびその製造法を提供することにある。
It is an object of the present invention to provide a semiconductor device having an At alloy interconnection film having both corrosion resistance and electromigration resistance in place of an At-Pd alloy, and a method for manufacturing the same.

〔発明の概要〕[Summary of the invention]

本発明は、半導体素子上の配線膜をpdとptの少なく
とも1つをα1〜2重量%含むAt合金又は更にシリコ
ンを0.1〜3重量%含むAt合金によシ形成するもの
である。なお、前記At合金において、PdとptとS
tの少なくとも1つは単体又は金属間化合物の形で析出
させることが必要である。
In the present invention, a wiring film on a semiconductor element is formed of an At alloy containing α1 to 2% by weight of at least one of PD and PT, or an At alloy further containing 0.1 to 3% by weight of silicon. In addition, in the At alloy, Pd, pt, and S
At least one of t needs to be precipitated as a simple substance or in the form of an intermetallic compound.

従来、耐エレクトロマイグレーション特性と耐食性は両
立せず、特に耐エレクトロマイグレーション性を高める
Cuはλを基地の耐食性を低くしていた。
Conventionally, electromigration resistance and corrosion resistance are not compatible, and in particular, Cu, which improves electromigration resistance, lowers the corrosion resistance of the λ base.

そこでkAの耐食性を高めるPdを適量添加し、金属間
化合物を分散析出させる事によって耐食性。
Corrosion resistance is achieved by adding an appropriate amount of Pd, which increases kA corrosion resistance, and by dispersing and precipitating intermetallic compounds.

耐エレクトロマイグレーション特性が共に優れた特性を
示すA/、合金配線膜を形成できる事が分かった。Pd
をα1〜2s添加したA4合金膜あるいはAt−2%8
i合金膜で問題となるのはピッティングが生じる事であ
る。一方、配線膜の腐食で問題となるのはポンディング
パッド部分の腐食であるがパッドの面積は通常、100
μff1X100μmと広く多少のピッティングが生じ
ても問題ない事が分かった。エポキシ樹脂で封止した実
際の半導体素子のAt膜パッド腐食の防止に効果がみら
れるのはα005〜2チPdの範囲であり、それはPd
K:よってAt基地がアノード分極されることによりA
t膜表面の酸化皮膜が強化されるためと考えられる。
It has been found that it is possible to form an A/alloy wiring film that exhibits excellent electromigration resistance. Pd
A4 alloy film with α1~2s added or At-2%8
A problem with i-alloy films is that pitting occurs. On the other hand, the problem with corrosion of the wiring film is the corrosion of the bonding pad, but the area of the pad is usually 100
It was found that there was no problem even if some pitting occurred as wide as μff1×100 μm. The range of α005 to 2 cm Pd is effective in preventing At film pad corrosion in actual semiconductor devices sealed with epoxy resin;
K: Therefore, when the At base is anodically polarized, A
This is thought to be because the oxide film on the surface of the t-film is strengthened.

エレクトo−rイグレークヨンは電流が流れる事によっ
てAt膜の結晶粒界が移動し、配線部分が断線に至るも
ので、結晶粒界を強化する事によって耐エレクトロマイ
グレーション性を高める事ができる。A4基地中へのP
dの固溶限が0.11であるため0.1チ以上のPdt
−Atに添加する事によってA/、−Pdの金属間化合
物を析出させる事ができる。そのための熱処理は蒸着あ
るいはスパッタで形成したAt膜を510Cで10分間
加熱する事によってPdを均一にAt中に固溶させる。
In the electro-or migration, when a current flows, the crystal grain boundaries of the At film move, leading to disconnection in the wiring portion, and electromigration resistance can be improved by strengthening the crystal grain boundaries. P into A4 base
Since the solid solubility limit of d is 0.11, Pdt of 0.1 or more
By adding it to -At, intermetallic compounds of A/ and -Pd can be precipitated. The heat treatment for this purpose involves heating the At film formed by vapor deposition or sputtering at 510C for 10 minutes to uniformly dissolve Pd in At.

次に400Cで30分間加熱する事により粒界にpdを
移動させるとともに、粒界での析出物を形成させる。そ
の次に400Cで未析出だったPdを析出させるため3
50Cで1時間の加熱を行なう。この最後の熱処理で、
400Cで析出していたAt−Pd析出物の周囲に微細
な析出物を形成する事ができる。
Next, by heating at 400C for 30 minutes, PD is moved to the grain boundaries and precipitates are formed at the grain boundaries. Next, in order to precipitate unprecipitated Pd at 400C,
Heating is performed at 50C for 1 hour. In this final heat treatment,
Fine precipitates can be formed around the At-Pd precipitates that were precipitated at 400C.

ここで述べた3段階の熱処理によってAt!Xの粒界に
Pdを析出させる事ができ、耐エレクトロマイグレーシ
ョン性を高める事ができる。
By the three-step heat treatment described here, At! Pd can be precipitated at the grain boundaries of X, and electromigration resistance can be improved.

pdの添加量は耐食性の点から0.005〜2%、耐エ
レクトロマイグレーションの点からo、1tlj以上と
規定され、両者を満足させる組成範囲として0.1慢〜
2−があげられる。Si量は0.1〜3重量−とする。
The amount of pd added is defined as 0.005 to 2% from the viewpoint of corrosion resistance, and 1 tlj or more from the viewpoint of electromigration resistance, and the composition range that satisfies both is 0.1 to 2%.
2- is given. The amount of Si is 0.1 to 3 weight.

また耐エレクトロマイグレーション性を高める熱処理は
上に述べた温度および加熱保持時間に限定されるもので
はなく、At膜の組織が結晶粒界に析出物が析出した構
造となれば多少の変動は可能である。
In addition, heat treatment to improve electromigration resistance is not limited to the above-mentioned temperature and heating holding time; slight variations are possible as long as the structure of the At film has a structure in which precipitates are deposited at grain boundaries. be.

具体的には480〜530Cで10〜30分間加熱保持
の溶体化処理と380〜480Cとで20〜60分間加
熱保持の析出処理および330〜380Cで60〜18
0分間加熱保持の再加熱処理を施すようにすれば析出物
を析出させることが  ′できる。
Specifically, solution treatment is carried out by heating and holding at 480-530C for 10-30 minutes, precipitation treatment is heating and holding at 380-480C for 20-60 minutes, and 60-18C is heated at 330-380C.
Precipitates can be precipitated by performing a reheating treatment in which the temperature is maintained for 0 minutes.

以上述べた事はptにもあてはまる。What I have said above also applies to PT.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を詳細に説明するつAt−pd合
金膜及びAt−2チ5i−pd合金膜をスパッタ法によ
りAr分圧6Pa、高周波出力2klの条件で熱酸化シ
リコン上に厚さ1μm形成したっただし、基板へのAL
−Pd又はAt−8i−Pd合金薄膜の形成方法はスパ
ッタ法に限らず、電子ビーム真空蒸着、CVD法等を利
用できる。この薄膜をウェットエツチング法あるいはケ
ミカルドライエツチング法によシ配線、電極を作製し、
510Cで10分間、400Cで30分間、350tl
l’で1時間の3段階熱処理を施した。
Examples of the present invention will be described below in detail. An At-pd alloy film and an At-2 5i-pd alloy film are deposited on thermally oxidized silicon by sputtering under conditions of an Ar partial pressure of 6 Pa and a high frequency output of 2 kl. However, the AL on the substrate is 1 μm thick.
The method for forming the -Pd or At-8i-Pd alloy thin film is not limited to the sputtering method, but may also utilize electron beam vacuum evaporation, CVD, or the like. Wiring and electrodes are made from this thin film by wet etching or chemical dry etching.
510C for 10 minutes, 400C for 30 minutes, 350tl
A three-step heat treatment was performed at l' for 1 hour.

その後、Siチップに分割し金属リードフレームとSi
チップをA 11− S j接合あるいはAgペースト
で接合し、At配線膜とリードフレームとを直i3Gμ
m0Au線でワイヤボンディングした。
After that, it is divided into Si chips and attached to a metal lead frame.
The chips are bonded using A11-S j bonding or Ag paste, and the At wiring film and lead frame are directly bonded using i3Gμ.
Wire bonding was performed using m0Au wire.

ボンディング後、エポキシレジンを用いて150Cでモ
ールドし、レジンを硬化させるため150Cで2時間加
熱し丸。
After bonding, it was molded at 150C using epoxy resin, and heated at 150C for 2 hours to harden the resin.

このようにして作製したレジンモールド素子の耐食性試
験としてP CT (Pressure Cooker
Test 、 121C2気圧、飽和水源気中放置試験
)を行ない、そのpd添加量と試料の半数が腐食によっ
て断線するまでの時間t、oとの関係を第1図に示すつ
この結果素子の状態ではo、oos〜2−のpd添加が
Atあるいはht−zssio耐食性を高める事ができ
る。
P CT (Pressure Cooker
Figure 1 shows the relationship between the amount of PD added and the time t and o until half of the samples break due to corrosion. Addition of pd of o, oos to 2- can improve At or ht-zssio corrosion resistance.

エレクトロマイグレーション試験は200Cのオーブン
中で電流密度を2 X 10 ’ A/cm2に保ち配
線がエレクトロマイグレーションによって断線に至るま
での時間を測定した。この結果、試料の半数が断線に至
るまでの時間tsoとPda加量の関係を第2図に示す
。0.1チ以上のpd添加が有効な事が分かる。
In the electromigration test, the current density was maintained at 2 x 10' A/cm2 in an oven at 200C, and the time until the wiring reached disconnection due to electromigration was measured. As a result, the relationship between the time tso until half of the samples reach disconnection and the amount of Pda added is shown in FIG. It can be seen that adding PD of 0.1 inch or more is effective.

次に熱処理の影響をAL−2’48 i−1襲Pdで検
討した。スパッタ法で形成した膜を450C−で、1時
間加熱したものと、510Cで10分間、加熱処理を施
した際のエレクトロマイグレーション性を評価すると、
前者がtsoで10時間に対し後者は125時間と12
.5倍もの信頼性を有することが分かったつ450C,
1時間加熱の組織を第3図に、3段階加熱処理の組織を
第4図に示す。
Next, the influence of heat treatment was examined on AL-2'48 i-1 attack Pd. When evaluating the electromigration properties of a film formed by sputtering, heated at 450C for 1 hour and heat treated at 510C for 10 minutes,
The former is TSO and 10 hours, while the latter is 125 hours and 12 hours.
.. 450C, which was found to be five times more reliable.
The structure after heating for 1 hour is shown in FIG. 3, and the structure after three-step heat treatment is shown in FIG. 4.

尚、耐エレクトロマイグレーション性を高めるためには
ここに述べ良熱処理条件に限らず、Atji[の組織が
第4図に示す構造になれば良い。図中の特号は1が析出
物、2が結晶粒界を示している。
Incidentally, in order to improve the electromigration resistance, it is not necessary to use the favorable heat treatment conditions described here, but it is sufficient that the structure of Atji[ is as shown in FIG. 4]. The special numbers 1 in the figure indicate precipitates and 2 indicate grain boundaries.

第5図は本発明の3段階熱処理において第1段熱処理後
の組織を示している。
FIG. 5 shows the structure after the first stage heat treatment in the three stage heat treatment of the present invention.

第6図は、溶体化処理後、析出処理を行なったときの組
織を示しているつAt−Pdの金属間化合物がAtの結
晶粒界に析出してくる。この組織ではAtの粒界=りが
抑制されるため耐エレクトロマイグレーション性は著し
く向上するその後330〜380Gで60〜iso分間
再加熱する事により第4図に示したように未析出で固溶
していたpd又はptの金属間化合物をAtの粒界乃薫
粒界近傍に更に析出させる事ができる。この結果耐エレ
クトロマイグレー7ヨン性を更に高める事ができる。
FIG. 6 shows the structure when precipitation treatment is performed after solution treatment. At--Pd intermetallic compounds precipitate at At grain boundaries. In this structure, the grain boundaries of At are suppressed, so the electromigration resistance is significantly improved.After that, by reheating at 330 to 380G for 60 to iso minutes, it becomes a solid solution without precipitating as shown in Figure 4. It is possible to further precipitate the pd or pt intermetallic compound near the At grain boundaries or smoke grain boundaries. As a result, the electromigration resistance can be further improved.

第7図rcht−2ms + −1*pdo組成で各熱
処理を行った配線膜の耐エレクトロマイグレーション性
を示す。また比較のためにAt−2181配線膜を45
0Cで1時間処理した従来例についても示すっ 〔発明の効果〕 本発明によれば、耐食性、耐エレクトロマイグレーショ
ン性共に優れた半導体用配線膜が得られる。その結果レ
ジンモールドあるいはセラミックスモールドの高密度、
微細配線パターンに適用でき素子の信頼性の向上を図る
ことができる。
FIG. 7 shows the electromigration resistance of wiring films subjected to various heat treatments with rcht-2ms + -1*pdo composition. Also, for comparison, 45 At-2181 wiring films were used.
A conventional example treated at 0C for 1 hour will also be shown. [Effects of the Invention] According to the present invention, a wiring film for semiconductors having excellent corrosion resistance and electromigration resistance can be obtained. As a result, the high density of resin mold or ceramic mold,
It can be applied to fine wiring patterns and improve the reliability of devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明におけるAt及びAt−21SR中のp
d添加量とPCT腐食時間の関係を示す特性図、第2図
は本発明におけるAt及びAt−2’ASl中のPd添
加量とエレクトロマイグレー7ヨンによる断線時間の関
係を示す特性図、第3図は450Cで1時間加熱した時
のAt−21S +−XチPdの組織図、第4図は本発
明によるAt−2チ5t−xspdの3段階熱処理後の
組織図、第5図は1段目熱処理後の組織図、第6図は2
段熱処理後の組織図、第7図は従来の配線膜と本発明に
よる配線膜についてエレクトロマイグレーション試験結
果を示す特性図である。 1・・・析出物、2・・・結晶粒界。
Figure 1 shows At in the present invention and p in At-21SR.
Figure 2 is a characteristic diagram showing the relationship between the amount of d added and the PCT corrosion time. Figure 3 is a tissue diagram of At-21S +-X ChiPd heated at 450C for 1 hour, Figure 4 is a tissue diagram of At-2 Chi 5t-xspd after three-step heat treatment according to the present invention, and Figure 5 is a diagram of At-21S + - The organization diagram after the first stage heat treatment, Figure 6 is 2
FIG. 7 is a diagram showing the structure after the step heat treatment, and is a characteristic diagram showing the electromigration test results for the conventional wiring film and the wiring film according to the present invention. 1... Precipitates, 2... Grain boundaries.

Claims (1)

【特許請求の範囲】 1、半導体素子上に配線膜を有するものにおいて、前記
配線膜がパラジウムとプラチナの少なくとも一方を0.
1〜2重量%含み、残部が実質的にアルミニウムよりな
り、且つ前記パラジウムと前記プラチナの少なくとも1
つが単体又は金属間化合物の形で析出した合金により構
成されていることを特徴とする半導体装置。 2、半導体素子上に配線膜を有するものにおいて、前記
配線膜がパラジウムとプラチナの少なくとも一方を0.
1〜2重量%、シリコンを0.1〜3重量%含み、残部
が実質的にアルミニウムよりなり、且つ前記パラジウム
と前記プラチナと前記シリコンの少なくとも1つが単体
又は金属間化合物の形で析出した合金により構成されて
いることを特徴とする半導体装置。 3、半導体素子上の配線膜形成部分にパラジウムとプラ
チナの少なくとも一方を0.1〜2重量%含み、残部が
実質的にアルミニウムよりなる合金薄膜を形成したのち
、480〜530℃で10〜30分間加熱保持の溶体化
処理と380〜480℃で20〜60分間加熱保持の析
出処理および330〜380℃で60〜180分間加熱
保持の再加熱処理を施すことを特徴とする半導体装置の
製造法。
[Scope of Claims] 1. In a device having a wiring film on a semiconductor element, the wiring film contains at least one of palladium and platinum.
1 to 2% by weight, the remainder substantially consisting of aluminum, and at least one of the palladium and the platinum.
1. A semiconductor device characterized in that the semiconductor device is composed of an alloy in which the elements are precipitated in the form of a single substance or an intermetallic compound. 2. In a device having a wiring film on a semiconductor element, the wiring film contains at least one of palladium and platinum.
an alloy containing 1 to 2% by weight and 0.1 to 3% by weight of silicon, the remainder substantially consisting of aluminum, and in which at least one of the palladium, the platinum, and the silicon is precipitated alone or in the form of an intermetallic compound. A semiconductor device comprising: 3. After forming an alloy thin film containing 0.1 to 2% by weight of at least one of palladium and platinum and the remainder substantially aluminum on the wiring film formation area on the semiconductor element, the film is heated at 480 to 530°C for 10 to 30% by weight. A method for manufacturing a semiconductor device characterized by performing solution treatment by heating and holding for 380 to 480°C for 20 to 60 minutes, and reheating treatment by heating and holding at 330 to 380°C for 60 to 180 minutes. .
JP26620284A 1984-12-19 1984-12-19 Semiconductor device and manufacture thereof Pending JPS61144847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26620284A JPS61144847A (en) 1984-12-19 1984-12-19 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26620284A JPS61144847A (en) 1984-12-19 1984-12-19 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS61144847A true JPS61144847A (en) 1986-07-02

Family

ID=17427676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26620284A Pending JPS61144847A (en) 1984-12-19 1984-12-19 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS61144847A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0326018A2 (en) * 1988-01-20 1989-08-02 Hitachi, Ltd. Semiconductor device comprising conductor films
JPH021126A (en) * 1988-01-20 1990-01-05 Hitachi Ltd Semiconductor device and its manufacture
US5846877A (en) * 1995-05-27 1998-12-08 Lg Semicon Co., Ltd. Method for fabricating an Al-Ge alloy wiring of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0326018A2 (en) * 1988-01-20 1989-08-02 Hitachi, Ltd. Semiconductor device comprising conductor films
JPH021126A (en) * 1988-01-20 1990-01-05 Hitachi Ltd Semiconductor device and its manufacture
US5019891A (en) * 1988-01-20 1991-05-28 Hitachi, Ltd. Semiconductor device and method of fabricating the same
EP0326018B1 (en) * 1988-01-20 1997-11-19 Hitachi, Ltd. Semiconductor device and fabrication method
US5846877A (en) * 1995-05-27 1998-12-08 Lg Semicon Co., Ltd. Method for fabricating an Al-Ge alloy wiring of semiconductor device

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