JPS61140199A - Manufacture of multilayer printed circuit board and multilayer printed circuit board manufacture thereby - Google Patents
Manufacture of multilayer printed circuit board and multilayer printed circuit board manufacture therebyInfo
- Publication number
- JPS61140199A JPS61140199A JP60274364A JP27436485A JPS61140199A JP S61140199 A JPS61140199 A JP S61140199A JP 60274364 A JP60274364 A JP 60274364A JP 27436485 A JP27436485 A JP 27436485A JP S61140199 A JPS61140199 A JP S61140199A
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- multilayer printed
- circuit board
- layers
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/091—Locally and permanently deformed areas including dielectric material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0195—Tool for a process not provided for in H05K3/00, e.g. tool for handling objects using suction, for deforming objects, for applying local pressure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0221—Perforating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
- Y10T29/49167—Manufacturing circuit on or in base by forming conductive walled aperture in base with deforming of conductive path
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は多層プリント回路基板の製造方法に関するもの
であって、この方法では、第1回路層の関連した導体が
1つあるいはそれ以上の他の回路層の関連した導体また
は複数の導体と接触する様に、相互接続されるべき導体
の位置において第1回路層の少くとも1つの凹み(de
pression)を形成することによって、異なった
回路層の導体は相互接続されている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a multilayer printed circuit board, in which the associated conductors of a first circuit layer are connected to the associated conductors of one or more other circuit layers. or at least one recess in the first circuit layer at the location of the conductor to be interconnected so as to contact a plurality of conductors.
The conductors of different circuit layers are interconnected by forming a conductor.
本発明はまた、異なった層の導体が相互接続されている
ところの本方法によって製造された多層プリント回路基
板にも関係している。The invention also relates to multilayer printed circuit boards produced by the method in which conductors of different layers are interconnected.
電気的に絶縁された薄片の反対側でプリント回路層を相
互接続する方法あるいはプリント回路基板の2個の相互
に絶縁された回路層を相互接続する方法は、例えば米国
特許出願間llI!第3,346,450号で開示され
ている。この米国特許出願明細書では、第2層が貫通さ
れること無しに接触が第1層と第2層の間に形成される
押下げ技術(dHression technique
)を記載している。この様に形成された仮の接続は、例
えば凹みに銅あるいは金のめっきをすることによって、
追加的導電材料で電気的かつ機械的に補強されねばなら
ない。第2層に貫通しないために、上記の米国特許出願
明細書による方法は押下げの間に変形しない硬い支持面
(backing 5ur4ace )に対して実行さ
れねばならない。もし本方法がプリント回路層を具えた
電気的な絶縁薄片に適用されるなら、硬い支持面が一時
的に必要とされ、もしプリント回路基板の1方の側の2
個の回路層に適用されるなら、°基板は充分硬くなくて
はならない。Methods of interconnecting printed circuit layers on opposite sides of electrically insulating flakes or two mutually insulated circuit layers of a printed circuit board are described, for example, in US Pat. No. 3,346,450. This U.S. patent application discloses a push-down technique in which contact is formed between the first and second layers without the second layer being penetrated.
) are listed. Temporary connections formed in this way can be made by plating the recesses with copper or gold, for example.
It must be electrically and mechanically reinforced with additional conductive material. In order not to penetrate into the second layer, the method according to the above-mentioned US patent application must be carried out on a rigid backing surface that does not deform during pressing. If the method is applied to electrically insulating foils with printed circuit layers, a temporary hard support surface is required, and if two
If applied to individual circuit layers, the substrate must be sufficiently rigid.
本発明の目的は、異なった層で相互接続された導体を有
する多層プリント回路基板の製造方法を提供することで
あり、これはガラス繊維とかプリント回路基板で普通に
用いられている他の材料で補強されたエポキシ・レジン
の支持面の様な、硬さの少ない層の使用を可能にしてい
る。本発明の別の目的は、2つ以上の回路層を含む多層
プリント回路基板でまた使うことのできる方法を提供す
ることである。本発明の別の目的は、回路層の間の接触
が凹みの位置で良好であって、従って付加的導電材料に
よる接触のいっそうの補強が無くて済む様な方法を提供
することである。It is an object of the present invention to provide a method for manufacturing a multilayer printed circuit board having conductors interconnected in different layers, which can be made of fiberglass or other materials commonly used in printed circuit boards. This allows the use of less rigid layers, such as reinforced epoxy resin support surfaces. Another object of the invention is to provide a method that can also be used in multilayer printed circuit boards containing two or more circuit layers. Another object of the invention is to provide a method in which the contact between the circuit layers is good at the location of the recesses, so that no further reinforcement of the contact by additional conductive material is required.
これらの目的は冒頭の記事で説明された方法によって本
発明に従って達成されており、これは多層プリント回路
基板が少なくとも押下げプロセスの間に変形可能な基板
上に置かれ、かつ第1回路層が他の回路層(複数を含む
)のレベルを越えて押下げられ、従りて回路層が凹みの
位置で相互接続される様に、回路層の変形および回路層
間で絶縁層(複数を含む)の変形を引き起すことを特徴
としている。These objectives are achieved according to the invention by the method described in the opening article, in which a multilayer printed circuit board is placed on a deformable substrate at least during the pressing process, and the first circuit layer is Deformation of circuit layers and insulating layer(s) between circuit layers such that the circuit layers are pushed down beyond the level of other circuit layer(s) and thus the circuit layers are interconnected at recessed locations. It is characterized by causing the deformation of
可撓薄片の反対側で導体を相互接続する方法は西ドイツ
特許出願明細書筒D E 2,107,591号から既
知であり、第1層は第2層のレベルを越えて押下げられ
るが、その層は機械的接触には至らず、そして電気的導
電接続は押下げによって形成されたラグが更に曲がって
はんだ付けされるまでは実現されない。上記の西ドイツ
特許出願明細書による方法は不変(permanent
)支持面無しに可撓薄片にのみ使うことができる。更
にこの方法はダイスを使用する。A method of interconnecting conductors on opposite sides of a flexible foil is known from West German patent application DE 2,107,591, in which the first layer is pressed down beyond the level of the second layer, but The layers do not come into mechanical contact, and an electrically conductive connection is not achieved until the lugs formed by pressing down are bent further and soldered. The method according to the above-mentioned West German patent application is permanent.
) Can only be used on flexible flakes without a support surface. Additionally, this method uses dice.
本発明の非常に効率的な実施例による多層プリント回路
基板において、変形可能な基板の1方の側は不変回路層
と絶klilを具えている。従って、基板と回路層と絶
縁層は共にプリント回路基板を作り上げている。In a multi-layer printed circuit board according to a highly efficient embodiment of the present invention, one side of the deformable board comprises a permanent circuit layer and a permanent circuit. Thus, the substrate, circuit layer, and insulating layer together make up a printed circuit board.
所望なら、接続は例えば流動はんだ付は操作(flOW
−3ol(lerin(l 0peration)によ
って貫通のあと更に補強することができ、ここで好まし
くは、はんだ遮蔽ラッカ(solder−screen
ing 1acquer)が接続を作るべき領域の外側
の基板に与えられている。この流動はんだ付は操作にお
いて、はんだは貫通によって形成された空洞に与えられ
ている。If desired, the connections can be made, e.g. by flow soldering operation (flOW).
-3ol(lerin(l0peration)) can be further reinforced after the penetration, where preferably a solder-screen lacquer (solder-screen lacquer)
ing 1acquer) is applied to the substrate outside the area where the connection is to be made. In this flow soldering operation, solder is applied to the cavity formed by the penetration.
この様に形成されたはんだ付は点は端子を負荷すること
無しに電気部品を取付けるのに適しており、これは例え
ば接着剤による一時的固定のあと、同じかあるいは別の
はんだ付は操作で取付けることができる。Soldering joints formed in this way are suitable for mounting electrical components without stressing the terminals, which means that after temporary fixing, for example with adhesive, the same or another soldering joint cannot be operated. Can be installed.
本発明によるこの方法は両側に導体層を有する可撓な電
気的に絶縁された薄片にもまた適用されよう。凹みが形
成されると、上記の薄片は充分な程度まで変形できる一
時的支持板上に置かれる。This method according to the invention may also be applied to flexible electrically insulating foils with conductor layers on both sides. Once the depression has been formed, the flakes are placed on a temporary support plate that can be deformed to a sufficient extent.
この目的に対し熱可塑材料が最適であり、もし必要なら
、変形条件は温度の上昇によって満足できる。Thermoplastic materials are most suitable for this purpose and, if necessary, the deformation conditions can be satisfied by increasing the temperature.
本発明の方法が可撓薄片の反対側の導体の相互接続に使
われる場合、空洞は平行側面を有するであろう。と言う
のは、一時的支持基板の材料の変形は押下げの間に、こ
の支持基板の上に元々位置している材料が空洞中にクラ
ンプされる程度に変形される様な逆圧を生成するからで
ある。If the method of the invention is used to interconnect conductors on opposite sides of the flexible foil, the cavities will have parallel sides. This is because the deformation of the material of the temporary support substrate creates a counterpressure during depression such that the material originally located on this support substrate is deformed to such an extent that it is clamped into the cavity. Because it does.
本発明による方法の実施例は図面によって詳細に説明さ
れよう。Embodiments of the method according to the invention will be explained in detail by means of the drawings.
第1図は、絶縁層3によってお互いに分離されている導
体層2および4を支持している基板の部分の断面図であ
る。基板1は、層の厚さ1.5111とガラス遷移温度
125°を有するガラス繊維強化エポキシ・レジンの様
なこの技術分野で普通に用いられている材料から形成さ
れている。ガラス繊維は好ましくは網状パターンに配列
されるべきでなく、特に絶縁層3においてその位1に独
立に作られた凹みを許容している。導体層2および4は
、例えば35μm厚のパターン化された銅の層から構成
されている。絶縁層3は例えば厚さ75μ鴫を有する基
板1と同じ材料からできていよう。この層は既知の圧縮
法によって一緒に接合できる。FIG. 1 is a cross-sectional view of the part of the substrate supporting conductor layers 2 and 4 separated from each other by an insulating layer 3. FIG. The substrate 1 is formed from materials commonly used in the art, such as glass fiber reinforced epoxy resin with a layer thickness of 1.5111 and a glass transition temperature of 125°. The glass fibers should preferably not be arranged in a reticulated pattern, allowing indentations, particularly in the insulation layer 3, to be made independently. The conductor layers 2 and 4 consist of patterned copper layers, for example 35 μm thick. The insulating layer 3 may for example be made of the same material as the substrate 1 with a thickness of 75μ. The layers can be bonded together by known compression methods.
例えば硬化鋼の円錐形押下げ工具によって凹み5は導体
層4が導体層2を越で圧縮される様に形成されている。For example, by means of a conical push-down tool of hardened steel, the recess 5 is formed in such a way that the conductor layer 4 is compressed over the conductor layer 2.
このことは導体層2と4の間で環状接触6となっている
。ふくらみ7は就中、変形された絶縁材料3の集積によ
り凹み5のまわりに生成されている。ふくらみ7は小さ
い寸法であって、例えば曲りやはんだ付けされたラグと
は対照に、多層プリント回路基板のいっそうの機械的処
理を妨げない様になっている。幅0.511の導体の場
合に、例えば0.2i+m直径の凹みが使用されている
。This results in an annular contact 6 between the conductor layers 2 and 4. The bulge 7 is created, inter alia, around the depression 5 by the accumulation of the deformed insulating material 3. The bulges 7 are of small dimensions so as not to interfere with further mechanical processing of the multilayer printed circuit board, in contrast to, for example, bent or soldered lugs. For a conductor with a width of 0.511, a recess with a diameter of 0.2i+m is used, for example.
第1図に示されたものと類似の多層プリント回路基板の
部分の断面図である第2図において、対応する要素は周
じ参照番号を持っている。In FIG. 2, which is a cross-sectional view of a portion of a multilayer printed circuit board similar to that shown in FIG. 1, corresponding elements have circumferential reference numbers.
この場合、円錐台形(frustoconical )
押下げ工具が使用され工いる。第1図と第2図に示され
た実施例では、接続は凹みにおいて例えばはんだの様な
導電材料を与えることで更に補強することができる。第
1図の場合、層2と4の間の接続は接触6の領域で改良
されようし、第2図の場合には、もし層4が上記の層の
変形によって切断されるなら接続は改良されよう。In this case, frustoconical
A push-down tool is used for machining. In the embodiment shown in FIGS. 1 and 2, the connection can be further reinforced by applying a conductive material, such as solder, in the recess. In the case of FIG. 1, the connection between layers 2 and 4 would be improved in the area of contact 6, and in the case of FIG. It will be.
貫通もしくは押下げに使われる工具に依存して、この様
に形成された接触の部分は詳細には異なって見えるであ
ろう。非対称押下げ工具もまた適当である。例えば第3
図は3角形押下げ工具を示し、それによって不等四角形
凹みが形成できる。第4図は斜めに切断された円錐形押
下げ工具を示しており、それによって楕円形凹みが形成
できる。その様な切断された円錐形の適当な形状は、例
えば約50°の円錐の頂角、円錐形の軸と10°の角度
をなす端面および長さ0.2mmの長さを有する端面の
楕円の主軸によって規定されている。所望の結果を得る
ために、上述の寸法は選ばれた材料と層の厚さに適応さ
れなくてはならない。Depending on the tool used for penetration or depression, the area of contact thus formed will look different in detail. Asymmetric push-down tools are also suitable. For example, the third
The figure shows a triangular depression tool, with which uneven square depressions can be formed. FIG. 4 shows a conical depression tool cut at an angle so that an oval recess can be formed. A suitable shape for such a truncated cone is, for example, an apex angle of the cone of about 50°, an end face making an angle of 10° with the axis of the cone and an elliptical end face with a length of 0.2 mm. is defined by the principal axis of In order to obtain the desired result, the above-mentioned dimensions must be adapted to the chosen material and layer thickness.
(要約〉
本発明は、絶縁層(複数を含む)が変形され、かつ最外
層と次の層もしくは複数の次の層の適当な導体(複数を
含む)との間に接触が作られる様に、最外層の関連した
導体に凹みを形成することにより多層プリント回路基板
の異なった層の導体を相互接続する方法に関するもので
ある。SUMMARY The present invention provides a method in which the insulating layer(s) are modified such that contact is made between the outermost layer and the appropriate conductor(s) of the next layer or layers. , relates to a method for interconnecting conductors of different layers of a multilayer printed circuit board by forming recesses in the associated conductors of the outermost layer.
本方法は基板上の多層プリント回路や電気的絶縁薄片の
可撓多層プリント回路で適当に使用することができる。The method can be suitably used in multilayer printed circuits on substrates and flexible multilayer printed circuits in electrically insulating foils.
後者の場合に押下げプロセスに対し一時的な支持面が必
要とされる。基板あるいは一時的支持面は充分な程度に
変形可能でなくてはならない。In the latter case a temporary support surface is required for the pressing down process. The substrate or temporary support surface must be deformable to a sufficient degree.
第1図は、円錐形押下げ工具によって変形された凹みの
断面図である。
第2図は、円錐台形工具によって変形された凹みの断面
図である。
第3図と第4図は、本発明の方法で用いられた押下げ工
具の別の実施例である。
1・・・基板 2,4・・・導体層 3・・・絶縁
層5・・・凹み 6・・・接触 7・・・ふ(らみ
10・・・3角形押下げ工具
20・・・斜めに切断された円錐形押下げ工具特許出願
人 エヌ・ベー・フィリップス・フルーイランペン
フ7ブリケンFIG. 1 is a cross-sectional view of a recess deformed by a conical push-down tool. FIG. 2 is a cross-sectional view of a recess deformed by a frustoconical tool. 3 and 4 are alternative embodiments of the push-down tool used in the method of the present invention. DESCRIPTION OF SYMBOLS 1... Board 2, 4... Conductor layer 3... Insulating layer 5... Recess 6... Contact 7... Rise 10... Triangular push-down tool 20... Diagonally cut conical push-down tool Patent applicant: NV Philips Fluoran Penf 7 Bricken
Claims (1)
の他の回路層の関連した導体あるいは複数の関連した導
体と接触する様に、相互接続されるべき導体の位置にお
いて第1回路層中の少くとも1つの凹みを形成すること
により異なった層の導体が相互接続される多層プリント
回路基板の製造方法において、 多層プリント回路基板が少くとも押下げプ ロセスの間で変形可能な基板上に置かれ、かつ第1回路
層が他の回路層のレベルを越えて押下げられ、従って回
路層が凹みの位置で相互接続される様に、回路層の変形
および回路層間の絶縁層の変形が引き起されることを特
徴とする多層プリント回路基板の製造方法。 2、特許請求の範囲第1項記載の如き方法によって製造
された異なった層の導体が相互接続されている多層プリ
ント回路基板において、変形可能な基板の1つの側面が
不変回路層 と絶縁層のスタックを具えていることを特徴とする多層
プリント回路基板。Claims: 1. Conductors to be interconnected such that the associated conductor of the first circuit layer contacts the associated conductor or multiple associated conductors of one or more other circuit layers. A method of manufacturing a multilayer printed circuit board in which conductors of different layers are interconnected by forming at least one recess in a first circuit layer at a location, wherein the multilayer printed circuit board is placed on the deformable substrate and deforms the circuit layers and between the circuit layers such that the first circuit layer is pushed down beyond the level of the other circuit layers, thus interconnecting the circuit layers at recessed locations. A method for manufacturing a multilayer printed circuit board, characterized in that deformation of an insulating layer is caused. 2. In a multilayer printed circuit board in which the conductors of different layers are interconnected, manufactured by the method as claimed in claim 1, one side of the deformable board is connected to the invariant circuit layer and the insulating layer. A multilayer printed circuit board comprising a stack.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL8403755 | 1984-12-11 | ||
NL8403755A NL8403755A (en) | 1984-12-11 | 1984-12-11 | METHOD FOR MANUFACTURING A MULTI-LAYER PRINTED WIRING WITH SEW-THROUGH TRACKS IN DIFFERENT LAYERS AND MULTI-LAYER PRINTED WIRES MADE BY THE METHOD |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61140199A true JPS61140199A (en) | 1986-06-27 |
Family
ID=19844891
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60274364A Pending JPS61140199A (en) | 1984-12-11 | 1985-12-07 | Manufacture of multilayer printed circuit board and multilayer printed circuit board manufacture thereby |
Country Status (4)
Country | Link |
---|---|
US (1) | US4663840A (en) |
EP (1) | EP0187399A1 (en) |
JP (1) | JPS61140199A (en) |
NL (1) | NL8403755A (en) |
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US4937930A (en) * | 1989-10-05 | 1990-07-03 | International Business Machines Corporation | Method for forming a defect-free surface on a porous ceramic substrate |
US5121299A (en) * | 1989-12-29 | 1992-06-09 | International Business Machines Corporation | Multi-level circuit structure utilizing conductive cores having conductive protrusions and cavities therein |
US5146674A (en) * | 1991-07-01 | 1992-09-15 | International Business Machines Corporation | Manufacturing process of a high density substrate design |
US5729150A (en) * | 1995-12-01 | 1998-03-17 | Cascade Microtech, Inc. | Low-current probe card with reduced triboelectric current generating cables |
US5736679A (en) * | 1995-12-26 | 1998-04-07 | International Business Machines Corporation | Deformable interconnect structure for connecting an internal plane to a through-hole in a multilayer circuit board |
US5914613A (en) | 1996-08-08 | 1999-06-22 | Cascade Microtech, Inc. | Membrane probing system with local contact scrub |
US6034533A (en) * | 1997-06-10 | 2000-03-07 | Tervo; Paul A. | Low-current pogo probe card |
WO1999049708A1 (en) * | 1998-03-27 | 1999-09-30 | Minnesota Mining And Manufacturing Company | Method for making electrical connections between conductors separated by a dielectric |
US6256882B1 (en) | 1998-07-14 | 2001-07-10 | Cascade Microtech, Inc. | Membrane probing system |
US6578264B1 (en) | 1999-06-04 | 2003-06-17 | Cascade Microtech, Inc. | Method for constructing a membrane probe using a depression |
AU5224499A (en) * | 1999-07-21 | 2001-02-13 | Cascade Microtech, Inc. | Membrane probing system |
US6838890B2 (en) * | 2000-02-25 | 2005-01-04 | Cascade Microtech, Inc. | Membrane probing system |
WO2001078475A1 (en) * | 2000-03-31 | 2001-10-18 | Dyconex Patente Ag | Method and device for fabricating electrical connecting elements, and connecting element |
WO2001080612A1 (en) * | 2000-03-31 | 2001-10-25 | Dyconex Patente Ag | Method for fabricating electrical connecting element, and electrical connecting element |
WO2001076336A1 (en) * | 2000-03-31 | 2001-10-11 | Dyconex Patente Ag | Method for fabricating electrical connecting elements, and connecting element |
DE20114544U1 (en) | 2000-12-04 | 2002-02-21 | Cascade Microtech, Inc., Beaverton, Oreg. | wafer probe |
DE10101236A1 (en) * | 2001-01-12 | 2002-07-25 | Schunk Ultraschalltechnik Gmbh | Method of joining flat cables by ultrasonic vibrations e.g. for motor vehicle electrical systems, involves placing cables on carrier designed partially as counter-electrode |
AU2002327490A1 (en) | 2001-08-21 | 2003-06-30 | Cascade Microtech, Inc. | Membrane probing system |
KR100864916B1 (en) | 2002-05-23 | 2008-10-22 | 캐스케이드 마이크로테크 인코포레이티드 | Probe for testing a device under test |
US6724205B1 (en) | 2002-11-13 | 2004-04-20 | Cascade Microtech, Inc. | Probe for combined signals |
US7057404B2 (en) * | 2003-05-23 | 2006-06-06 | Sharp Laboratories Of America, Inc. | Shielded probe for testing a device under test |
JP2005026322A (en) * | 2003-06-30 | 2005-01-27 | Shinko Electric Ind Co Ltd | Wiring board and manufacturing method therefor |
WO2006017078A2 (en) | 2004-07-07 | 2006-02-16 | Cascade Microtech, Inc. | Probe head having a membrane suspended probe |
JP2007517231A (en) | 2003-12-24 | 2007-06-28 | カスケード マイクロテック インコーポレイテッド | Active wafer probe |
KR20070058522A (en) | 2004-09-13 | 2007-06-08 | 캐스케이드 마이크로테크 인코포레이티드 | Double sided probing structures |
US7535247B2 (en) | 2005-01-31 | 2009-05-19 | Cascade Microtech, Inc. | Interface for testing semiconductors |
US7656172B2 (en) | 2005-01-31 | 2010-02-02 | Cascade Microtech, Inc. | System for testing semiconductors |
US7403028B2 (en) | 2006-06-12 | 2008-07-22 | Cascade Microtech, Inc. | Test structure and probe for differential signals |
US7723999B2 (en) | 2006-06-12 | 2010-05-25 | Cascade Microtech, Inc. | Calibration structures for differential signal probing |
US7764072B2 (en) | 2006-06-12 | 2010-07-27 | Cascade Microtech, Inc. | Differential signal probing system |
JP4840132B2 (en) * | 2006-12-26 | 2011-12-21 | 株式会社デンソー | Multilayer substrate manufacturing method |
US7876114B2 (en) | 2007-08-08 | 2011-01-25 | Cascade Microtech, Inc. | Differential waveguide probe |
US7888957B2 (en) | 2008-10-06 | 2011-02-15 | Cascade Microtech, Inc. | Probing apparatus with impedance optimized interface |
US8410806B2 (en) | 2008-11-21 | 2013-04-02 | Cascade Microtech, Inc. | Replaceable coupon for a probing apparatus |
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US3037265A (en) * | 1957-12-30 | 1962-06-05 | Ibm | Method for making printed circuits |
US3364300A (en) * | 1965-03-19 | 1968-01-16 | Texas Instruments Inc | Modular circuit boards |
US3346950A (en) * | 1965-06-16 | 1967-10-17 | Ibm | Method of making through-connections by controlled punctures |
GB1261039A (en) * | 1968-10-02 | 1972-01-19 | Elliott Brothers London Ltd | Improvements relating to printed circuit assemblies |
US3499098A (en) * | 1968-10-08 | 1970-03-03 | Bell Telephone Labor Inc | Interconnected matrix conductors and method of making the same |
DE2107591A1 (en) * | 1971-02-17 | 1972-08-31 | Siemens Ag | Process for through-hole plating of foils coated with conductor tracks on both sides |
DE2347216A1 (en) * | 1973-09-19 | 1975-03-27 | Siemens Ag | Printed cct. boards metal coated on both sides - uses contacting of both sides between its two metal layers brought closely together |
DE2524581A1 (en) * | 1975-06-03 | 1976-12-23 | Siemens Ag | FLEXIBLE PRINTED CIRCUIT |
US4183137A (en) * | 1977-02-15 | 1980-01-15 | Lomerson Robert B | Method for metalizing holes in insulation material |
US4319708A (en) * | 1977-02-15 | 1982-03-16 | Lomerson Robert B | Mechanical bonding of surface conductive layers |
SU1019682A1 (en) * | 1982-01-29 | 1983-05-23 | Предприятие П/Я М-5181 | Method for making multilayer printed circuit boards |
-
1984
- 1984-12-11 NL NL8403755A patent/NL8403755A/en not_active Application Discontinuation
-
1985
- 1985-11-21 EP EP85201917A patent/EP0187399A1/en not_active Withdrawn
- 1985-12-02 US US06/803,357 patent/US4663840A/en not_active Expired - Fee Related
- 1985-12-07 JP JP60274364A patent/JPS61140199A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0187399A1 (en) | 1986-07-16 |
US4663840A (en) | 1987-05-12 |
NL8403755A (en) | 1986-07-01 |
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