JPS61138346A - Access control system of storage system - Google Patents

Abstract

PURPOSE:To make using efficiency of an address line and a data bus 100% by repeating the continuous output of one writing instruction and one reading inctruction. CONSTITUTION:When a 0 WAY (even No.) is selected by an WAY address, a signal SEL 00 WAY is outputted. Consequently, a clock CLK is applied only to WD REG 0 WAY in a data register 10 and data on a store data bus are stored. At that time the output SEL 00 WAY of the data 9 is set up to SEL 00 REG and inputted to a multiplexer MPX 01 with 1tau delay. Since the MPX 01 is controlled so as to select the output of the SEL 00 REG at the select signal output timing of the ODD WAY by a control signal SEL 16B at the 16-byte access operation, the MPX 01 impresses a CLK delayed by 1tau from the CLK to the WD REG 1 WAY of the register 10. At that time the 2nd 8-byte data on the store data bus are stored in the WD REG 1 WAY.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an access control method between a storage device in a storage system such as a computer and a device that accesses the storage device, and particularly relates to an access control method for accessing storage data. Concerning access control schemes to improve efficiency. □ [Prior art] Figure 2 shows an example of the configuration of a conventional storage device.
is a memory with N+1 MAY from 0-^Y to N-^Y, 2 is a store data bus, 3 is a chip address line,
4 is the 1^V address line, 5 is the memory input register, 6 is the -AY address timing generator, 7 is the decoder, 8 is the address register Ant) -REG, 9 is the decoder,
10 is a write data register t4n-ngc,
11 is a decoder, 12 is a read data register RD-R
EG, 13 is an OR gate, and 14 is a fetch data bus.

The illustrated device is capable of accessing, for example, 8 bytes of data, but for the sake of simplicity, only a 1-bit data access circuit is shown in FIG.

When writing to the storage device, a control device (not shown) that uses the storage device responds to write commands Go and O.
P (Go multiplication signal OP code), address and store data are supplied.

Memory 1 uses an interleave method to increase speed, and has a bank configuration consisting of N+1 independent memory sections. It is called the Y address. Also, the address given to the memory chip in one enemy coin is called a chip address. Here, when we simply say address, it means Y address to chip address.

In this figure, store data bus 2 and fetch data bus 14 have a length of 8 bytes.

It is also assumed that the chip nutless and WAY addresses each have multiple bits.

Address register Anrl -RUG 8 is for supplying chip addresses to each -^Y of memory 1 separately.

It is composed of N+1 WAY units. Similarly,
The write data register 11-REG 10 and the read data register R11-REG 12 are also each composed of N+1 -AY units in order to hold write data and read data corresponding to the 1^Y configuration of the memory 1. There is.

The chip address supplied to the chip address line 3 passes through the memory input register 5 and is sent to the address register ADD.
-RF! It is stored in any one ^V unit selected by the WAY address in G8.

The WAY address supplied to MAY address 4 is.

The signals are applied to the MAY address timing generator 6 through the memory input register 5, and are outputted to the decoders 7, 9, and 11 at a predetermined timing. Note that the MAY address timing generator 6
A chip select signal C8 and a write enable signal WE (not shown) are also supplied to the memory chip.

The output of the decoder 7 becomes a signal for selecting one AY unit of AI)D-12RGFI. Further, the decoder 9 transfers the store data supplied to the store data bus 2 to the write data register D-R[! It has a function of selectively inputting to one MAY unit corresponding to the WAY address of G10. Similarly, the decoder 11 selects W out of the data read from each -AY of the memory 1.
It has a function of inputting only the data corresponding to the AY address to the corresponding off^Y unit of the read data register RD-RIEG 12.

Next, a more detailed operation of the specific example shown in the timing diagram of FIG. 3 will be explained. In the example shown in Figure 3, a write command (ST) and an address (80ry) are output from the control device, and 8 bytes (B) of store data are output with a delay of 1τ, without further freeing up the address bus. This instruction (ST) is for a 16-byte store operation in which this instruction (ST) is issued again.

In Figure 2, the enemy AV address (-8Y-ADD
) is input to the MAY address timing generator 6.

Here it is converted to a WAY address with timing,
Decoder 7.9.11 respectively address register AI)D-17FG 8. Write data register D-REG 10. Read data register R[]
-1? 1 of N WAY units in EG 12
Choose one.

As a result, 8110-R1 corresponding to the WAY address sent! Store the chip address in the -AY unit of G, store the store data in the corresponding MAY unit of 10-12EG, and write the memory chip C3, WE.
is also output only to the corresponding AY.

Only the memory section of the selected AV operates to complete the writing.

The time required for this writing depends on the value of τ.

Usually, it is around 10τ, and during this period, the memory section indicated by this -AY address cannot be used for anything else (that is, becomes RUSY TIMF!).

Therefore, as shown by the arrows between (a), (b), and (c) in Figure 3, when store data is sent again at the next τ, it cannot be written to the same InAV. It must be stored in another free WAY. This BIISY-TIME management is generally performed on the control device side.

Next, in the case of a read operation, (a) and (
b) As shown by the arrow between them, when the read command (FH) and address are sent to the storage device, the 1 to V 8 DD - RHG 8 1 to Y unit, chip select C8, etc. corresponding to the WAY address are sent. Operation and identification of memory 1-
The memory section of AY is read, and further RD-R1'! G
Twelve specific WAY units are selected and read data, that is, fetch data is set. This Rrl-
Since the output of REG 12 is set to "θ" when 1 is not selected, the outputs of N MAY can be combined by simply ORing the outputs of each -AM unit.

As shown by the arrow between (a), (b), and (d) in Figure 3.

After the read command (FH) is activated, the fetch data is output to the fetch data bus after a memory chip access time of one normal number τ has elapsed, depending on the value of τ. Therefore, at the next τ of Go, OP, read with a MAY address different from the above read instruction (PH).
When the instruction (PH) is activated, Ig(d)
As shown in the figure, fetch data of 8 bytes x 2 = 16 bytes can be obtained continuously.

Furthermore, as shown in FIG. 3(a), a write command (S↑) and a read command (FH) are issued a total of 8 times (8τ).

When issuing to a storage device, one transfer is 8 bytes, so a total of 64 bytes of data can be sent and received.

This is the conventional transfer method, and no matter how the order of writing/reading is changed, only a maximum of 64 bytes can be accessed with 8τ.

[Problem to be solved by the invention] By the way, in recent years electronic computers using such storage devices, as the processing power of the arc has improved, huge amounts of data have been written to the storage devices.

Read requests are increasing. Therefore, storage devices must process as much data as possible per unit time.

For this purpose, 8 bytes of data are transferred every 1τ and MA
They were set in a register group for each Y, and after setting, writing/reading was performed to the register within the time that the memory chip for each Y could operate.

In order to further increase the speed, it is possible to increase the number of MAY and increase the storage capacity of 1'W'AY for a large-capacity monitor, but this is due to hardware considerations.

This method had its limitations.

Therefore, in order to achieve higher speed while keeping the number of InAVs and storage capacity constant, the method shown in Figure 3 should be used.

There was a problem in that the upper limit of the data transfer amount' of 64 bytes at 8τ had to be increased further.

[Means for solving problems]

The present invention focuses on the usage rate of the store data bus and the fetch data bus, and improves the problem that there is a 2τ vacancy in the example shown in FIG. This increases the amount of data transferred.

And what is the configuration of the present invention for that purpose? ! A storage device configured of several basic memory banks and accessed by addresses consisting of bank addresses and intra-bank addresses, an address bus, and a write data bus.

In a storage system that supports a read data bus, the plurality of basic memory banks are physically addressed as even numbers and odd numbers, and read instructions are issued by pairing sequential even and odd bank addresses. and write commands alternately, supply only one of the even-numbered and odd-numbered bank addresses onto the address bus, and respond by replenishing the other bank address in the storage device. The basic memory bank is accessed, and write data and read data are continuously transmitted on a write data bus and a read data bus, respectively.

[Operation of the invention 1] In the present invention, one address attached to one instruction handles the amount of data equivalent to two addresses.

By issuing one write command and one consecutive write command twice, both the store data bus and the fetch data bus are used for 2τ due to two consecutive addresses on the address bus. become. So write, read, write.

By repeating reading, etc., the usage efficiency of the address lines and data bus can be made 100%.

〔Example〕

The details of the present invention will be explained below based on examples.

FIG. 1 is a timing diagram of one embodiment of the system of the present invention, and corresponds to the timing diagram of the example of the conventional system shown in FIG.

In Figure 1, (a) is the GO multiplication signal of the instruction and the OP
5T16 represents a 16-byte access write command, and FH16 similarly represents a 16-byte access read command.

In addition, (b) in the figure represents the address that is output on the address line when each instruction (ST16.FH16) is issued.
, 0DD (odd number), F! Only the address of νEN is used. These EVEN addresses are designated as IP, 2E, 3E, 4E for convenience. The storage device generates the 0rlI'] address based on this EVEN address. The generated 0Dr) address is 1
0,20,30.40.

Further, (C) in the figure represents store data supplied on the store data bus. One 16-byte store data is U! 8 bytes (8B) of VEN address and On
This is a combination of 8 bytes (8B) of the D address. In the illustrated example, two 16-byte data (ie, four 8-byte data) indicated by addresses IE, 10.3E, and 30 are consecutively supplied within 4τ.

Similarly, (d) in the figure shows 2E, 20.4B of memory.
, 40 addresses and output on the fetch data bus, two consecutive 16-byte data (ie, four 8-byte data) within 4τ.

First, in operation, the control device side issues an OP code (SrI2) instructing writing of 16 bytes of data and a Go times signal.

At this time, if the address to be sent to the storage device at the same time is determined to be EVEN, the WAY address in the address will always be EVEN. Next, data is sent twice in succession of 8 bytes each. The address allocation at this time is EVEN for the first time and ODD for the second time.

The storage device side identifies from the OP code that it is a 16-byte access request. By the way, it was sent to me-A
Y address is EVI! N, and it is specified that the data is also sent twice, so the first data is the 4 nits of EVEN-8Y of the address register ^DD-REG, and the primary data is the unit of 0rlD-8Y. It would be a good idea to store it in .

In this way, in the case of 8-byte access, there is no need to take the trouble to attach an address to each 8-byte data, and data for 2×8 bytes can be sent in 1τ.

Here, since 16 bytes of address are sent at 1τ, the address bus is left vacant by 1τ, unlike the conventional method. Therefore, it is possible to send another 16 bytes of address to this empty space, but since the instruction write data is sent twice consecutively onto the store data bus, the store data bus is not used. Can not.

This address bus free space is used for fetch accesses to avoid using the store data bus (the fetch data bus is used instead).

In the next access at τ, the store data bus is free again, so a store access can be performed, but a fetch access cannot be performed because the fetch data bus is not free.

In this way, store/fetch/store/fetch...
By controlling the controller to perform 16-byte accesses, the bus usage efficiency can be reduced by 1.
It can be set to 00%. In the example in Figure 1, 4τ is 6
4-byte access control is performed.

In addition, the control device and storage device are controlled by the OP code.
Since access switching between 8 bytes and 16 bytes can be easily performed, the type of access can be used depending on the data structure of the access source.

Next, an example circuit for realizing these accesses will be explained.

FIG. 4 shows the selection mechanism of the write data register register REG, and 9 and 10 in FIG. 1 correspond to the decoder and write data registers WD-RF and G in FIG. 2, respectively. Further, 15 is an ODD W^Y 5ELEC↑ signal generation circuit required in the present invention.

Further, FIG. 5 is an operation timing diagram of the circuit shown in FIG. 4, and ``■'' and ``■'' represent signals at the portions indicated by ``■'' and ``■'' in FIG.

In FIG. 4, the decoder 9 receives stored data 10-12I! WD-REG 10's WAY unit (O
WAY-N tIAV). Therefore, the decoder 9 reads: SRL 00 WAY, SEL 01 WA
N + 1 (DSI!LECT signal outputs of Y, .

This is the timed V address supplied from the Y address generator to the other party. This ■^Y address is 1
In case of 6-byte access, I! Because it will only be on VHN,
The output of the decoder 9 is only the even numbers, that is, S[! 1.0
0 WAY, S[! L 02 WAY, ・・・-・
・It becomes.

The 5ELIICT signal generation circuit 15 has a black function that replenishes the ODD WAY address from the EVEN WAY address during a 16-byte access operation. This is EV [! The EvEN output of the decoder 9 is held when the N-^V address is input, and at the timing of the first-order τ, that is, the 0011 MAY address,
Instead of the onn output of decoder 9, S'E L I!
It outputs a CT multiplied signal. Register S[
! I, 00 anal G, Sl! L 02 Rt! G, S.E.
L 04 REG.

. . . are the EVf! of decoder 9, respectively. Has the function of holding N output. Also multiplexer MPX 01.
MPX 03°MPX 05. ... selects each ODO output of the decoder 9 during 8-byte access operation, and
During 6-byte access operation, register SF! L 00
RUG, St! L 02 R1! G.

It has a function to select the output of SBL 04 RUG,...

For example, depending on the MAY address, the number between 0 and Y (EVI
! N WAY) is selected, the decoder 9 outputs 1τ(7) St! indicated by ■. LlICT signal SEL 00 WA
Y is output and the result.

Write data register 1^Y unit WD-RI!
A clock CLK indicated visually is given only to GO-^Y, and the data on the store data bus at that time is stored.

Also at this time, the output St! of the decoder 9! L 00 WA
Y is.

It is set in the register SEL 00 REG and the
The signal is input to the multiplexer MPX 01 with a delay of 1τ as shown in FIG.

During the 16-byte access operation, the MPX 01 uses the control signal 5EL16B indicated by ■ to control the ODD WAY.
Since the state is set to select the output of 5RL00REG shown by ■ in accordance with the 5ELlICT signal output timing of Apply to REG I WAY. Therefore,
At this time, the second 8-byte data on the store data bus is WD Rf! Stored in G 1 -^Y.

In this way, for any other EVEN-^V address, even-numbered Sl! is output from the decoder 9! L
From the tIC↑ signal to the next τ, the odd numbered St! Can generate LlICT signal. Each W of the write data register
Data can be selectively stored in the AY unit. The data in each MAY unit of the write data register is sent to the memory unit MAY by MAY.

At this time, regarding the WE signal of the memory section, WAY
EVI! N, Qrl (input with a timing difference of .1τ according to l).

Figure 6 shows the address register At)D-R[! 7 shows the selection mechanism of G, and FIG. 7 is its operation timing diagram. They correspond to the recorder f and address register ADD-REG in FIG. 2, respectively. 16 is the onn required by the present invention.
-＾Y SEl. F. This is a CT signal generation circuit. This circuit 16 corresponds to the circuit 15 in FIG. 4, but the register SRL 00 RRG for holding the EVEN WAY SRLECT signal and the like are removed.

In addition, the multiplexer liver χ01. MPX 03. M
Similarly to the circuit 15, PX 05° . . . is controlled to select the upper input by the signal 5EL16B during the 16-byte access operation.

The operation is performed using the write data register WD-REG in FIG.
It is almost the same as in the case of [! Vl! N101) D is stored in the address register Ar1D-REG at the same time.

Therefore, there is no need to perform a 1τ delay operation like I'1ATA, and when accessing 16 bytes, for example, 0. Select I MAY (EVENloDD) at the same time.

Store the chip address data of 1τ in ^DD-REG.

Next, the operation of the circuit shown in FIG. 6 will be explained with reference to FIG. The signals marked ``■'' to ``■'' in FIG. 7 are signals of the portions ``■'' to ``■'' shown in the circuit of FIG.

For example, when the OWAY MAY address is given to the decoder 7 from the WAY address timing generator,
From the decoder 7, 5RLF of ■ (:T signal SEI, 0
0 WAY is output.

When accessing 16 bytes, MPX 01 uses ■SEL
Since it is set to the upper side by 16B, the clock C of ■
LK is the address register ADD as shown by ■ and ■.
It is applied to the 0-AV and 1-^Y units of -REG 8 at the same time, and the address data (2), that is, the chip address, is similarly stored in both of these WAY units.

Note that the selection circuit for the read data register R11-REG can be constructed in the same manner as the selection circuit for the write data register D-REG in FIG. 4, so a description thereof will be omitted.

In the above embodiment, only the EVEN WAY address was transmitted, but instead of 2 O! ll'l
It is clear that the same implementation can be achieved by transmitting only 14 AV addresses.

〔Effect of the invention〕

In conventional 8-byte access, it was necessary to send 1τ of address data in one data transmission. For this reason, when transferring a large amount of data at high speed, it became a bus neck.5 However, with the present invention, by handling 2 x 8 bytes worth of data with 1τ address data, the free space on the data bus can be eliminated. be able to. As a result, the bus usage efficiency becomes 100%, allowing higher-speed data transfer. Further, the increase in circuitry required for this purpose can be negligible.

[Brief explanation of drawings]

FIG. 1 is a timing diagram of an access operation in one embodiment of the method of the present invention, FIG. 2 is a configuration diagram of a conventional storage system targeted by the present invention, and FIG. 3 is a timing diagram of an access operation of the conventional method. Figure 4 shows write data register D-
An embodiment circuit diagram of the REG selection mechanism, FIG. 5 is an operation timing diagram of the mechanism in FIG. 4, and FIG. 6 is an address register Al.
FIG. 7 is a circuit diagram of an embodiment of the l+1-RIEG selection mechanism. FIG. 7 is an operation timing diagram of the circuit of FIG. In the figure, 1 is a bank-configured memory, 2 is a store data bus, 3 is a chip address line, 4 is a Y address line, 6 is a WAY address timing generator, 7°9.11 is a decoder, and 8 is an address register. ^DD-REG, 10 is the write data register low 0-low G. 12 is a read data register, 14 is a fetch data bus, 15.16 is 01]D WAY 5ELTICT
A signal generation circuit is shown.

Claims (1)

[Claims] In a storage system comprising a storage device comprising a plurality of basic memory banks and accessed by an address consisting of a bank address and an address in the bank, an address bus, a write data bus, and a read data bus, the plurality of basic memory banks physically address even-numbered and odd-numbered bank addresses, and further issue read commands and write commands alternately by pairing sequential even-numbered and odd-numbered bank addresses, and Only one of the bank addresses is supplied onto the address bus, and in the storage device, the other bank address is supplemented to access the corresponding basic memory bank, and the write data and read data are transferred to the write data bus and An access control method in a storage system characterized by continuous transmission on a read data bus.