JPH0250497B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an access control method between a storage device in a storage system such as a computer and a device that accesses the storage device, and particularly relates to an access control method for controlling storage data. This invention relates to an access control method for improving access efficiency.

[Conventional technology]

Figure 2 shows an example of the configuration of a conventional storage device, where 1 is N+ from O WAY to N WAY.
Memory with 1 WAY, 2 is store data bus, 3 is chip address line, 4 is WAY address line, 5 is memory input register, 6 is WAY address timing generator, 7 is decoder, 8 is address register ADD-REG , 9 is a decoder, 10 is a write data register WD-REG, 11 is a decoder, 12 is a read data register RD-REG, 1
3 is an OR gate, and 14 is a fetch data bus.

The illustrated storage device is capable of accessing, for example, 8 bytes of data, but for the sake of simplicity, only a 1-bit data access circuit is shown in the figure.

A control device (not shown) using the storage device supplies a write command GO.OP (GO signal and OP code), an address, and store data when writing to the storage device.

Memory 1 uses an interleave method to increase speed, and has a bank configuration consisting of N+1 independent memory sections, and these memory sections are
Address this as WAY~N WAY.
It is called a WAY address. Another WAY
The address given to the memory chip in the chip is called the chip address. When we simply say address here, we mean chip address + WAY address.

In this figure, store data bus 2 and fetch data bus 14 have a length of 8 bytes. It is also assumed that the chip address and WAY address each have multiple bits.

The address register ADD-REG8 is composed of N+1 WAY units in order to supply chip addresses to each WAY of the memory 1 separately. Similarly, write data register WD-REG1
0 and read data register RD-REG12
In correspondence with the WAY configuration of the memory 1, each of the WAY units is composed of N+1 WAY units in order to hold write data and read data.

The chip address supplied to the chip address line 3 passes through the memory input register 5 and is stored in any one WAY unit selected by the WAY address in the address register ADD-REG8.

The WAY address supplied to the WAY address 4 is applied to the WAY address timing generator 6 via the memory input register 5, and is outputted to the decoders 7, 9, and 11 at a predetermined timing. Note that the WAY address timing generator 6 also supplies a chip select signal CS and a write enable signal WE (not shown) to the memory chips of each WAY.

The output of decoder 7 is one of ADD-REG8.
This is a signal for selecting the WAY unit. Further, the decoder 9 transfers the store data supplied to the store data bus 2 to the write data register WD-
One corresponding to the WAY address of REG10
It has the function of being selectively input to the WAY unit. Similarly, decoder 11 decodes each WAY of memory 1.
Among the data read from the WAY address, only the data corresponding to the WAY address is read out from the data register RD-.
It has a function to input to the corresponding WAY unit of REG12.

Next, a more detailed operation of the specific example shown in the timing diagram of FIG. 3 will be explained. The example in Figure 3 is a write command (ST) and an address (ADD).
is output from the control device, 8 bytes (B) of store data is output with a delay of 1τ, and this command (ST) is issued again without emptying the address bus. It is something.

In Figure 2, the WAY address (WAY-
ADD) is input to the WAY address timing generator 6. Here, it is converted into a timed WAY address, and decoders 7, 9, and 11 address one of N WAY units in address register ADD-REG8, write data register WD-REG10, and read data register RD-REG12, respectively. Choose one.

As a result, the chip address is stored in the WAY unit of the ADD-REG that corresponds to the sent WAY address, and the chip address is stored in the WAY unit of the ADD-REG that corresponds to the WAY address that was sent.
The store data is stored in the WAY unit, and the CS and WE of the memory chip are output only to the corresponding WAY, so only the memory section of the selected WAY operates to complete the write.

The time required for this write depends on the value of τ, but is usually around 10τ, and during this period, this WAY
The memory section indicated by the address cannot be used for anything else (ie, it becomes BUSY TIME).

Therefore, as shown by the arrow between a, b, and c in Figure 3, if store data is sent again to the immediately next τ, it cannot be written to the same WAY, and it will be sent to another vacant WAY. It must be stored in the WAY that exists.
This BUSY-TIME management is generally performed on the control device side.

Next, in the case of a read operation, when the read command (FH) and address are sent to the storage device as shown by the arrow between a and b in FIG.
WAY ADD-REG8 corresponding to WAY address
The WAY unit, chip select CS, etc. are operated to read out the memory section of a specific WAY in the memory 1, and furthermore, the specific WAY unit in the RD-REG 12 is selected, and read data, that is, fetch data is set. The output of this RD-REG12 is set to "0" when it is not selected, so the outputs of N WAYs can be combined by simply ORing the outputs of each WAY unit. .

As shown by the arrows between a, b, and c in Figure 3, after the read command (FH) has been activated, a memory chip access time of usually several τ has elapsed, depending on the value of τ. The fetch data is output from the fetch data bus to the fetch data bus. So, at the next τ of GO.OP,
When a read command (FH) with a WAY address different from the above read command (FH) is activated, as shown in Figure d, 8 bytes ×
2 = 16 bytes of fetch data can be obtained continuously.

Furthermore, as shown in Figure 3a, write command (ST)
and read command (FH) to the storage device a total of 8 times (8τ), one transfer is 8 times (8τ).
Since it is a byte, a total of 64 bytes of data can be sent and received.

This is the conventional transfer method, and no matter how you change the write/read order, you cannot access and command a maximum of 64 bytes in 8τ.

[Problem that the invention seeks to solve]

By the way, as the data processing capabilities of recent electronic computers and the like that use such storage devices have improved, huge amounts of data have been written to the storage devices.
Read requests are increasing. Therefore, the storage device must process as much data as possible per unit time.

To this end, we transferred 8 bytes of data every 1τ and set it in the register group of each WAY, and after setting, we performed writing/reading within the time that the memory chip of each WAY could operate. .

In order to further increase the speed, it is possible to increase the number of WAYs and increase the storage capacity of 1WAY for large amounts of data, but this method has limitations due to hardware constraints.

Therefore, in order to achieve higher speed while keeping the number of WAYs and storage capacity constant, the upper limit of the data transfer amount of 64 bytes at 8τ must be further increased, as shown in Figure 3. There was a problem.

[Means for solving problems]

The present invention focuses on the usage rate of the store data bus and the fetch data bus, and improves the point that, for example, in the example shown in FIG. This increases the amount of data transferred.

The configuration of the present invention for this purpose includes a storage device that is composed of a plurality of basic memory banks and that is accessed by an address consisting of a bank address and an address within the bank, an address bus, a write data bus, and a read data bus. In the system, the plurality of basic memory banks are physically addressed as even numbers and odd numbers, and read commands and write commands are issued alternately by pairing the sequential even and odd bank addresses. , and only one of the even-numbered and odd-numbered bank addresses is supplied onto the address bus, and in the storage device, the other bank address is supplemented to access the corresponding basic memory bank, and the write data and It is characterized in that read data is continuously transmitted on a write data bus and a read data bus, respectively.

[Action of the invention]

In the present invention, one address for one instruction handles the amount of data for two addresses, and by issuing two consecutive instructions, one write instruction and one read instruction, With two consecutive addresses, both the store data bus and the fetch data bus will be used for 2τ. Therefore, by repeating writing, reading, writing, reading, etc., the usage efficiency of the address lines and data bus can be made 100%.

〔Example〕

The details of the present invention will be explained below with reference to Examples.

FIG. 1 is a timing diagram of one embodiment of the system of the present invention, which corresponds to the timing diagram of the example of the conventional system shown in FIG.

In Figure 1, a is the GO signal of the command and
ST16 represents a 16-byte access write command, and FE16 similarly represents a 16-byte access read command.

Also, b in the figure shows each instruction (GT16, FH16)
It represents the address that is output on the address line when the issuance of the
When divided into EVBN (even number) and ODD (odd number),
Only EVEN addresses are used. these
EVEN addresses are designated as 1E, 2E, 3E, and 4E for convenience. The storage device generates an ODD address based on this EVEN address. The generated ODD addresses are shown as 1O, 2O, 3O, and 4O.

Further, c in the figure represents store data supplied on the store data bus. One 16-byte store data is 8 bytes (8B) of EVEN address
and 8 bytes (8B) of the ODD address are combined. In the illustrated example, 1E, 1O, 3E,
Two 16-byte data (ie, four 8-byte data) indicated by the address 3O are consecutively supplied within 4τ.

Similarly, d in the figure represents memory 2E, 2O,
It represents two consecutive 16-byte data (ie, four 8-byte data) within 4τ read from addresses 4E and 4O and output on the fetch data bus.

First, in operation, the control device side sends an OP code (ST16) that instructs to write 16 bytes of data.
Send GO signal.

At this time, the address sent to the storage device is
If you select EVEN, the WAY address in the address will always be EVEN. Next, data is sent twice in succession of 8 bytes each. The address assignment at this time is EVEN for the first time and ODD for the second time.
shall be.

The storage device side identifies from the OP code that it is a 16-byte access request. By the way, the WAY address sent is EVEN, and it is specified that the data will be sent twice.
The first data is in the address register ADD-REG.
For the EVEN WAY unit, the following data is ODD
All you have to do is store it in the WAY unit.

In this way, in the case of 8-byte access, there is no need to add an address to each 8-byte data, and it is possible to send 2×8 bytes of data in 1τ.

In this case, 16 bytes of address are sent in 1τ, so unlike the conventional method, the address bus becomes free by 1τ. Therefore, another
Although it is possible to send 16 bytes worth of addresses, the store data bus cannot be used because the current write data is being sent twice consecutively onto the store data bus.

This free space on the address bus is used for fetch accesses so that the store data bus is not used (the fetch data bus is used instead).

In the next access at τ, the store data bus is free again, so a store access can be performed, but a fetch access cannot be performed because the fetch data bus is not free.

In this way, by controlling the control device to perform 16-byte accesses in the order of store/fetch/store/fetch, etc., bus usage efficiency can be made 100%. In the example shown in FIG. 1, access control for 64 bytes is performed with 4τ.

Furthermore, since the control device and the storage device can easily switch between 8-byte and 16-byte accesses using the OP code, the type of access can be used depending on the data structure of the access source.

Next, an example circuit for realizing these accesses will be described.

FIG. 4 shows the selection mechanism of the write data register WD-REG, and 9 and 10 in the figure correspond to the decoder and write data register WD-REG in FIG. 2, respectively. 15 is the ODD WAY SELECT required in the present invention.
This is a signal generation circuit.

FIG. 5 is an operation timing diagram of the circuit shown in FIG. 4, or represents signals of the parts indicated by . . . in FIG. 4.

In FIG. 4, the decoder 9 selects the WAY unit (O WAY to N WAY) of the WD-REG 10 at a timing such that the sent store data can be taken into the WD-REG 10. Therefore, the decoder 9 outputs SEL 00 WAY, SEL 01 WAY,
It has N+1 SELECT signal outputs.
The input to the decoder 9 is a timed WAY address supplied from a WAY address generator. Since this WAY address is only EVEN in the case of 16-byte access, the decoder 9
The output is only for even numbers, i.e. SEL 00 WAY,
SEL 02 WAY,...

The ODD WAY SELECT signal generation circuit 15 is
It has the function of replenishing the ODD WAY address from the EVEN WAY address during 16-byte access operation. This holds the EVEN output of the decoder 9 when the EVEN WAY address is input, and replaces the ODD output of the decoder 9 at the next τ, that is, the timing of the ODD WAY address.
It outputs a SELECT signal. Registers SEL 00 REG, SEL 02 REG, SEL 04 in the diagram
REG, . . . each have a function of holding the EVEN output of the decoder 9. Also a multiplexer
MPX 01, MPX 03, MPX 05, ... selects each ODD output of decoder 9 during 8-byte access operation, and selects the register output during 16-byte access operation.
SEL 00 REG, SEL 02 REG, SEL 04 REG,
It has a function to select the output of...

For example, depending on the WAY address, 0 WAY
When (EVEN WAY) is selected, the decoder 9 outputs a 1τ SELECT signal SEL 00 WAY, and as a result, the write data register is
WAY unit WD--REG 0 Gives the clock CLK shown only to WAY to store the data on the store data bus at that time.

Also, at this time, the output of decoder 9 SEL 00
WAY is set in register SEL 00 REG,
Then, the multiplexer is delayed by 1τ as shown in
Input to MPX 01.

During 16-byte access operation, MPX 01 uses the control signal SEL 16B shown as ODD WAY.
Since the state is set to select the output of SEL 00 REG shown by according to the SELET signal output timing, the CLK that is 1τ behind the CLK of the write data register is selected as shown by
Apply to WAY unit WD REG 1 WAY.
Therefore, the second 8-byte data on the store data bus at this time is stored in WD REG 1 WAY.

In this way, for any other EVEN WAY address, the even-numbered SELECT signal output from the decoder 9 is changed to the odd-numbered SELECT signal at the next τ.
A SELECT signal can be generated to selectively store data in each WAY unit of the write data register. The data of each WAY unit in the write data register is sent to the memory section for each WAY. At this time, the memory section
The WE signal is also input with a 1τ timing difference according to WAY's EVEN and ODD.

FIG. 6 shows the selection mechanism of the address register ADD-REG, and FIG. 7 is its operation timing diagram.

7 and 8 in FIG. 6 are the decoder and address register ADD-REG in FIG. 2, respectively.
It corresponds to Further, 16 is an ODD WAY SELECT signal generation circuit required by the present invention. This circuit 16 is similar to the circuit 15 in FIG.
EVEN WAY
Register SEL 00 to hold SELECT signal
REG etc. have been removed.

In addition, multiplexers MPX 01, MPX 03,
MPX 05, . . . , like that of circuit 15, are controlled to select the upper input by signal SEL 16B during a 16-byte access operation.

The operation is performed using the write data register WD- in Figure 4.
It is almost the same as in the case of REG, but the chip address is only sent 1τ, and EVEN/ODD
Since both WAY have the same value, EVEN/ODD are stored in the address register ADD-REG at the same time.

Therefore, there is no need to perform a 1τ delay operation like with DATA, and during a 16-byte access operation, for example, select 0 and 1 WAY (EVEN/ODD) at the same time and store 1τ chip address data in ADD-REG.

Next, the operation of the circuit shown in FIG. 6 will be explained with reference to FIG. The signals shown in FIG. 7 are those of the portions shown in the circuit of FIG.

For example, the WAY address of 0 WAY is WAY
When given from the address timing generator to the decoder 7, the SELECT signal from the decoder 7
SEL 00 WAY is output.

When accessing 16 bytes, MPX 01 has a SEL of
Since it is set to the upper side by 16B, the clock
CLK is an address register as shown in
It is simultaneously applied to the 0 WAY and 1 WAY units of ADD-REG 8, and the address data, ie, the chip address, is similarly stored in both WAY units.

The selection circuit for the read data register RD-REG is the write data register WD-REG shown in Figure 4.
Since it can be configured in the same manner as the selection circuit of , the explanation will be omitted.

In addition, in the above embodiment, only the EVEN WAY address was transmitted, but instead
It is clear that the same implementation can be achieved by transmitting only the ODD WAY address.

〔Effect of the invention〕

In conventional 8-byte access, it was necessary to send 1τ of address data for each data transmission. For this reason, when transferring a large amount of data at high speed, it has become a bus network, but with the present invention, by handling 2 x 8 bytes of data with 1τ address data, free space on the data bus is freed. It can be resolved. This increases bus usage efficiency to 100%, enabling faster data transfer. Further, the increase in circuitry required for this purpose can be negligible.

[Brief explanation of drawings]

FIG. 1 is a timing diagram of an access operation in one embodiment of the method of the present invention, FIG. 2 is a configuration diagram of a conventional storage system targeted by the present invention, and FIG. 3 is a timing diagram of an access operation of the conventional method. 4 is a circuit diagram of an embodiment of the selection mechanism of the write data register WD-REG, FIG. 5 is an operation timing diagram of the mechanism of FIG. 4, and FIG. 6 is a circuit diagram of an embodiment of the selection mechanism of the address register ADD-REG. FIG. 7 is an operation timing diagram of the circuit of FIG. 6. In the figure, 1 is a bank-configured memory, 2 is a store data bus, 3 is a chip address line, 4 is a WAY address line, 6 is a WAY address timing generator, 7, 9, and 11 are decoders, and 8 is an address register ADD- REG, 10 is the write data register
RD-REG, 12 is read data register, 14
is fetish data bus, 15 and 16 are ODD
Shows the WAY SELECT signal generation circuit.

Claims (1)

[Claims] 1. In a storage system comprising a storage device consisting of a plurality of basic memory banks and accessed by an address consisting of a bank address and an address in the bank, an address bus, a write data bus, and a read data bus, the plurality of basic memories physically addressing banks into even and odd numbers, and further issuing read and write commands alternately by pairing sequential even and odd bank addresses; Supply only one bank address on the address bus, and in the storage device, access the corresponding basic memory bank by replenishing the other bank address, and write data and read data.
An access control method in a storage system characterized by continuous transmission on a write data bus and a read data bus, respectively.