JPS61138153A - Method for measuring thermal fatigue of joining material - Google Patents

Method for measuring thermal fatigue of joining material

Info

Publication number
JPS61138153A
JPS61138153A JP26120684A JP26120684A JPS61138153A JP S61138153 A JPS61138153 A JP S61138153A JP 26120684 A JP26120684 A JP 26120684A JP 26120684 A JP26120684 A JP 26120684A JP S61138153 A JPS61138153 A JP S61138153A
Authority
JP
Japan
Prior art keywords
terminal
sample
measuring
heater
thermal fatigue
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26120684A
Other languages
Japanese (ja)
Inventor
Eiji Horikoshi
堀越 英二
Kaoru Hashimoto
薫 橋本
Hiroshi Kano
博司 鹿野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP26120684A priority Critical patent/JPS61138153A/en
Publication of JPS61138153A publication Critical patent/JPS61138153A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/02Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
    • G01N27/04Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
    • G01N27/041Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body

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  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)

Abstract

PURPOSE:To enable the continuous recording and observation of a thermal fatigue degree by adding the temp. cycle to the measuring instrument with operating the heater for measuring sample and refrigerator and by finding the variation in the resistance value of the joining material by four terminal method with flowing a current between the joining material of each one set with the state thereof. CONSTITUTION:A sample 9 is set to the inside of a refrigerator 10, the terminals 6, 7 of each solder ball 1 provided on the ceramics substrate 4 thereof are connected to each terminal of a scanner 11 and the terminal of the resisting body pattern 8 being provided on a tip 2 is connected to the terminal of a heater electric power adjuster 12. The electrifying circuit of the solder ball 1 of one set in two pieces is switched by the scanner 11 with the state of reaching the prescribed temp. by electrifying the sample 9 by the program of a controller 15 and the electric resistance is found by four terminal method with measuring in order using an ohmmeter 16, is displayed 17 and recorded 18. Then when dropped to the prescribed temp. it is heated to the prescribed temp. by electrifying with the motion of the heater power adjuster 12 again by the instruction of the controller 15. The variation in the resistance value in the solder ball joining part can be measured automatically.

Description

【発明の詳細な説明】 〔産業上の利用分野〕   □ 本発明は半導体rcチップなどの回路素子を配線基板に
装着する接合材料の熱波−労度測定方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] □ The present invention relates to a method for measuring heat waves and stress of a bonding material used to attach a circuit element such as a semiconductor RC chip to a wiring board.

情報処理装置の処理能力を向上するためにIC,LSr
などの半導体装置は小形化と大容量化が進められている
が同時に実装方法も改良されている。
IC, LSr to improve the processing capacity of information processing equipment
Semiconductor devices such as these are becoming smaller and larger in capacity, and at the same time, mounting methods are also being improved.

すなわち従来の半導体装置はチップ毎にセラミック基板
に装着して樹脂封止を行った後、樹脂ケースなどに収納
するパフケージ構造がとられており、これをプリント配
線基板上にパターン形成しであるランド或いはスルーホ
ールに装着する実装形態がとられていた。
In other words, conventional semiconductor devices have a puff cage structure in which each chip is mounted on a ceramic substrate, sealed with resin, and then stored in a resin case. Alternatively, it has been mounted in a through hole.

然し、パッシベーション技術の進歩と共に実装方法も改
良され、複数個のLSI素子をセラミック多層基板に搭
載してLSIモジュールを作り、これをプリント配線基
板に装着する方法がとられようとしている。
However, with advances in passivation technology, mounting methods have also been improved, and a method is now being adopted in which a plurality of LSI elements are mounted on a ceramic multilayer board to create an LSI module, and this is mounted on a printed wiring board.

かかる場合、LSI素子のセラミック基板への装着は半
田ポール或いは半田バンブなどの接合材料を用いて行わ
れる。
In such a case, the LSI element is attached to the ceramic substrate using a bonding material such as a solder pole or a solder bump.

すなわちLSI素子の周辺部などに設けた導体回路の端
子部(パッド)とセラミック基板上にパターン形成され
ている導体線路のランドとを半田ボールを用いて接合す
るか、或いはセラミック基板上の導体線路に設けられて
いる半田バンプにLSIモジュールのパッドを位置合わ
せした後、熱圧着することにより接合が行われている。
In other words, the terminals (pads) of a conductor circuit provided around the periphery of an LSI element and the lands of a conductor line patterned on a ceramic substrate are bonded using solder balls, or the conductor line on a ceramic substrate is After aligning the pads of the LSI module with the solder bumps provided on the board, the bonding is performed by thermocompression bonding.

このようにして半導体素子はセラミック多層基板に回路
接続されるが、半導体基板とセラミック基板とは熱膨張
係数が異なるために使用中に接合材料にストレスが発生
し、次第にこれが蓄積して柊には接合材料が破断すると
云う問題がある。
In this way, the semiconductor element is connected to the ceramic multilayer board, but since the semiconductor and ceramic boards have different coefficients of thermal expansion, stress is generated in the bonding material during use, and this gradually accumulates, causing the There is a problem in that the bonding material breaks.

すなわち半導体素子は板金低温に保持されていても使用
時には発熱してかなりの温度に達しており、通電を停止
すると元の温度に戻るが、この際の熱膨張の差によるス
トレスは接合材料が受け、これが繰り返えされる結果、
接合部でのクランク発生や断線障害が起こることになる
In other words, even if the semiconductor element is kept at a low temperature, it generates heat during use and reaches a considerable temperature.When the current is turned off, the semiconductor element returns to its original temperature, but the stress due to the difference in thermal expansion is not absorbed by the bonding material. , as a result of repeating this,
This will cause cranking and disconnection problems at the joints.

本発明はこのようにして発生する接合材料の熱疲労度を
測定する方法に関するものである。
The present invention relates to a method for measuring the degree of thermal fatigue of the bonded material thus generated.

〔従来の技術〕[Conventional technology]

従来の熱疲労度測定方法は低温と高温とに保持された二
つの恒温層を用意し、この間で試料を移動し、顕微鏡を
用いてクランクの有無を検出する方法がとられていた。
The conventional method for measuring thermal fatigue has been to prepare two constant-temperature layers, one kept at a low temperature and one at a high temperature, move the sample between them, and use a microscope to detect the presence or absence of a crank.

然し、この方法によると半導体基板(以下略してチップ
)とセラミック基板とが同時に熱膨張と収縮を行うため
にシュミレーションが行えないと云う問題がある。
However, this method has the problem that simulation cannot be performed because the semiconductor substrate (hereinafter referred to as a chip) and the ceramic substrate undergo thermal expansion and contraction at the same time.

すなわち実際にはチップが通電により発熱して膨張し、
この熱が接合材料を通してセラミック配線基板に伝導さ
れて基板の膨張が起こり、この間に時間のずれがあり、
そのため複雑な形でストレスが接合材料に発生している
In other words, the chip actually heats up and expands when energized.
This heat is conducted to the ceramic wiring board through the bonding material, causing expansion of the board, and there is a time lag during this time.
As a result, stress is generated in the joining materials in a complex manner.

また破断の検出は蓄積したストレスが解消した結果であ
り、破断に到る中間過程は判からす、また顕微鏡観察で
は微細なりラックは検出が難しいと云う問題がある。
Furthermore, the detection of fracture is the result of the release of accumulated stress, and the intermediate processes leading to fracture are unclear, and there is also the problem that microscopic racks are difficult to detect by microscopic observation.

これらのことから現実に即した接合材料の熱疲労の測定
方法はなく、かかる測定方法の実用化が要望されていた
For these reasons, there is no practical method for measuring thermal fatigue of bonding materials, and there has been a desire to put such a measuring method into practical use.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

以上説明したように実装状態に近い状態で接合材料の熱
疲労度を測定できる方法がないことが問題である。
As explained above, the problem is that there is no method that can measure the degree of thermal fatigue of bonding materials in a state close to the mounted state.

〔問題点を解決するための手段〕[Means for solving problems]

上記の問題は複数個の接合材料により接−合する上下の
基板を用いて測定試料を構成し、上側基板にはヒータお
よび各接合材料を結ぶ導体線路をパターン形成し、一方
下側基板の接合材料装着位置の各々には電流端子と電圧
測定端子をパターン形成してあり、ヒータと冷凍機を動
作させて測定装置に温度サイクルを加え、この状態で各
一組づつの接合材料間に電流を通じ、四端子法により該
接合材料の抵抗値変化を求めることを特徴とする接合材
料の熱疲労度測定方法により解決することができる。
The above problem can be solved by constructing a measurement sample using upper and lower substrates that are bonded using multiple bonding materials, forming a pattern on the upper substrate with a heater and a conductor line connecting each bonding material, while bonding the lower substrate. A current terminal and a voltage measurement terminal are patterned at each material mounting position, and the heater and refrigerator are operated to apply a temperature cycle to the measuring device, and in this state, current is passed between each set of bonding materials. This problem can be solved by a method for measuring the degree of thermal fatigue of a bonding material, which is characterized by determining the change in resistance of the bonding material using a four-terminal method.

〔作用〕[Effect]

本発明はチップ自体に発熱体を設け、これに通電する電
流をON −OFFすると共に環境温度も最高温度から
最低温度まで変化させることにより実装状態に近い状態
で熱疲労が起こるようにすると共に、二個の接合材料を
繋ぐ複数個の回路を設け、これら回路の電気抵抗変化を
四端子法で自動測定することにより熱疲労度を連続的に
記録すると同時に観察できるようにしたものである。
The present invention provides a heating element in the chip itself, turns on and off the current flowing through it, and changes the environmental temperature from the highest temperature to the lowest temperature, so that thermal fatigue occurs in a state close to the mounted state. A plurality of circuits are provided to connect two bonding materials, and changes in electrical resistance of these circuits are automatically measured using the four-terminal method, thereby making it possible to continuously record and observe the degree of thermal fatigue at the same time.

〔実施例〕〔Example〕

チップをセラミ・7り基板に装着する方法には半田ボー
ルを用いる方法とバンブを使用する場合などがあるが、
ここでは前者の場合について説明する。
There are two ways to attach a chip to a ceramic board: one using solder balls and the other using bumps.
Here, the former case will be explained.

第1図は本発明に係る接合材料の熱疲労測定用試料の正
面図、第2図はこの斜視図また第3図は本発明に係る測
定装置のブロックダイヤグラムである。
FIG. 1 is a front view of a sample for thermal fatigue measurement of a bonding material according to the present invention, FIG. 2 is a perspective view thereof, and FIG. 3 is a block diagram of a measuring device according to the present invention.

すなわち第1図と第2図とに示すように半田ボール1は
チップ2に設けられているパッド3とセラミック基板4
のスルーホール部に設けられているパッド5を結ぶこと
により回路接続が行われるが、この測定用試料の場合に
はセラミック基板にはスルーホールは無く、その代わり
に四端子法で抵抗値変化を測定するための電流端子6と
電圧測定端子7とがパターン形成されている。
That is, as shown in FIGS. 1 and 2, the solder ball 1 is connected to the pad 3 provided on the chip 2 and the ceramic substrate 4.
Circuit connection is made by connecting the pads 5 provided in the through-hole portions of the ceramic substrate, but in the case of this measurement sample, there are no through holes in the ceramic substrate, and instead, the resistance value change is measured using the four-terminal method. A current terminal 6 and a voltage measurement terminal 7 for measurement are formed in a pattern.

またチップ2の上にはニクロム(Ni−Cr) 蒸着な
どの方法によって抵抗体パターン8が設けである。
Further, a resistor pattern 8 is provided on the chip 2 by a method such as nichrome (Ni--Cr) vapor deposition.

なおこの実施例においては第2図に示すように抵抗体パ
ターン8をS字状に形成することによりチップ2の全域
を均等に加熱するよう工夫しである。
In this embodiment, as shown in FIG. 2, the resistor pattern 8 is formed in an S-shape so that the entire area of the chip 2 can be heated evenly.

またチップ2お裏面には複数の半田ボール1を繋ぐ導体
線路がパターン形成されており、任意の二個の半田ボー
ルを繋いで通電できるよう構成されている。
Furthermore, a pattern of conductive lines connecting a plurality of solder balls 1 is formed on the back surface of the chip 2, so that any two solder balls can be connected and energized.

第3図はか\る試料9に温度サイクルを与えて熱疲労度
を測定するブロックダイヤグラムを示すもので、試料9
は冷凍機10の中に設置すると共にセラミック基板4に
設けられている各半田ボールlの電流端子6と電圧測定
端子7はスキャナ11の各端子に接続されており、また
チップ2の上に設けられている抵抗体パターン8の端子
はヒータ電力調節器12の端子に接続されている。
Figure 3 shows a block diagram for measuring the degree of thermal fatigue by subjecting sample 9 to a temperature cycle.
is installed in the refrigerator 10, and the current terminal 6 and voltage measurement terminal 7 of each solder ball l provided on the ceramic substrate 4 are connected to each terminal of the scanner 11, and the The terminals of the resistor pattern 8 are connected to the terminals of the heater power regulator 12.

また試料9の基板温度は温度計13.14で側温されヒ
ータ電力調節器12にフィードバックされるようになっ
ている。
Further, the substrate temperature of the sample 9 is measured by thermometers 13 and 14 and fed back to the heater power regulator 12.

ここで本発明に係る第3図の機構を説明すると次のよう
になる。
The mechanism shown in FIG. 3 according to the present invention will now be explained as follows.

コントローラー5のプログラムにより試料9に通電して
一定の温度に達した後、電流を切り、所定の温度に達し
た状態でスキャナー1により二個で一組となっている半
田ボール1の通電回路を切り換えて抵抗計16を用い、
四端子法で順次全部の組合せの電位差を測定し、これか
ら電気抵抗を求め、表示装置17に表示すると共に記録
装置18に記録しておく。
After the sample 9 is energized according to the program of the controller 5 and reaches a certain temperature, the current is turned off, and when the predetermined temperature is reached, the energized circuit of the two solder balls 1 is connected by the scanner 1. Switch and use the resistance meter 16,
The potential differences of all the combinations are sequentially measured using the four-terminal method, and the electrical resistance is determined from the electrical resistance, which is displayed on the display device 17 and recorded in the recording device 18.

次に温度が下がって規定の温度に達した後はコントロー
ラー5の指示により、再びヒータ電力調節器12が動作
して試料9に通電し、所定の温度まで試料9を加熱する
Next, after the temperature decreases and reaches a specified temperature, the heater power regulator 12 operates again according to instructions from the controller 5 to energize the sample 9 and heat the sample 9 to a specified temperature.

このように本発明に係る試料構成および測定回へ 路を使用すれば、温度サイクルを繰り返してゆく過程で
の半田ボール接合部における抵抗値変化を自動計測する
ことができる。
As described above, by using the sample configuration and measurement circuit according to the present invention, it is possible to automatically measure the change in resistance value at the solder ball joint during the process of repeating temperature cycles.

第4図はチップ1として15 X 15nのシリコン(
Si)チップを、またセラミック基板4としてアルミナ
(α−AI203 )を用い、この導体パターンとパッ
ド3.5をそれぞれ0.05μmのニクロム(Ni−C
r)と1μmの金(Au)の二層で形成し、一方半田ポ
ール1として直径300 μmの鉛(Pb)−63錫(
Sn)を用いて接合した試料に本発明に係る測定方法で
0−100℃の温度サイクルを5分間の周期で連続して
加えた場合の電気抵抗の変化を示すものである。
Figure 4 shows a 15 x 15n silicon chip (chip 1).
Alumina (α-AI203) is used as the ceramic substrate 4, and the conductor pattern and pad 3.5 are each made of nichrome (Ni-C) with a thickness of 0.05 μm.
r) and 1 μm gold (Au), while lead (Pb)-63 tin (300 μm in diameter) is used as the solder pole 1.
2 shows the change in electrical resistance when a temperature cycle of 0 to 100° C. is continuously applied at a period of 5 minutes to a sample bonded using Sn) using the measuring method according to the present invention.

この特性曲線19から260回付近でストレスのために
約5%の抵抗値の増加を生じ、その後320回付近で破
断した状態を示している。
This characteristic curve 19 shows that the resistance value increased by about 5% due to stress around 260 times, and then broke around 320 times.

このように本発明によれば実装形態に近似した状態で熱
疲労度を測定することができ、破断に到る前のストレス
の蓄積状態を明瞭に測定することができる。
As described above, according to the present invention, the degree of thermal fatigue can be measured in a state similar to the mounting form, and the state of stress accumulation before breakage can be clearly measured.

〔発明の効果〕〔Effect of the invention〕

以上記したように本発明の実施により接合材料の温度サ
イクルによる熱疲労度の測定を連続的にまた自動的に測
定することが可能となり、接合材料の改良に寄与するこ
とが可能となる。
As described above, by implementing the present invention, it becomes possible to continuously and automatically measure the degree of thermal fatigue of bonding materials due to temperature cycles, and it becomes possible to contribute to the improvement of bonding materials.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る熱疲労度測定用試料の構成を示す
正面図、 第2図はこの斜視図、 第3図は本発明に係る測定装置のブロックダイヤグラム
、 第4図は接合材料の測定結果、 である。 図において、 1は半田ボール、    2はチ・ノブ、3.5はパッ
ド、     4はセラミック基板、6は電流端子、 
    7は電圧測定端子、8は抵抗体パターン、  
 9は試料、19は特性曲線、 である。 ¥  1  図 へ〇ツド 蔓  Z 圓 P 3 幻 乎 4 目
Fig. 1 is a front view showing the structure of a sample for measuring thermal fatigue degree according to the present invention, Fig. 2 is a perspective view thereof, Fig. 3 is a block diagram of a measuring device according to the present invention, and Fig. 4 is a diagram of a bonding material. The measurement result is . In the figure, 1 is a solder ball, 2 is a chi knob, 3.5 is a pad, 4 is a ceramic board, 6 is a current terminal,
7 is a voltage measurement terminal, 8 is a resistor pattern,
9 is a sample, 19 is a characteristic curve. ¥ 1 Go to figure〇 Tsudo vine Z EnP 3 Genyu 4 eyes

Claims (1)

【特許請求の範囲】[Claims] 複数個の接合材料により接合する上下の基板を用いて測
定試料を構成し、上側基板にはヒータおよび各接合材料
を結ぶ導体線路をパターン形成し、一方下側基板の接合
材料装着位置の各々には電流端子と電圧測定端子をパタ
ーン形成してあり、ヒータと冷凍機を動作させて測定装
置に温度サイクルを与え、この状態で各一組づつの接合
材料間に電流を通じ、四端子法により該接合材料の抵抗
値変化を求めることを特徴とする接合材料の熱疲労度測
定方法。
A measurement sample is constructed using upper and lower substrates that are bonded using multiple bonding materials, and a heater and a conductor line connecting each bonding material are patterned on the upper substrate, while a pattern is formed on each of the bonding material mounting positions on the lower substrate. The device has a pattern of current terminals and voltage measurement terminals, and the heater and refrigerator are operated to give the measurement device a temperature cycle. In this state, current is passed between each pair of bonding materials, and the four-terminal method is used to measure the temperature. A method for measuring the degree of thermal fatigue of a joining material, characterized by determining a change in the resistance value of the joining material.
JP26120684A 1984-12-11 1984-12-11 Method for measuring thermal fatigue of joining material Pending JPS61138153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26120684A JPS61138153A (en) 1984-12-11 1984-12-11 Method for measuring thermal fatigue of joining material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26120684A JPS61138153A (en) 1984-12-11 1984-12-11 Method for measuring thermal fatigue of joining material

Publications (1)

Publication Number Publication Date
JPS61138153A true JPS61138153A (en) 1986-06-25

Family

ID=17358615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26120684A Pending JPS61138153A (en) 1984-12-11 1984-12-11 Method for measuring thermal fatigue of joining material

Country Status (1)

Country Link
JP (1) JPS61138153A (en)

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JP2007255925A (en) * 2006-03-20 2007-10-04 Espec Corp Joint evaluation method and joint evaluation device
JP2007255926A (en) * 2006-03-20 2007-10-04 Espec Corp Joint evaluation method and joint evaluation device
WO2019097801A1 (en) * 2017-11-17 2019-05-23 日立金属株式会社 Sensor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005274381A (en) * 2004-03-25 2005-10-06 Tohoku Techno Arch Co Ltd Nondestructive inspection method and nondestructive inspection apparatus of back defect and material characteristics by electromagnetic method
JP2007255925A (en) * 2006-03-20 2007-10-04 Espec Corp Joint evaluation method and joint evaluation device
JP2007255926A (en) * 2006-03-20 2007-10-04 Espec Corp Joint evaluation method and joint evaluation device
JP4669424B2 (en) * 2006-03-20 2011-04-13 エスペック株式会社 Bonding evaluation method and apparatus
JP4728852B2 (en) * 2006-03-20 2011-07-20 エスペック株式会社 Bonding evaluation method and apparatus
WO2019097801A1 (en) * 2017-11-17 2019-05-23 日立金属株式会社 Sensor

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