JP2675763B2 - Semiconductor wafer inspection system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection device for inspecting a large number of IC chips to be inspected on a semiconductor wafer.

[0002]

2. Description of the Related Art Generally, an IC is used to inspect an IC chip formed on a semiconductor wafer or a product under manufacturing thereof.
The chip group is checked element by element with an inspection electrode, or a contact is brought into contact with the external electrode group of each IC chip to repeat the inspection. At this time, while moving the semiconductor wafer, each IC chip formed on the wafer is inspected.

[0003]

Therefore, it takes a lot of time to inspect a large number of IC chips on a wafer, and the inspection cost is high.

Furthermore, since processing of electric signals and response signals necessary for inspection depends entirely on external inspection circuits, it has become necessary to detect weak signals and input / output high-frequency signals as in recent years. In the inspection, there are cases where the inspection cannot be performed due to the attenuation and noise due to the circuit on the way.

Recently, there is an increasing demand for performing a burn-in test on an IC package on a bare IC chip. In this burn-in test of the bare IC chip, the IC chip is directly burned in as it is without packaging the IC chip. However, the contact group is brought into contact with the electrode pad group of the IC chip and the electrical contact is performed through the contact group in a high temperature atmosphere. I / O must be done.

The electrode pad group of the IC chip is a large number of hundreds of pads with a fine pitch, and the contact group that contacts it is also fine and numerous. Therefore, in order to burn-in at a high temperature while keeping the position of the electrode pad group and the contact group of the IC chip in contact with each other, the contact is not deformed by heat or the contact or
It is necessary that the material holding the C-chip does not undergo thermal deformation. That is, there is a limit to making the contact pitch fine, and there is a problem that the material holding the contact causes thermal expansion or deformation due to high heat in burn-in, and the position of the contact point is displaced, resulting in lack of reliability.

[0007]

As a means for solving the above problems, the present invention targets a semiconductor wafer 1 having a large number of IC chips 1a to be inspected, and a large number of IC chips 2a to be inspected. The inspection card 2 is formed by the semiconductor wafer that it has. The inspection IC chip is provided with a gate circuit control signal wiring 4a for controlling opening / closing of each gate circuit 2b and each inspection I via each gate circuit 2b.
An input signal wiring 4b for supplying an inspection signal and power to the C chip 2a and an output signal wiring 4c for extracting a response signal from each IC chip 1a to be inspected and the inspection IC chip 2a via each gate circuit are provided. The wirings 4a, 4b, 4c
Is connected to the external inspection circuit 6.

The gate circuit 2b is connected in parallel to the wiring 4a so that the gate circuit opening / closing control signal S ₁ can be individually supplied from the external inspection circuit 6 to the gate circuit control signal wiring 4a. Further, each gate circuit 2b is connected in parallel to the wiring 4b so that the inspection signal S ₂ and the power can be individually supplied from the external inspection circuit 6 to the input signal wiring 4b. From the gate circuit 2b to the external inspection circuit 6 on the output signal wiring 4c.
Each gate circuit 2b is connected in parallel to the wiring 4c so that the response signal S ₄ can be individually taken out.

Further, a plurality of units of inspection IC chips 2a are connected to each gate circuit 2b so that each gate circuit 2b and each inspection IC chip 2a can individually exchange the inspection / response signal S ₃ and supply power. And any gate circuit 2b
Is selectively opened by the gate circuit opening / closing control signal from the control signal wiring 4a supplied from the external inspection circuit, whereby the input signal wiring 4b supplied from the external inspection circuit 6 is opened.
The inspection signal and power from the inspection circuit I flow into the inspection IC chips 2a of a plurality of units corresponding to the gate circuit 2b, and the inspection I
IC chip 1 to be inspected that is in contact with C chip 2a
The inspection / response signal is output by energizing a, and the inspection / response signal is introduced into the output signal wiring 4c through the closed gate circuit 2b and taken into the external inspection circuit 6.

[0010]

According to the present invention, all the unit IC chips to be inspected on the semiconductor wafer are divided into a plurality of groups for each gate circuit, and each gate circuit is controlled by the gate circuit opening / closing control signal from the gate circuit control signal wiring. Is selectively opened to energize only the inspected IC chips and the inspected IC chips belonging to the group connected to the opened gate circuit, and at the same time, the power through the input signal wiring is applied to only the IC chip. And an inspection signal are supplied, the response signal is taken into the external inspection circuit through the output signal wiring, and all the IC chips to be inspected are energized for each group (other groups are completely killed). Moreover, the quality can be grasped for each group. Moreover, such an inspection method can be appropriately implemented by the present invention. Since power is supplied to and energized only to the IC chip to be inspected and the IC chip to be inspected connected to the gate circuit, noise can be effectively prevented from flowing into each other and to the non-inspected groups or the external inspection circuit. Each inspection can be performed properly.

If an IC chip that has not been inspected is placed in a state where power is supplied, if a short circuit damage occurs in this IC chip, all current will flow through this IC chip, and power will be supplied to the IC chip to be inspected. Although not performed, the present invention can effectively prevent such a problem.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention has a large number of ICs to be inspected as shown in FIG.
The semiconductor wafer 1 having the chip 1a is an inspection target.

In FIG. 2, an IC chip 1a to be inspected formed on the semiconductor wafer 1 is pasted on a flexible plastic sheet 1c in a separated state. The plastic sheet 1c is a thermoplastic film or a plastic film having an adhesive layer on the surface. The semiconductor wafer 1 to be inspected means one in the state shown in FIG. 1 or FIG.

On the other hand, the inspection card 2 is formed by a semiconductor wafer on which a large number of inspection IC chips 2a are formed.

Therefore, the card 2 is manufactured based on the known semiconductor wafer forming technique, and has the same material and the same effect as the semiconductor wafer 1 to be inspected.

In FIG. 3, the inspection IC chip 2a and the gate circuit 2b are shown separately to facilitate understanding, but the inspection card 2, that is, a plurality of inspection IC chips formed on a semiconductor wafer. 2a is an object to be inspected I to be inspected
It is composed of a plurality of gate circuits 2b formed by a switching circuit group which operates the C chip 1a for each unit group, and a bump 5 group which comes into contact with the electrode pad 1b group of the IC chip 1a to be inspected.

Further, as shown in FIG. 3, the inspection card 2 further includes gate circuit control signal wiring 4a for controlling the opening / closing of each gate circuit 2b, and each inspection IC via each gate circuit 2b.
An input signal wiring 4b for supplying an inspection signal and power to the chip 2a and an output signal wiring 4c for extracting a response signal from each IC chip 1a to be inspected and each inspection IC chip 2a via each gate circuit 2b are provided. Each wiring 4a, 4b, 4c
Is connected to the external inspection circuit 6.

The gate circuit control signal wiring 4a is provided with an individual control signal S from the external inspection circuit 6 to each gate circuit 2b.
Each gate circuit 2b to the wiring 4a so that ₁ can be supplied
Are connected in parallel, and the inspection signal S from the external inspection circuit 6 to each gate circuit 2b is individually connected to the input signal wiring 4b.
₂ and each gate circuit 2b are connected in parallel to the wiring 4b so that power can be supplied, and the response signal S ₄ can be individually taken out from each gate circuit 2b to the external inspection circuit 6 on the output signal wiring 4c. As described above, each gate circuit 2b is connected in parallel to the wiring 4c.

Further, a plurality of units of the inspection IC chips 2a are connected to a unit gate circuit 2b so that the inspection / response signal S ₃ can be exchanged individually between the gate circuits 2b and the inspection IC chips 2a. Another unit gate circuit 2b
The other plural units of inspection IC chips 2a are connected to.

All the above-mentioned connections between the respective wirings 4a, 4b, 4c and the gate circuit 2b and the inspection IC chip 2a are formed by a known wafer manufacturing technique for forming IC chips on a semiconductor wafer.

On the other hand, bumps 5 which come into contact with the electrode pads 1b of the IC chip 1a to be inspected are formed on the surface of the inspection IC chip 2a on the semiconductor wafer forming the inspection card 2, and the gate circuit 2b has the bumps 5b. Connected to 5.

The inspection IC chip 2a has the bumps 5
Signals are exchanged via the contact between the electrode pad 1b of the IC chip 1a to be inspected.

The bump 5 group is formed of, for example, minute plastic balls 5a as shown in FIG.
This plastic ball 5a is an elastic body having a metal plating coat 5'on its surface. Since it is a plastic, it can be manufactured to have a very small diameter, and the proper elasticity required for pressure contact can be secured.

As another example, the bump 5 is formed by a metal ring 5b as shown in FIG. 7, and the circumferential surface of the metal ring 5b is used as a pressure contact point.

As still another example, the bump 5 is formed by wire bonding 5c as shown in FIG.

Each of the plastic ball 5a and the metal ring 5b has an inspection IC chip 2 at one point on its circumferential surface.
It is adhered to the electrode pad 2c on the surface of a, and one point on the opposite side is used as a pressure contact point with the electrode pad 1b.

The wire bonding 5c is formed by melting and separating the tip of a thin wire on the surface of the electrode pad, and the sharp tip is formed on the electrode pad 1b.
It is the point of pressure contact with.

As shown in FIG. 4, the semiconductor wafer 1 to be inspected is placed on the inner bottom surface of the accommodation chamber 8 formed on the upper surface of the inspection stage 7. The stage 7 is heated by the heater 11 as needed.

On the other hand, the inspection card 2 made of a semiconductor wafer has bumps 5 of which the electrode pads 1 of the IC chip 1a to be inspected.
The semiconductor wafer 1 is superposed on the semiconductor wafer 1 while being aligned so as to contact with b.

The inspection card 2 covers the accommodation chamber 8 in which the semiconductor wafer 1 is accommodated, and when the gas in the accommodation chamber 8 is vacuumed through the suction port 9 provided on the stage 7, the inspection card 2 is inspected for the semiconductor wafer 1. Bump 5 pressed against the surface
A pressure contact between the group and the electrode pad 1b is obtained.

The stage 7 is provided with an elastic sealing 10 for supporting the inspection card 2 around the accommodation chamber 8, that is, around the semiconductor wafer 1. The inspection card 2 is pressed against the elastic sealing 10 by the vacuum to keep airtightness. The pressure contact state between the bump group 5 and the electrode pad 1b is maintained.

FIG. 5 shows the semiconductor wafer 1 and the inspection card 2 described above.
3 is an enlarged view of the contact portion of the above, and signals are exchanged through contact between the two bump groups 5 and the electrode pad 1b.

Thus, in the state shown in FIGS. 4 and 3, one of the gate circuit 2b groups is selectively opened by the gate circuit opening / closing control signal from the control signal wiring 4a supplied from the external inspection circuit 6. (Gate-on state), so that the inspection signal and power of the input signal wiring 4b supplied from the external inspection circuit 6 flow into a plurality of units of inspection IC chips 2a corresponding to the gate circuit 2b, and the inspection IC chips 2a Correspondingly contacted IC chip 1a to be inspected is energized to output an inspection / response signal. This inspection / response signal is introduced into the output signal wiring 4c via the gate circuit 2b whose gate is turned on, and taken into the external inspection circuit 6.

While the above inspection is being performed, all the other gate circuits 2b are placed in the closed state (gate off state) to prepare for the next command.

That is, by opening / closing each gate circuit 2b through the control signal wiring 4a, a plurality of units of the inspection IC chip 2a and the inspection IC chip 1a are selected from the outside while the inspection target semiconductor wafer of the inspection target semiconductor wafer is selected. The plurality of IC chips 1a to be inspected are electrically inspected one after another. Therefore, there are no mechanical operations at all and a large number of inspected objects I on a semiconductor wafer are tested.
The C chip 1a can be inspected at high speed.

On the other hand, in the burn-in test, all ICs to be inspected
Since it is necessary to keep the chip 1a in the operating state, it is assumed that the gate circuit 2b connects the signal of the input signal wiring 4a necessary for the operation of the IC chip to be inspected to the bump 5 group in the normal state.

As an example, on the inspection card 2, that is, on the inspection semiconductor wafer, an amplifier circuit for a weak signal, which is a part of the external inspection circuit 6, and an IC chip for an inspection determination circuit for determining the quality of the IC chip to be inspected. Can be formed. This embodiment is effective as a countermeasure against this noise when the line length connected to the external inspection circuit 6 is long and causes a noise problem.

Further, according to the present invention, the inspection target I
The case where the above-mentioned inspection is performed by directly contacting the electrode pad 1b of the C chip 1a and the electrode pad 2b of the inspection IC chip 2a is included.

Further, according to the present invention, the above-mentioned inspection can be performed without providing the bump 5 with the conductive elastomer interposed between the both 1a and 2a.

[0040]

According to the present invention, the gate circuit is selectively opened and closed through the gate circuit control signal wiring, and only the inspection IC chip and the inspected IC chip connected to the opened gate circuit are connected through the input signal wiring. Is supplied to the external inspection circuit through the output signal wiring, and all the IC chips to be inspected are energized for each group (ICs belonging to a group not inspected).
Chips have been completely killed), and the defects can be grasped for each group. Moreover, such an inspection method can be appropriately implemented by the present invention. Since power is supplied to and energized only to the IC chip to be inspected and the IC chip to be inspected connected to the gate circuit, noise can be effectively prevented from flowing into groups and groups not inspected, and inspection for each group can be performed. You can do it properly.

If the IC chip that has not been inspected is supplied with power, if a short circuit damage occurs in this IC chip, the entire current will flow through this IC chip and the IC chip to be inspected will not be supplied with power. Although not performed, the present invention can effectively prevent such a problem.

The inspection circuit element, wiring, and connection of the inspection card made of the above semiconductor wafer can be easily manufactured by the conventional semiconductor wafer forming technique, and the inspection device can be downsized and the cost can be reduced.

Further, since the semiconductor wafer to be inspected can be manufactured from the same material as that of the semiconductor wafer to be inspected, it is possible to effectively prevent the displacement of the contact portion due to the thermal expansion due to the heat at the time of burn-in inspection, and to greatly improve the reliability of inspection. You can

Further, by providing bumps on the electrode pads of the IC chip to be inspected formed by the wafer manufacturing technique, the accuracy can be improved and the fine pitch can be coped with. That is, it is possible to overcome the manufacturing positional accuracy and cost problems when the conventional probers (contactors) are arranged on the substrate at a fine pitch.

According to the present invention, a large number of IC chips formed on a semiconductor wafer can be inspected efficiently and at low cost without any mechanical operation, and it is possible to request inspection in a bare chip state before packaging and supply bare chips. It can properly respond to the inspection problems involved.

[Brief description of the drawings]

FIG. 1 is a plan view of an inspection card or a semiconductor wafer to be inspected.

FIG. 2 is a side view of the same.

FIG. 3 is a plan view illustrating circuit elements, wirings, and signal flows formed on an inspection card made of a semiconductor wafer.

FIG. 4 is a cross-sectional view of an inspection device inspecting a semiconductor wafer to be inspected using the inspection card.

FIG. 5 is an enlarged side view showing a contact state between an inspection card and a semiconductor wafer to be inspected.

FIG. 6 is an enlarged view showing an example of bumps attached to the surface of the inspection IC chip on the inspection card.

FIG. 7 is an enlarged view showing another example of the bump.

FIG. 8 is an enlarged view showing still another example of the bump.

[Explanation of symbols]

 1 semiconductor wafer to be inspected 1a IC chip to be inspected on the above semiconductor wafer 2 inspection card 2a consisting of a semiconductor wafer 2a inspection IC chip on the above inspection card 2b gate circuit on the inspection card 4a control signal wiring on the inspection card 4b same Input signal wiring 4c Same output signal wiring 6 External inspection circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/66 H01L 21/66 H

Claims (1)

(57) [Claims] 1. A semiconductor wafer (1) having a large number of IC chips (1a) to be inspected is an object to be inspected, and an inspection card (2) is formed by a semiconductor wafer having a large number of inspection IC chips (2a). ) Is formed, and the inspection IC chip (2a) has a gate circuit (2
b), a gate circuit control signal wiring (4a) for controlling opening / closing of each gate circuit (2b), and each gate circuit (2b)
Input signal wiring (4b) for supplying an inspection signal or power to each inspection IC chip (2a) via each, and each inspection IC chip (1a) and inspection IC chip (2a) via each gate circuit. Output signal wiring (4)
c) and the wirings (4a), (4b), (4c)
Is connected to an external inspection circuit (6), and the gate circuit control signal wiring (4a) is individually connected to the gate circuit opening / closing control signal (S ₁ ) from the external inspection circuit (6) to each gate circuit (2b).
So that the gate circuit (2
b) are connected in parallel, and the input signal wiring (4b)
The gate circuit (2b) is connected in parallel to the wiring (4b) so that the inspection signal (S ₂ ) and power can be individually supplied from the external inspection circuit (6) to each gate circuit (2b). Further, the output signal wiring (4c) is individually provided with a response signal (S) from each gate circuit (2b) to the external inspection circuit (6).
₄ ) The gate circuits (2b) are connected in parallel to the wiring (4c) so that the wiring can be taken out, and further, the gate circuits (2b) and the inspection IC chips (2a) are individually inspected.
A plurality of units of inspection IC chips (2a) are connected to each gate circuit (2b) so that a response signal (S ₃ ) can be exchanged and power can be supplied, and an arbitrary gate circuit (2b) is supplied from an external inspection circuit. The inspection signal and power from the input signal wiring (4b) given from the external inspection circuit (6) are selectively closed by the gate circuit opening / closing control signal from the control signal wiring (4a). Is a plurality of units of inspection IC chips (2a) corresponding to the gate circuit (2b)
The IC chip (1a) that is in contact with the inspection IC chip (2a) and flows into the IC to output an inspection / response signal, and the inspection / response signal is output to the closed gate. An inspection apparatus for a semiconductor wafer, which is introduced into an output signal wiring (4c) via a circuit (2b) and is taken into an external inspection circuit (6).