JPH08184612A - Inspection apparatus for semiconductor wafer - Google Patents

Inspection apparatus for semiconductor wafer

Info

Publication number
JPH08184612A
JPH08184612A JP33964794A JP33964794A JPH08184612A JP H08184612 A JPH08184612 A JP H08184612A JP 33964794 A JP33964794 A JP 33964794A JP 33964794 A JP33964794 A JP 33964794A JP H08184612 A JPH08184612 A JP H08184612A
Authority
JP
Japan
Prior art keywords
inspection
inspected
chip
semiconductor wafer
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33964794A
Other languages
Japanese (ja)
Other versions
JP2675763B2 (en
Inventor
Nobushi Suzuki
悦四 鈴木
Masashi Okuma
真史 大熊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaichi Electronics Co Ltd
Original Assignee
Yamaichi Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaichi Electronics Co Ltd filed Critical Yamaichi Electronics Co Ltd
Priority to JP6339647A priority Critical patent/JP2675763B2/en
Publication of JPH08184612A publication Critical patent/JPH08184612A/en
Application granted granted Critical
Publication of JP2675763B2 publication Critical patent/JP2675763B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the size and cost of an inspection apparatus by using an inspection card formed of a semiconductor wafer formed of an inspection IC chip and having the same effectiveness as an object to be inspected. CONSTITUTION: An inspection card is formed of a semiconductor wafer having the same material and effectiveness as those of an object to be inspected and formed with many inspecting IC chips 2a. The card also has a plurality of gate circuits 2b for selectively operating the IC chip to be inspected, wirings 4a for a gate circuit control signal, and wirings 4b, 4c for input and output signals. The wirings 4a to 4c are connected to an external inspection circuit 6, the circuit 2b is connected in parallel with wirings 4a to 4c, which extract a control signal S1 , an inspection signal S2 and a response signal S4 . Further, one or a plurality of the chips 2a are connected to the circuit 2b to replace an inspection response signal S3 . Thus, the chips 2a input inspection signal from the circuit 6 to the IC chip to be inspected, and outputs a response signal to the circuit 6. The inspection circuit elements can be easily formed on the card by IC forming technology, so that they can be simplified and reduced in cost.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は半導体ウェハ上の多数
の被検査ICチップを検査対象とした検査装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection device for inspecting a large number of IC chips to be inspected on a semiconductor wafer.

【0002】[0002]

【従来の技術】半導体ウェハ上に形成されたICチッ
プ、或いはその製造途上品を検査するには、一般にIC
チップ群を一素子ずつ検査電極でチェックするか、又は
各ICチップの外部電極群に接触子を接触させ、検査を
繰り返すことが行なわれている。この時半導体ウェハを
移動させながらウェハ上に形成された各ICチップを検
査している。
2. Description of the Related Art Generally, an IC is used to inspect an IC chip formed on a semiconductor wafer or a product under manufacturing thereof.
The chip group is checked element by element with an inspection electrode, or a contact is brought into contact with the external electrode group of each IC chip to repeat the inspection. At this time, while moving the semiconductor wafer, each IC chip formed on the wafer is inspected.

【0003】[0003]

【発明が解決しようとする問題点】従ってウェハ上の多
数のICチップを検査するには多大な時間を要し、検査
コストが高くつく。
Therefore, it takes a lot of time to inspect a large number of IC chips on a wafer, and the inspection cost is high.

【0004】更には検査に必要な電気信号や応答信号の
処理は全て外部に設けられた検査回路に依存しているた
め、最近のように微弱信号の検出や高周波の信号の出入
力が必要な検査では途中回路による減衰やノイズにより
検査不可能な場合が生じている。
Furthermore, since processing of electric signals and response signals necessary for inspection depends entirely on external inspection circuits, it has become necessary to detect weak signals and input / output high-frequency signals as in recent years. In the inspection, there are cases where the inspection cannot be performed due to the attenuation and noise due to the circuit on the way.

【0005】又最近、ICパッケージにおいて行なわれ
ているバーンイン検査をベアICチップにおいて行なう
要求が強くなって来ている。このベアICチップのバー
ンイン検査はICチップをパッケージ化せずに裸のまま
直接バーンインするのであるが、接触子群をICチップ
の電極パッド群に接触し、高温雰囲気中でその接触子群
を通して電気的入出力しなければならない。
Recently, there is an increasing demand for performing a burn-in test on an IC package on a bare IC chip. In this burn-in test of the bare IC chip, the IC chip is directly burned in as it is without packaging the IC chip. Input and output must be done.

【0006】ICチップの電極パッド群は微細ピッチで
数百の多数パッドであり、それに接触する接触子群も同
様に微細,多数である。従ってICチップの電極パッド
群と接触子群を位置を保ち接触させながら高温のバーン
インをするためには熱変形しない接触子や、接触子やI
Cチップを保持する材料が熱変形しないことが必要であ
る。即ち接触子を微少ピッチにするには限界があり、又
接触子を保持する材料がバーンインにおける高熱により
熱膨張や変形を生じて接触点の位置がずれ信頼性に欠け
る問題を有している。
The electrode pad group of the IC chip is a large number of hundreds of pads with a fine pitch, and the contact group that contacts it is also fine and numerous. Therefore, in order to burn-in at a high temperature while keeping the position of the electrode pad group and the contact group of the IC chip in contact with each other, the contact is not deformed by heat or the contact or
It is necessary that the material holding the C-chip does not undergo thermal deformation. That is, there is a limit to making the contact pitch fine, and there is a problem that the material holding the contact causes thermal expansion or deformation due to high heat in burn-in, and the position of the contact point is displaced, resulting in lack of reliability.

【0007】[0007]

【問題点を解決するための手段】この発明は上記問題点
を解決する手段として、多数の被検査ICチップを有し
ている半導体ウェハを検査対象としており、多数の検査
ICチップを有している半導体ウェハによって検査カー
ドが形成され、上記検査ICチップは検査すべき被検査
ICチップに選択的に外部検査回路からの検査信号を入
力し且つ各検査ICチップからの応答信号を外部検査回
路へ出力するゲート回路を形成している半導体ウェハの
検査装置を構成したものである。
As a means for solving the above problems, the present invention targets a semiconductor wafer having a large number of IC chips to be inspected, and has a large number of inspection IC chips. An inspection card is formed by an existing semiconductor wafer, and the inspection IC chip selectively inputs an inspection signal from an external inspection circuit to an inspected IC chip to be inspected and sends a response signal from each inspection IC chip to the external inspection circuit. This is a device for inspecting a semiconductor wafer forming a gate circuit for outputting.

【0008】[0008]

【作用】この発明は検査対象たる半導体ウェハを安定な
検査に必要な回路素子群(検査ICチップ)を形成した
同効の半導体ウェハから成る検査カードを用いることに
より上記問題点を有効に解決したものである。
The present invention effectively solves the above problems by using an inspection card made of a semiconductor wafer of the same effect in which a circuit element group (inspection IC chip) necessary for stable inspection of a semiconductor wafer to be inspected is formed. It is a thing.

【0009】半導体ウェハ上の被検査ICチップを選択
的に検査する検査回路要素はIC形成技術により容易に
検査カード上に作ることができ、コンパクト化とローコ
スト化を達成する。
The inspection circuit element for selectively inspecting the IC chip to be inspected on the semiconductor wafer can be easily formed on the inspection card by the IC forming technique, and the size and cost can be reduced.

【0010】ウェハ上のICチップの電極パッドにバン
プを形成するので、高精度にでき検査対象と同じ材質で
検査カードが作れるのでバーンイン等の熱による接触点
の位置ズレがない。
Since bumps are formed on the electrode pads of the IC chip on the wafer, it is possible to make the inspection card with high accuracy and to make an inspection card with the same material as the inspection object, so there is no displacement of the contact points due to heat such as burn-in.

【0011】上記検査装置は半導体ウェハ上に多数形成
されているICチップを極めて能率良く安定に検査で
き、検査コストの削減に寄与する。
The above-described inspection apparatus can inspect a large number of IC chips formed on a semiconductor wafer in an extremely efficient and stable manner, and contributes to reduction in inspection cost.

【0012】[0012]

【実施例】この発明は図1に示す如く多数の被検査IC
チップ1aを有する半導体ウェハ1を検査対象としてい
る。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention has a large number of ICs to be inspected as shown in FIG.
The semiconductor wafer 1 having the chip 1a is an inspection target.

【0013】図2はこの半導体ウェハ1上に形成された
被検査ICチップ1aを柔軟性を有するプラスチックシ
ート1c上に切離した状態で貼布している。このプラス
チックシート1cは熱可塑性フィルム又は表面に接着層
を持ったプラスチックフィルムである。検査対象となる
半導体ウェハ1とは図1又は図2の状態にあるものを意
味する。
In FIG. 2, an IC chip 1a to be inspected formed on the semiconductor wafer 1 is pasted on a flexible plastic sheet 1c in a separated state. The plastic sheet 1c is a thermoplastic film or a plastic film having an adhesive layer on the surface. The semiconductor wafer 1 to be inspected means one in the state shown in FIG. 1 or FIG.

【0014】他方検査カード2は多数の検査ICチップ
2aを形成した半導体ウェハによって形成される。
On the other hand, the inspection card 2 is formed by a semiconductor wafer on which a large number of inspection IC chips 2a are formed.

【0015】従って上記カード2は既知の半導体ウェハ
形成技術に基いて製造されるものであり、検査対象たる
半導体ウェハ1と同材質、同効のものである。
Therefore, the card 2 is manufactured based on the known semiconductor wafer forming technique, and has the same material and the same effect as the semiconductor wafer 1 to be inspected.

【0016】図3においては検査ICチップ2aとゲー
ト回路3とを理解を助けるために区分して表現している
が、上記検査カード2、即ち半導体ウェハ上に形成され
た複数の各検査ICチップ2aは検査すべき被検査IC
チップ1aを選択的に動作させる複数のゲート回路2b
(スイッチング回路群)と上記被検査ICチップ1aの
電極パッド1b群に接触するバンプ5群から構成されて
いる。
In FIG. 3, the inspection IC chip 2a and the gate circuit 3 are shown separately to facilitate understanding, but the inspection card 2, that is, a plurality of inspection IC chips formed on the semiconductor wafer. 2a is an IC to be inspected to be inspected
A plurality of gate circuits 2b for selectively operating the chip 1a
(Switching circuit group) and bumps 5 group contacting the electrode pad 1b group of the IC chip 1a to be inspected.

【0017】更に上記検査カード2は図3に示すように
各ゲート回路2bの開閉を制御するゲート回路制御信号
用配線4aと、各ゲート回路2bを経由して各検査IC
チップ2aに検査用信号や電源を供給する入力信号用配
線4bと、各ゲート回路3を経由して各被検査ICチッ
プ1a及び検査ICチップ2aから応答信号を取出す出
力信号用配線4cとを有し、各配線4a,4b,4cは
外部検査回路6に接続されている。
Further, as shown in FIG. 3, the inspection card 2 further includes gate circuit control signal wiring 4a for controlling the opening / closing of each gate circuit 2b, and each inspection IC via each gate circuit 2b.
An input signal wiring 4b for supplying an inspection signal and power to the chip 2a and an output signal wiring 4c for extracting a response signal from each IC chip 1a to be inspected and the inspection IC chip 2a via each gate circuit 3 are provided. However, the wirings 4 a, 4 b, 4 c are connected to the external inspection circuit 6.

【0018】上記ゲート回路制御信号用配線4aには各
ゲート回路2bと個別に制御信号S1を供給できるよ
う、配線4aに対し各ゲート回路2bを並列的に接続
し、又上記入力信号用配線4bには各ゲート回路2bへ
個別に検査用信号S2を供給できるよう配線4bに対し
各ゲート回路2bを並列的に接続し、又上記出力信号用
配線4cには各ゲート回路2bから個別に応答信号S4
が取出しできるよう、配線4cに対し各ゲート回路2b
を並列的に接続する。
The gate circuit control signal wiring 4a is connected in parallel with each gate circuit 2b so that the control signal S 1 can be supplied individually to each gate circuit 2b, and the input signal wiring is also provided. Each gate circuit 2b is connected in parallel to the wiring 4b so that the inspection signal S 2 can be individually supplied to each gate circuit 2b, and the output signal wiring 4c is individually connected to each gate circuit 2b. Response signal S 4
So that each gate circuit 2b can be taken out from the wiring 4c.
Are connected in parallel.

【0019】更に上記各ゲート回路2bと各検査ICチ
ップ2aとは個別に検査・応答信号S3の交換が行なえ
るよう、ある単位ゲート回路2bに対し一又は複数単位
の検査ICチップ2aが接続され、又他の単位ゲート回
路2bに対し他の一又は複数単位の検査ICチップ2a
が接続される。
Further, one or a plurality of units of inspection IC chips 2a are connected to a certain unit gate circuit 2b so that each of the gate circuits 2b and each of the inspection IC chips 2a can exchange the inspection / response signal S 3 individually. In addition, the inspection IC chip 2a of another unit or a plurality of units is provided for the other unit gate circuit 2b.
Is connected.

【0020】上記各配線4a,4b,4cとゲート回路
2b及び検査ICチップ2aとの上記各接続は全て半導
体ウェハ上にICチップを形成する既知のウェハ製造技
術によって形成される。
All the above-mentioned connections between the respective wirings 4a, 4b, 4c and the gate circuit 2b and the inspection IC chip 2a are formed by a known wafer manufacturing technique for forming IC chips on a semiconductor wafer.

【0021】他方上記検査カード2を形成する半導体ウ
ェハ上の検査ICチップ2aの表面には被検査ICチッ
プ1aの電極パッド1b群に接触するバンプ5群が形成
され、上記ゲート回路2bはこのバンプ5に接続してい
る。
On the other hand, bumps 5 which come into contact with the electrode pads 1b of the IC chip 1a to be inspected are formed on the surface of the inspection IC chip 2a on the semiconductor wafer forming the inspection card 2, and the gate circuit 2b has the bumps 5b. Connected to 5.

【0022】又この検査ICチップ2aは上記バンプ5
と被検査ICチップ1aの電極パッド1bの接触を介し
て信号の交換を行なう。
The inspection IC chip 2a has the bumps 5
Signals are exchanged via the contact between the electrode pad 1b of the IC chip 1a to be inspected.

【0023】上記バンプ5群は例えば、図6に示すよう
に微少なプラスチックボール5aによって形成される。
このプラスチックボール5aは表面に金属メッキコート
5′を施した弾性体であり、プラスチックであるが故に
極小径の製造が可能であり、且つ加圧接触に必要な適正
な弾性を確保できる。
The bump 5 group is formed of, for example, minute plastic balls 5a as shown in FIG.
This plastic ball 5a is an elastic body having a metal plating coat 5'on its surface. Since it is a plastic, it can be manufactured to have a very small diameter, and the proper elasticity required for pressure contact can be secured.

【0024】又他例として上記バンプ5は、図7に示す
ようにメタルリング5bによって形成され、メタルリン
グ5bの円周面を加圧接触点とする。
As another example, the bump 5 is formed by a metal ring 5b as shown in FIG. 7, and the circumferential surface of the metal ring 5b is used as a pressure contact point.

【0025】更に他例として上記バンプ5は図8に示す
ように、ワイヤボンディング5cによって形成される。
As still another example, the bump 5 is formed by wire bonding 5c as shown in FIG.

【0026】上記プラスチックボール5a及びメタルリ
ング5bは何れもその円周面の一点を検査ICチップ2
aの表面の電極パッド2cに接着され、その反対側の一
点を電極パッド1bとの加圧接触点とするものである。
Each of the plastic ball 5a and the metal ring 5b has an inspection IC chip 2 at one point on its circumferential surface.
It is adhered to the electrode pad 2c on the surface of a, and one point on the opposite side is used as a pressure contact point with the electrode pad 1b.

【0027】又ワイヤボンディング5cは細いワイヤの
先端を電極パッドの表面において溶融させつつ引離すこ
とによって形成され、その尖った先端を電極パッド1b
との加圧接触点とする。
The wire bonding 5c is formed by melting and separating the tip of a thin wire on the surface of the electrode pad, and the sharp tip is formed on the electrode pad 1b.
It is the point of pressure contact with.

【0028】図4に示すように、上記検査対象たる半導
体ウェハ1は検査ステージ7の上面に形成された収容室
8の内底面に収置される。ステージ7はヒータ11によ
り必要に応じ加熱される。
As shown in FIG. 4, the semiconductor wafer 1 to be inspected is placed on the inner bottom surface of the accommodation chamber 8 formed on the upper surface of the inspection stage 7. The stage 7 is heated by the heater 11 as needed.

【0029】他方半導体ウェハから成る検査カード2は
そのバンプ5群を被検査ICチップ1aの電極パッド1
bに接触する如く位置合せされて半導体ウェハ1上に重
ねる。
On the other hand, the inspection card 2 made of a semiconductor wafer has bumps 5 of which the electrode pads 1 of the IC chip 1a to be inspected.
The semiconductor wafer 1 is superposed on the semiconductor wafer 1 while being aligned so as to contact with b.

【0030】上記検査カード2は半導体ウェハ1が収置
された収容室8を覆い、該収容室8内の気体をステージ
7に設けた吸引口9を通じバキュームすると、検査カー
ド2は半導体ウェハ1の表面に押し付けられ、バンプ5
群と電極パッド1bとの加圧接触が得られる。
The inspection card 2 covers the accommodation chamber 8 in which the semiconductor wafer 1 is accommodated, and when the gas in the accommodation chamber 8 is vacuumed through the suction port 9 provided on the stage 7, the inspection card 2 is inspected for the semiconductor wafer 1. Bump 5 pressed against the surface
A pressure contact between the group and the electrode pad 1b is obtained.

【0031】上記ステージ7には収容室8の周囲、即ち
半導体ウェハ1の周囲において上記検査カード2を支え
る弾性シーリング10が設けられ、上記バキュームによ
り検査カード2を上記弾性シーリング10に押し付け気
密を保ち、上記バンプ5群と電極パッド1bの加圧接触
状態を保護する。
The stage 7 is provided with an elastic sealing 10 for supporting the inspection card 2 around the accommodation chamber 8, that is, around the semiconductor wafer 1. The inspection card 2 is pressed against the elastic sealing 10 by the vacuum to keep airtightness. The state of pressure contact between the bump group 5 and the electrode pad 1b is protected.

【0032】図5は上記半導体ウェハ1と検査カード2
の接触部位を拡大示したものであり、両者のバンプ5群
と電極パッド1bの接触を通じて信号の交換が行なわれ
る。
FIG. 5 shows the semiconductor wafer 1 and the inspection card 2 described above.
3 is an enlarged view of the contact portion of the above, and signals are exchanged through contact between the two bump groups 5 and the electrode pad 1b.

【0033】而して、図4,図3の状態においてゲート
回路2b群の一つが制御信号用配線4aからの制御信号
にて選択的に開かれ(ゲートオン状態)、これにより入
力信号用配線4bの信号がこのゲート回路2bに対応し
た検査ICチップ2aに流入し、この検査ICチップ2
aに対応して接触された被検査ICチップ1aを付勢し
て検査・応答信号を出力する。この検査・応答信号はゲ
ートオンされた上記ゲート回路2bを経由して出力信号
用配線4cに導入され外部検査回路6に取り込まれる。
Thus, in the state shown in FIGS. 4 and 3, one of the groups of gate circuits 2b is selectively opened by the control signal from the control signal wiring 4a (gate-on state), whereby the input signal wiring 4b. Signal flows into the inspection IC chip 2a corresponding to the gate circuit 2b, and the inspection IC chip 2a
The IC chip 1a to be inspected, which is brought into contact with a, is energized and an inspection / response signal is output. This inspection / response signal is introduced into the output signal wiring 4c via the gate circuit 2b whose gate is turned on, and taken into the external inspection circuit 6.

【0034】上記検査を実行している間、他の全てのゲ
ート回路2bは閉じた状態(ゲートオフ状態)に置か
れ、次の指令に備える。
While the above inspection is being performed, all the other gate circuits 2b are placed in the closed state (gate off state) to prepare for the next command.

【0035】即ち制御信号用配線4aを通して外部から
被検査ICチップ1aを選択しながら被検査半導体ウェ
ハの複数の被検査ICチップ1aを次々に電気的検査を
行う。従って全く機械的動作もなく半導体ウェハ上の多
数の被検査ICチップ1aを高速に検査することができ
る。
That is, while a plurality of IC chips 1a to be inspected are selected from the outside through the control signal wiring 4a, a plurality of IC chips 1a to be inspected of the semiconductor wafer to be inspected are successively electrically inspected. Therefore, many IC chips 1a to be inspected on the semiconductor wafer can be inspected at high speed without any mechanical operation.

【0036】一方バーインテストでは全ての被検査IC
チップ1aを作動状態にしておく必要性からゲート回路
2bは通常状態で被検査ICチップの動作に必要な入力
信号用配線4aの信号をバンプ5群に接続しているもの
とする。
On the other hand, in the burn-in test, all ICs to be inspected
Since it is necessary to keep the chip 1a in the operating state, it is assumed that the gate circuit 2b connects the signal of the input signal wiring 4a necessary for the operation of the IC chip to be inspected to the bump 5 group in the normal state.

【0037】実施例として上記検査カード2即ち検査半
導体ウェハ上には、外部検査回路8の一部である微弱信
号の増幅回路や、被検査ICチップの良否を判別する検
査判定回路用のICチップを形成することができる。こ
の実施例は外部検査回路6に接続する線路長が長くノイ
ズ的に問題となる場合、このノイズ対策として有効であ
る。
As an example, on the inspection card 2 or the inspection semiconductor wafer, an amplifier circuit for a weak signal which is a part of the external inspection circuit 8 or an IC chip for an inspection judgment circuit for judging the quality of the IC chip to be inspected Can be formed. This embodiment is effective as a countermeasure against this noise when the line length connected to the external inspection circuit 6 is long and causes a noise problem.

【0038】又この発明はバンプ5を設けずに被検査I
Cチップ1aの電極パッド1bと検査ICチップ2aの
電極パッド2bとを直接接触して上記検査が行う場合を
含む。
Further, according to the present invention, the inspection target I
The case where the above-mentioned inspection is performed by directly contacting the electrode pad 1b of the C chip 1a and the electrode pad 2b of the inspection IC chip 2a is included.

【0039】又この発明はバンプ5を設けずに導電エラ
ストマーを両者1a,2a間に介在して上記検査を行う
ことができる。
Further, according to the present invention, the above-mentioned inspection can be performed without providing the bump 5 with the conductive elastomer interposed between the both 1a and 2a.

【0040】[0040]

【発明の効果】上記半導体ウェハから成る検査カードは
その検査回路要素、配線、接続が従来の半導体ウェハ形
成技術により容易に作ることができ、検査装置の小形化
とコストダウンを達成できる。
The inspection card composed of the semiconductor wafer described above can be easily formed by the conventional semiconductor wafer forming technique for its inspection circuit elements, wiring, and connection, and the inspection device can be downsized and the cost can be reduced.

【0041】又検査対象となる半導体ウェハと同材質で
製造できるので、バーンイン検査時の熱による熱膨張か
ら起こる接触部の位置ずれを有効に防止でき、検査の信
頼性を飛躍的に向上することができる。
Further, since the semiconductor wafer to be inspected can be manufactured with the same material as that of the semiconductor wafer to be inspected, it is possible to effectively prevent the displacement of the contact portion due to the thermal expansion due to the heat at the time of burn-in inspection, and to greatly improve the reliability of inspection. You can

【0042】又、ウェハ製造技術により形成された被検
査ICチップの電極パッド上にバンプを付設することに
より、精度向上と微少ピッチ化への対応が図れる。即ち
従来のプローバ(接触子)を基板に微少ピッチで配列す
る場合の製造上の位置精度とコスト問題を克服できる。
Further, by providing bumps on the electrode pads of the IC chip to be inspected formed by the wafer manufacturing technique, it is possible to improve the accuracy and cope with a fine pitch. That is, it is possible to overcome the manufacturing positional accuracy and cost problems when the conventional probers (contactors) are arranged on the substrate at a fine pitch.

【0043】本発明によれば半導体ウェハ上に形成され
ている多数のICチップを機械的動作を伴わずに能率良
くローコストで検査でき、パッケージ化前のベアチップ
状態での検査の要請やベアチップ供給に伴う検査問題に
適切に応え得るものである。
According to the present invention, a large number of IC chips formed on a semiconductor wafer can be inspected efficiently and at low cost without any mechanical operation, and it is possible to provide an inspection request in a bare chip state before packaging or supply a bare chip. It can properly respond to the inspection problems involved.

【図面の簡単な説明】[Brief description of drawings]

【図1】検査カード又は検査対象たる半導体ウェハの平
面図。
FIG. 1 is a plan view of an inspection card or a semiconductor wafer to be inspected.

【図2】同側面図。FIG. 2 is a side view of the same.

【図3】半導体ウェハから成る検査カード上に形成され
た回路要素と配線と信号の流れを説明する平面図。
FIG. 3 is a plan view illustrating circuit elements, wirings, and signal flows formed on an inspection card made of a semiconductor wafer.

【図4】上記検査カードを使用して検査対象たる半導体
ウェハを検査している検査装置断面図。
FIG. 4 is a cross-sectional view of an inspection device inspecting a semiconductor wafer to be inspected using the inspection card.

【図5】検査カードと検査対象たる半導体ウェハの接触
状態を示す拡大側面図。
FIG. 5 is an enlarged side view showing a contact state between an inspection card and a semiconductor wafer to be inspected.

【図6】検査カード上の検査ICチップ表面に付設され
るバンプの一例を示す拡大図。
FIG. 6 is an enlarged view showing an example of bumps attached to the surface of the inspection IC chip on the inspection card.

【図7】上記バンプの他例を示す拡大図。FIG. 7 is an enlarged view showing another example of the bump.

【図8】上記バンプの更に他例を示す拡大図。FIG. 8 is an enlarged view showing still another example of the bump.

【符号の説明】[Explanation of symbols]

1 検査対象たる半導体ウェハ 1a 上記半導体ウェハ上の被検査ICチップ 1b 上記被検査ICチップの電極パッド 2 半導体ウェハから成る検査カード 2a 上記検査カード上の検査ICチップ 2b 検査カード上のゲート回路 4a 検査カード上の制御信号用配線 4b 同入力信号用配線 4c 同出力信号用配線 5 検査ICチップに付設したバンプ 1 semiconductor wafer to be inspected 1a IC chip to be inspected on the semiconductor wafer 1b Electrode pad of the IC chip to be inspected 2 Inspection card 2a consisting of a semiconductor wafer Inspection IC chip on the above inspection card 2b Gate circuit on the inspection card 4a Inspection Wiring for control signal on card 4b Wiring for same input signal 4c Wiring for same output signal 5 Bump attached to inspection IC chip

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/66 F ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 21/66 F

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】多数の被検査ICチップを有している半導
体ウェハを検査対象としており、多数の検査ICチップ
を有している半導体ウェハによって検査カードが形成さ
れ、上記検査ICチップは検査すべき被検査ICチップ
に選択的に外部検査回路からの検査信号を入力し且つ各
検査ICチップからの応答信号を外部検査回路へ出力す
るゲート回路を形成していることを特徴とする半導体ウ
ェハの検査装置。
1. A semiconductor wafer having a large number of IC chips to be inspected is inspected, and an inspection card is formed by the semiconductor wafer having a large number of inspection IC chips, and the inspection IC chips are inspected. A semiconductor wafer having a gate circuit for selectively inputting an inspection signal from an external inspection circuit to an IC chip to be inspected and outputting a response signal from each inspection IC chip to the external inspection circuit. Inspection device.
【請求項2】上記各検査ICチップには被検査ICチッ
プの電極パッドに接触するバンプを形成したことを特徴
とする請求項1記載の半導体ウェハの検査装置。
2. The semiconductor wafer inspection apparatus according to claim 1, wherein bumps are formed on each of the inspection IC chips so as to come into contact with the electrode pads of the IC chip to be inspected.
JP6339647A 1994-12-28 1994-12-28 Semiconductor wafer inspection system Expired - Fee Related JP2675763B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6339647A JP2675763B2 (en) 1994-12-28 1994-12-28 Semiconductor wafer inspection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6339647A JP2675763B2 (en) 1994-12-28 1994-12-28 Semiconductor wafer inspection system

Publications (2)

Publication Number Publication Date
JPH08184612A true JPH08184612A (en) 1996-07-16
JP2675763B2 JP2675763B2 (en) 1997-11-12

Family

ID=18329485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6339647A Expired - Fee Related JP2675763B2 (en) 1994-12-28 1994-12-28 Semiconductor wafer inspection system

Country Status (1)

Country Link
JP (1) JP2675763B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08220140A (en) * 1995-02-14 1996-08-30 Nippon Denshi Zairyo Kk Probe card and manufacture thereof
US6525555B1 (en) 1993-11-16 2003-02-25 Formfactor, Inc. Wafer-level burn-in and test
WO2009147724A1 (en) * 2008-06-02 2009-12-10 株式会社アドバンテスト Test wafer unit and test system
US7944225B2 (en) * 2008-09-26 2011-05-17 Formfactor, Inc. Method and apparatus for providing a tester integrated circuit for testing a semiconductor device under test
US8095841B2 (en) 2008-08-19 2012-01-10 Formfactor, Inc. Method and apparatus for testing semiconductor devices with autonomous expected value generation
US8122309B2 (en) 2008-03-11 2012-02-21 Formfactor, Inc. Method and apparatus for processing failures during semiconductor device testing
US8872534B2 (en) 2007-09-27 2014-10-28 Formfactor, Inc. Method and apparatus for testing devices using serially controlled intelligent switches

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JPS6412542A (en) * 1987-07-07 1989-01-17 Matsushita Electronics Corp Parallel tester
JPH03171749A (en) * 1989-11-30 1991-07-25 Toshiba Corp Probe card and semiconductor testing device
JPH05275504A (en) * 1992-01-16 1993-10-22 Toshiba Corp Probe card
JPH0661315A (en) * 1992-08-05 1994-03-04 Sharp Corp Structure for inspecting integrated circuit device
JPH07115113A (en) * 1993-08-25 1995-05-02 Nec Corp Semiconductor wafer testing device and testing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6412542A (en) * 1987-07-07 1989-01-17 Matsushita Electronics Corp Parallel tester
JPH03171749A (en) * 1989-11-30 1991-07-25 Toshiba Corp Probe card and semiconductor testing device
JPH05275504A (en) * 1992-01-16 1993-10-22 Toshiba Corp Probe card
JPH0661315A (en) * 1992-08-05 1994-03-04 Sharp Corp Structure for inspecting integrated circuit device
JPH07115113A (en) * 1993-08-25 1995-05-02 Nec Corp Semiconductor wafer testing device and testing method

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525555B1 (en) 1993-11-16 2003-02-25 Formfactor, Inc. Wafer-level burn-in and test
US6788094B2 (en) 1993-11-16 2004-09-07 Formfactor, Inc. Wafer-level burn-in and test
US7078926B2 (en) 1993-11-16 2006-07-18 Formfactor, Inc. Wafer-level burn-in and test
US7345493B2 (en) 1993-11-16 2008-03-18 Formfactor, Inc. Wafer-level burn-in and test
JPH08220140A (en) * 1995-02-14 1996-08-30 Nippon Denshi Zairyo Kk Probe card and manufacture thereof
US8872534B2 (en) 2007-09-27 2014-10-28 Formfactor, Inc. Method and apparatus for testing devices using serially controlled intelligent switches
US8122309B2 (en) 2008-03-11 2012-02-21 Formfactor, Inc. Method and apparatus for processing failures during semiconductor device testing
WO2009147724A1 (en) * 2008-06-02 2009-12-10 株式会社アドバンテスト Test wafer unit and test system
US8378700B2 (en) 2008-06-02 2013-02-19 Advantest Corporation Wafer unit for testing semiconductor chips and test system
US8095841B2 (en) 2008-08-19 2012-01-10 Formfactor, Inc. Method and apparatus for testing semiconductor devices with autonomous expected value generation
US7944225B2 (en) * 2008-09-26 2011-05-17 Formfactor, Inc. Method and apparatus for providing a tester integrated circuit for testing a semiconductor device under test

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