JPS6113813A - Special integration type timer circuit - Google Patents

Abstract

PURPOSE:To execute surely control for demmand/supply balance by providing the 1st timer circuit, a waveform shaping circuit outputting an output signal when an input value exceeds a prescribed value and the 2nd timer circuit to output a control signal when the measured time exceeds a setting value within a prescribed time of the input value. CONSTITUTION:The 1st timer circuit 1 generates a prescribed time T1. As the time T1, a time slightly longer than the time when the vibration of the system against the disturbance of a power system is converged is set. A level discriminating circuit 11 uses, e.g., a frequency as the input signal to discriminate whether frequency value is larger or smaller, and when the value is larger, a set signal is outputted to a set/reset circuit 13. Further, the setting circuit 12 sets the limit value of the state variable to be detected. The 2nd timer circuit 2 measures the time T when the state variable exceeds the limit value during the time interval T1. A discriminating circuit 26 compares the measured value T of a counter circuit 24 with the setting value T2 of the setting circuit 27, and when the condition of T>=T2 is established, a control signal is outputted.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a special integration type timer circuit that measures time when a certain condition is satisfied. There were those shown in Figures 1 and 2. In other words, when a certain predetermined condition is met, a timer circuit is set, and if the condition continues to be met beyond the set time of the timer, a certain control signal is output, and if the predetermined condition is not met within the set time, the timer circuit is set. In this case, a circuit method for resetting the timer circuit or a certain predetermined condition as shown in Figure 2 is established (Δ
Ti〉0) and the timer circuit is set (rotated in the positive direction), but if the condition does not hold (∆Ti〈0), the timer is not reset and the timer is reversed so that the sum of both exceeds the set value. It was a circuit that outputs a control signal when the

Since the conventional timer circuit has the circuit configuration as described above, for example, as shown in FIG. If an accident occurs in which a load PLn falls off in a power system consisting of an aircraft group PGn, a power transmission system N, and a load group PLn, the output control of the generator group PGn cannot be quickly executed, and the supply and demand of electric power will be affected. If the balance is out of whack and the amount of power generated is large, the frequency will continue to rise. However, after that, this frequency is detected by the power limiting protective relay, etc., and the generator group P
Since Gn controls the output so as to reduce the output, the frequency temporarily decreases, and finally converges to a certain value vibrationally as shown in FIG. In such cases, a control means takes into account the stress on equipment such as generators, and balances supply and demand by cutting off some generators for a certain period of time, for example, when the frequency of the grid exceeds a predetermined tolerance. However, if the system is oscillatory, the conventional timer circuit shown in FIGS. 1 and 2 repeats setting and resetting and becomes inoperable.

However, if the timer period is shortened to prevent this, there is a drawback that the timer may operate even when it is not required.

[Summary of the invention]

The present invention was made in order to eliminate the drawbacks of the conventional timer as described above, and includes a first timer circuit for passing a certain predetermined time, and a control signal from the first timer circuit. Based on the input, a second timer circuit includes a waveform shaping circuit that outputs an output signal only when the input value exceeds a predetermined value, and a counting circuit that measures the time during which the output signal from this waveform shaping circuit is significant. The purpose of the present invention is to provide a special integral type timer circuit which measures the time when a value exceeds a predetermined value within a predetermined time and outputs a control signal when the measured time exceeds a set value.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Fifth
In the figure, reference numeral 11 denotes a level determination circuit, and the input signal is compared with the output of the setting circuit 12. Reference numeral 13 denotes a set/reset circuit for the timer circuit 14, and the first timer circuit 1 is constituted by the above circuits. In addition, 21 is a gate circuit, 2
2 is a waveform shaping circuit that compares the output signal of the gate circuit 21 and the output signal of the setting circuit 23; 24 is a counting circuit; 25 is a reference clock circuit; and 26 is a waveform shaping circuit that compares the output signal of the counting circuit and the output signal of the setting circuit 27. A discrimination circuit that performs comparison and discrimination constitutes the second timer circuit 2, which includes the various circuits described above.

Next, the operation shown in FIG. 5 will be explained below. First, the first
The timer circuit 1 forms a predetermined time T1. This time T1 is set to be a slightly longer time than the time required for system vibration to converge in response to a disturbance in a certain power system. The level determination circuit 11 receives system state variables such as frequency and wave number as input signals, and determines whether the frequency value is smaller than the set value, and if it is larger, the set/reset circuit 1
A set signal is output to 8. In addition, the setting circuit 12
sets the limit value of the state variable to be detected. When the set/reset circuit 13 is partially set, it continues to output a set signal until the next reset signal is received. The timer circuit 14 is activated by a set signal from the set/reset circuit 13 and outputs a reset signal after a time T1. This reset signal is fed back into the set bone reset circuit 13 to again reset the set/reset circuit 18, and also resets the timer circuit 14 by its output signal. In this way, the first timer circuit 1 forms a predetermined time interval T1.

Next, the second timer circuit 2 constitutes a circuit for measuring the time Tfc during which the state variable exceeds the limit value during the time interval T1. That is, the gate circuit 21 opens the gate only when the output from the set/reset circuit 13 is in the set state, and transmits the state variable of the system to the waveform shaping circuit 22. The waveform shaping circuit 22 compares the input value from the gate circuit 21 with the setting value in the setting circuit 23 (that is, the limit value of the state variable, which may be the same value as the setting circuit 12 or a different value), and determines whether the input value is greater than the setting value. Only when the value is larger, an ON output is sent to the counting circuit 24. The counting circuit 24 is turned ON.
Measure the time the output is being output.

The counting circuit 24 measures the output time of the ON signal from the waveform shaping circuit 22 until it is reset by a reset signal from the timer circuit 14.

The output time of this ON signal is T. The determination circuit 26 compares the measured value T of the counting circuit 24 and the set value T2 of the setting circuit 27, and outputs a control signal when the condition of T≧T2 is satisfied. Here, T2 is a time period during which it is permissible for the state variable to continue to exceed the limit value.

〔Effect of the invention〕

As described above, according to the present invention, the state variable of a power system actually exceeds the limit value during the time T1 during which the first timer circuit and the second timer circuit cause the state variable of a power system to exceed the limit value. Measure time T and exceed this time T
The circuit is configured so that it outputs an output signal only when T2 is greater than the set value of time T2, so even if the system is oscillatory, it can be controlled to balance supply and demand by taking into account the stress limits that can be tolerated by generators and other equipment. Since it can be executed reliably, it has the effect of being able to perform a highly reliable protective operation even when a load is dropped in the power system.

[Brief explanation of the drawing]

FIGS. 1 and 2 are block diagrams of a timer circuit based on the operating principle of a conventional timer. 1.2... 1st. 2nd timer circuit, 11... Level discrimination circuit, +2.23.27... Setting circuit, 13.
...set/reset circuit, 14...timer circuit,
21... Gate circuit, 22... Waveform shaping circuit, 24
...-counting circuit, 26...discrimination circuit. Patent applicant Mitsubishi Electric Corporation Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Procedural amendment (voluntary)

Claims (1)

[Claims] A first timer circuit that forms a predetermined time when an input value exceeds a reference value regardless of the magnitude of the signal; a waveform shaping circuit that generates an output signal only while the timer exceeds the reference clock; and a waveform shaping circuit that calculates an output signal from the reference clock circuit only when the output signal from the waveform shaping circuit is significant; A special integration type timer circuit comprising a counting circuit that clears a counted value and a discrimination circuit that sends out an output signal when the output signal from the counting circuit exceeds a set value for a predetermined time.