JPS62113246A - Operation monitoring device for signal processor - Google Patents

Abstract

PURPOSE:To easily monitor the real operation of a signal processor by counting a system clock generated in the execution time of an instruction which should be executed between a start instruction for monitoring and a stop instruction and deciding the operation of the signal processor. CONSTITUTION:The 2nd comparing circuit 8 compares the output of a counting circuit 6 with the maximum (minimum) value time expected to be generated in the maximum (minimum) time required to execute the instruction interposed between a couple of preset monitoring instructions inputted from the 4th input terminal 9 (5th input terminal 10). A couple of comparison results are outputted to a monitor signal generating circuit 11. The monitor signal generating circuit 11 inputs the output of the 2nd comparing circuit 8 and a monitor signal outputted by a monitor signal generating circuit 11 is '1' when the counted value of the counting circuit 6 is between the maximum and minimum values or '0' when not.

Description

[Detailed description of the invention] (Industrial use 1?) The present invention relates to a signal processor operation monitoring device.

(Prior art) Conventionally, in this type of signal processor operation monitoring device,
This is accomplished by comparing the output signal pattern output by a plurality of instructions other than the original signal processing in the operating signal processor with the output signal pattern expected during normal operation using an external circuit. For this reason, the load on the external circuit becomes large, making it troublesome.

(Problems to be Solved by the Invention) In the conventional signal processor operation monitoring device described above,
Since an output signal pattern different from the original one and a normal output signal pattern are compared in an external circuit, there is a drawback that the load on the external circuit is large.

An object of the present invention is to arbitrarily set a monitoring start instruction and a stop instruction, and to count system clocks generated during the execution time of an instruction to be executed between two distant instructions, thereby controlling the operation of a signal processor. It is an object of the present invention to provide a signal processor operation monitoring device configured to eliminate the above-mentioned drawbacks and to easily monitor the true operation of a signal processor.

(Means for Solving the Problems) A signal processor operation monitoring device according to the present invention includes a program counter, a first comparison circuit, a control circuit, a counting circuit, a second comparison circuit, and a monitoring signal generator. This circuit is configured to be able to count and output the number of system clocks generated between execution of a start instruction and execution of a stop instruction.

The program counter is used to indicate the memory address where the next instruction to be executed is stored when the signal processor is operating according to a group of instructions.

The first comparison circuit compares the output of the program counter with a first range defined by a start instruction and a stop instruction included in the instruction group, and determines whether the output of the program counter is included in the first range. This is to output a match signal when a match occurs.

The control circuit receives the output of the first comparison circuit and generates a control signal.

The counting circuit is for counting system clocks according to a control signal output from the control circuit.

The second comparison circuit compares the output of the counting circuit with a second range defined by the maximum execution time and minimum execution time of the instruction group, and determines whether the output of the counting circuit is included in the second range. This is to output a match signal when the

The monitoring signal generation circuit is for monitoring the operation of the signal processor by outputting a coincidence signal from the second comparison circuit.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a signal processor operation monitoring device according to the present invention.

In FIG. 1 showing an embodiment of the present invention, the signal processor operation monitoring device includes a program counter l, a first comparison circuit 2, a control circuit 5, a counting circuit 6, and a second comparison circuit 8. , and a supervisory signal generation circuit 11.

The program counter l indicates the address where the next instruction to be executed is stored.

The first comparison circuit 2 first compares the output of the program counter 1 with the smaller address of a pair of pre-selected monitoring instructions inputted through the first input terminal 3. compare.

Further, the first comparison circuit 2 compares the address with the larger address of a pair of preselected monitoring instructions inputted from the second input terminal 4. The pair of comparison results are output to the control circuit 6.

When the output of the first comparison circuit 2 is larger than the smaller address inputted from the first input terminal 3 and smaller than the larger address inputted from the second input terminal 4, the control circuit The control signal output from 5 becomes %11, and becomes 10l at other times. The output of the control circuit 5 is output to the counting circuit 6, which inputs the control signal output from the control circuit 5, and when the control signal is %11, inputs the system clock input from the eighth input terminal 7. It counts and holds its contents when it is %ON.

The second comparison circuit 8 firstly receives the output of the counting circuit 6 and the fourth
is compared with the maximum time expected to occur in the maximum time required to execute the instruction inserted between the pair of monitoring instructions input from the input terminal 9 of the above-mentioned set. Furthermore, the second comparison circuit 8 receives the output of the counting circuit 6 and the fifth input terminal 10.
The instruction inserted between the pair of monitoring instructions inputted by
Compare the minimum amount of time expected to occur with the minimum amount of time it takes to execute. The pair of comparison results are output to the supervisory signal generation circuit 11.

Supervisory signal generation circuit 11id A monitor output from the supervisory signal generation circuit 11 when the output of the second comparison circuit 8 is input and the count value of the counting circuit 6 is between the maximum value and the minimum value. When the signal is not 11I and the count value is not between the maximum value and the minimum value, the monitoring signal becomes %QJ.

According to the above, if the signal processor is operating normally, the supervisory signal is not 111, and if it is not operating normally, the supervisory signal power is βOl.

It is assumed that the count value of the counting circuit 6 is reset after one count ends and before the next count begins, for example, upon execution of the first instruction.

(Effects of the Invention) As described above, the present invention provides a system in which a monitoring smate instruction and a stop instruction are arbitrarily set, and the monitoring smate instruction and the stop instruction are set arbitrarily, and the monitoring instruction is generated during the execution time of an instruction to be executed between a pair of instructions that are separated from each other. By counting the clocks and determining the operation of the signal processor, there is an effect that the true operation of the signal processor can be easily monitored.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal processor operation monitoring device according to the present invention. l...Program kakunta 2.8/-6 comparison circuit 5...control circuit 6...counting circuit 11...monitoring signal generation circuit

Claims (1)

[Claims] A program counter that indicates the memory address where the next instruction to be executed is stored when the signal processor is operating according to the instruction group, and a start instruction and a stop instruction included in the instruction group. a first comparison circuit for comparing a first range and an output of the program counter and outputting a match signal when the output of the program counter is included in the first range; a control circuit for inputting an output of a circuit to generate a control signal; a counting circuit for counting a system clock according to the control signal output from the control circuit; an output of the counting circuit and the instruction; a second range for comparing a second range defined by a maximum execution time and a minimum execution time of the group and outputting a coincidence signal when the output of the counting circuit is included in the second range; A signal processor operation monitoring device comprising: a comparison circuit; and a monitoring signal generation circuit for monitoring the operation of the signal processor by outputting a coincidence signal from the second comparison circuit.