JPS6113678A - Manufacture of josephson junction element - Google Patents

Abstract

PURPOSE:To form a pattern for a through-hole, which has no burr, etc. and is shaped according to design size, by using GeO as a through-hole insulating film and an inter-layer insulating film material. CONSTITUTION:An inter-layer insulating film 32 and a NbN film 33 as a base electrode are applied onto an Si substrate 31. A resist pattern 34 is formed onto the film 33, the film 33 is ion-etched, and an unnecessary resist is removed. A lift-off mask 35 for shaping a through-hole for a junction is prepared. A GeO film is formed onto the whole surface. An inter-layer insulating film 36 with the through-hole for the junction is shaped through lift-off. Accordingly, a pattern for the through-hole for the Josephson junction, which has no burr, etc. and is extremely precise to design size, can be formed by using GeO as an insulating film material.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the production of Pb alloy-based and Nb-based Josephson junction elements, and particularly to a method of producing a through-hole for junction.

[Background of the invention]

Conventional Josephson junction devices have problems with the method of manufacturing through-holes for junctions, making it impossible to obtain patterns that meet the design dimensions, resulting in large variations in current density between each junction, and a reduction in operating margins for logic, memory circuits, etc. It was causing this.

First, the manufacturing process of a conventional bonding through hole and its problems will be explained using figures.

FIGS. 1(a) and 1(b) are explanatory diagrams showing a process for manufacturing a junction through hole of a conventional Josephson junction element. In the figure, 11 is a substrate, and 12 is a resist stencil mask (hereinafter referred to as a lift-off mask) having an overhang made of AZ resist (trade name of Sibley, Inc., USA).
, 13 is a SiO film.

As shown in FIG. 1(a), a SiO film 13, which is an insulating film material, was deposited using a lift-off mask 12, and a lift-off process was performed using a solvent to form a pattern.

However, the deposition particles of SiO are strongly scattered and adhere to the bottom and side walls of the overhang of the lift-off mask 12, and in the subsequent lift-off process 1, as shown in FIG. (the portion indicated by the dotted line ``peak 1'' circle), etc. remained, causing a reduction in the operating margin of the memory circuit according to the designed dimensions.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing an element having a Josephson junction through-hole pattern that is in accordance with the designed dimensions and is free from paris and the like.

[Summary of the invention]

In order to realize this, the present invention has been studied by changing various insulating film materials. That is, I n 205 +5n0
2. The target was GeO, etc. As a result, GeO can be easily vapor-deposited using the resistance heating method, and (a), as in the conventional method, the overhang area on the substrate 21 is patterned using the Odrigraph technique and the lift-off process is performed in addition to the fabrication of through-holes. This process is repeated in various steps. It is desirable that the lift-off masks produced in each process have an overhang, and the lift-off masks are used in various processes in the process of producing the Josephson junction element of the present invention.

The method for manufacturing a lift-off mask having an overbang portion is a known technique, and details are available from, for example, IBM Tech.
Bull, 19.4048 (1977).

Usually, a positive resist AZ1350J (trade name, manufactured by Shipley, Inc., USA) is used. Lift-O 3 = Tsumashu is fabricated by forming an altered layer on the resist surface using a pattern exposure machine and chlorobenzene immersion treatment, and the surface of the exposed portion during development treatment is a cross-sectional view of the main part of the Josephson junction element using a developer. be. Order (a) in the figure
The main steps will be explained in correspondence with (i).

(a): The substrate has a thickness of 50IIInlφ and a thickness of 400p.
m.

A <100> Si substrate 31 is used, and a 200 nm
GeO 32, which is an interlayer insulating film, is deposited. next,
On top of this, a 3-layer 5mTo
A film thickness of -200 nm was deposited by direct current high speed sputtering in a 10% N2 Ar mixed gas of rr.

(b): Made of 3 NbN films A resist mask for 3-on etching was prepared under the following conditions.

After applying A21350J resist to a thickness of 1 μm on the NbN film 33, pre-bake treatment at 70°C for 930 minutes. Bost baking was performed at a line density of 0.5 mA/c to maintain the cross-sectional shape of the tube 34.
Ion etching was performed under nT conditions. After etching, the substrate 31 was taken out of the vacuum chamber, and the resist on the NbN film 3 was removed by plasma ashing using oxygen gas to form a base electrode 33.

(d) A lift-off mask 35 for forming secondary bonding through holes was manufactured under the following conditions. After applying the AZ resist to a thickness of 1.2 μm on the base electrode 33 and the interlayer insulating film 32, pre-baking at 70° C. for 30 minutes, and then applying the AZ resist at an illuminance of 7.
Pattern exposure was performed for 20 seconds at mw/cd, and then chlorobenzene immersion treatment was performed for 10 minutes.
) was developed by developing for 90 seconds.

(e): Ar sputter cleaning was performed again in the vacuum chamber. The conditions at this time were RF power of 5 W, Ar pressure of 3×10 −3 Torr, and sputtering.

-1'5 (g): Next, the first lift for forming the counter electrode.
A first mask 37 was produced under the following conditions. AZ cash register +P
After coating the interlayer insulating film 36 with a film thickness of 1.5 μm, as described above (
It was formed by developing for 90 seconds with the same composition as b) and (d).

(h): The Si substrate 31 is inserted into a vacuum chamber, and after the degree of vacuum is once reduced to 4×10 −' Torr, the surface of the base electrode 33 exposed from the through hole is cleaned by Ar sputtering. The conditions at this time are -Ar pressure 3
X 10-3 Torr, acceleration voltage 800 V, and sputtering time 20 minutes. After this, once, 4X10'Torr
After the pressure was reduced to 1, 02 gas was injected into the vacuum chamber to bring the pressure to 1 atm, and thermal oxidation treatment was performed at a substrate temperature of 40° C. and an oxidation time of 30 minutes to form a tunnel barrier 38. next,
After reducing the vacuum degree in the vacuum chamber to 4 X I 0-7 Torr, Pb, Au, and In were sequentially coated in Ascent using a resistance heater in the same manner as in the production of Active 33 [film thickness of 40]. (For example, since 1μ- becomes thicker,
Considering that lift-off can be easily performed, the film thickness is 1.5
It was prepared by setting it to μm. After inserting it into a vacuum chamber and performing Ar sputter cleaning, GeO was deposited to a thickness of 1 μm. Lift-off was performed in the same manner as for forming the counter electrode described above, and a protective film (SiO film) 40 was formed.

Through the above steps, a Josephson junction element of the present invention comprising a base electrode of NbN and a counter electrode of a PbTn-Au alloy was completed.

〔Effect of the invention〕

It is clear from SEM (scanning electron microscope) observation images that the Josephson junction element according to the present invention uses the insulating film material GeO as described in the examples, and as a result, the junction dimensions are extremely faithful to the designed dimensions. Thus, a device with uniform bonding properties was confirmed. Furthermore, it was also revealed that GeO is extremely chemically stable, without dissolving or leaking in solvents or aqueous solutions.

As explained above, in the present invention, the insulating film can be changed from SiO to Ge.
Although GeO was replaced with O, the conventional process can be used as is for vapor deposition of GeO, and there is no particular problem.

Finally, the present invention was applied to an all-pb alloy process and an Nb-based process, and results with excellent bonding properties were obtained.

[Brief explanation of drawings]

Figures 1 (a) and (b) are explanatory diagrams of the manufacturing process of a through hole for junction in a conventional Josephson junction element, and Figure 2 (
a) and (b) are explanatory diagrams of the manufacturing process of a through hole for bonding according to the present invention, and FIG. 3 (a) GeO film, 32... interlayer insulating film (Sj○ film). 33.35.37...Lift-off mask. 34,...Base electrode (NbN film), 36...
Interlayer insulating film for bonding (G e O film), 38... tunnel barrier layer, 39... counter electrode (Pb-Au
-Tn film), 40...-protective film (SjO film). Figure 1 Figure 2 and

Claims (2)

[Claims] 1. A method for manufacturing a Josephson junction element, characterized in that GeO is used as a material for a through-hole insulation film and an interlayer insulation film for forming a Josephson junction by separating a base electrode and a counter electrode made of a superconducting thin film. 2. In the method for manufacturing a Josephson junction device according to claim 1, the superconducting thin film is made of Pb alloy-based,
Nb series, NbN, MoN, Nb_3Sn, Nb_3Al
, V_3Si, MoRe, etc. A method for manufacturing a Josephson junction element.