JPH0448788A - Formation of pattern of josephson junction element - Google Patents

Abstract

PURPOSE:To form a resist pattern with high reliability and with good reproducibility by a method wherein three-layer films of a lower-part electrode, a tunnel barrier layer and an upper-part electrode are formed continuously on a substrate and the resist pattern which prescribes a junction area is formed on the upper-part electrode film. CONSTITUTION:An Nb film of a lower-part electrode 12 is applied to an Si substrate 11 by a DC magnetron sputtering method. An AlOx layer 13 whose surface oxide film of Al is used as a tunnel barrier layer is formed. After three-layer films have been formed continuously, the Si substrate 11 is taken out from a sputtering apparatus. Then, a resist film 15 used to prescribe a junction area is formed on an upper-part electrode 14. A resist pattern 16 is formed. An insulating film 17 for filling-up use is formed, as a protective film, in one part on an etching part and on the upper-part electrode 14. At this time, the junction area at the Al oxide film and the AlOx layer is prescribed by the upper-part electrode 14 as the tunnel barrier layer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming a pattern of a Josephson junction element that operates at high speed at extremely low temperatures, and particularly to a method for forming a junction pattern suitable for highly integrated circuits.

[Prior Art] As a conventional method for forming a Josephson junction element, as described in JP-A-58-176983,
A method is used in which a lower electrode, a tunnel barrier layer, and an upper electrode made of a b/AlOx/Nb film are successively formed, and then a junction and wiring pattern are formed by dry etching using a desired resist pattern as a mask. It's here. According to this method, a high-quality junction can be obtained because there is no intervening pattern formation process, and this method has the great feature of being able to form Josephson junctions with low leakage current. Applications were underway.

[Problem to be solved by the invention]

However, in the conventional pattern forming method, there is a problem in the manufacturing process, and good reproducibility of one dimension of bonding area variation with respect to the design value cannot be obtained. In particular, when the mask pattern size at the junction is 2 μm or less, the influence of reflection from the underlying layer and the difference in resist film thickness between the top and bottom of the step are exposed.

The narrow margin of development conditions made it impossible to form a highly accurate resist pattern. In addition, there is a structural problem in backfilling the insulating film after dry etching the joint.
There is a problem in that micro-shorts and disconnection of wiring electrodes are likely to occur.

FIG. 2 shows the manufacturing process of a conventional Josephson junction element.

First, as shown in FIG. 2(a), a lower electrode 22 made of an Nb film is deposited on a substrate 21 to serve as a tunnel barrier layer.
x layer 23. A three-layer film of the upper electrode 24 made of a Nb film is deposited by sputtering.

Next, a positive resist is formed on the upper electrode 24 by spin coating.

After prebaking, a resist pattern including wiring and bonding portions 26 is formed by mask transfer and development as shown in FIG. 2(b). Next, as shown in FIG. 2(c), dry etching is performed to remove the upper electrode 24, except for the portion where the resist pattern 26 is formed. Tunnel barrier layer 23. The lower electrode 22 is removed by etching. After etching, unnecessary resist used as a mask is removed by a combination of oxygen plasma ashing and acetone to form an inductor pattern A and a wiring pattern B including a bonding portion.

Next, as shown in FIG. 2(d), a resist film 27 for defining the bonding area is formed by spin coating. After prebaking, bonding resist pattern 2 is formed as shown in FIG. 2(e).
8 is formed by mask transfer and development, then the second
As shown in Figure (f), AQOx is removed by dry etching.
Etching is performed until the layer 23 is exposed, and the upper electrode 24 is removed except for the portion where the resist pattern 28 is formed.

Next, as shown in FIG. 2(g), using the resist on the bonding pattern consisting of the upper electrode 24 as a lift-off mask, the etched portions of the lower electrode 22 and the upper electrode 24 are entirely covered with an insulating film 29 and buried. Next, as shown in FIG. 2(h), lift-off is performed using acetone to protect the exposed portion of the lower electrode 22 and the side wall of the bonding pattern consisting of the upper electrode 24 with an insulating film 29. Then the second
As shown in Figure (i), the surface of the upper electrode 24 is sufficiently coated with Ar.
Upper electrode connection wiring 3 after sputter cleaning
Complete by forming 0.

However, there are two problems with the above method:
It is a point. Namely.

The first point is that, as shown in FIG. 2(d), the resist film thickness is different between the upper and lower portions of the step (a, b), and the surface reflectance is different between the three-layer film and the substrate. That is,
Since the resist pattern defining the bonding area is formed on the upper electrode 24, exposure, T! The margin of the image condition is narrow and it is difficult to form it according to the designed dimensions. Actually, as shown in FIG. 2(e), the finished resist pattern size is formed smaller than the one-dot line (design size).

For this reason, the superconducting critical current (Ic) deviates from the designed value, resulting in a reduction in the circuit operation margin.

As a second point, as shown in FIG. 2(i), the upper electrode 24
When performing connection wiring with the upper electrode 24, it is necessary to completely remove the oxide film on the surface of the upper electrode 24 by Ar sputter cleaning. However, when the groove is formed, Ar particles are removed from the tunnel barrier layer AQOx23 during Ar sputter cleaning.
The etching progresses to the lower electrode layer.
For this reason, when a wiring electrode film is deposited, micro-shorts occur locally between the lower electrodes, causing deterioration of the bonding characteristics (A in the dotted circle in FIG. 2(i)).

On the other hand, if a break is formed, the connection wiring or the wiring pattern in the upper layer may be disconnected, resulting in a fatal defect (B in the dotted circle in FIG. 2(i)).

Due to the above-mentioned problems with conventional methods, it is difficult to form Josephson elements with high precision and a small bonding area according to the design dimensions with high reliability and good reproducibility. Met.

The object of the present invention is to use a highly accurate resist pattern as a mask for defining the junction area, and to create a Josephson bond with a structure in which no grooves or palls are formed when backfilling the insulating film during dry etching of the upper electrode Nb pattern. An object of the present invention is to provide a method for forming a pattern of an element.

[Means to solve the problem]

In order to achieve the above object, a method for forming a pattern of a Josephson junction element according to the present invention includes the following steps.

(1) Step of continuously forming a three-layer film of a lower electrode, a tunnel barrier layer, and an upper electrode on a substrate.

(2) A step of forming a resist pattern defining a bonding area on the upper electrode film, patterning the upper electrode film, and then backfilling the etched portion with an insulating film.

(3) After forming an inductor resist pattern including a bonding portion on the upper electrode bonding pattern and the insulating film, and patterning the insulating film, tunnel barrier layer, and lower electrode film, the etched portion is backfilled with the insulating film. The process of doing.

(4) forming a superconducting film on the upper electrode bonding pattern;
A step of forming and patterning a resist pattern for wiring and lower conductive connection wiring on the superconducting film.

Here, after dry etching, the unnecessary resist pattern that defines the above-mentioned bonding area and the unnecessary resist pattern for the inductor including the bonding pattern are shaped back by oxygen plasma ashing treatment, and the edges and corners of the part to be etched are Forms a slight terrace. After that, an insulating film is deposited and backfilled, that is, a structure is created in which the insulating film is deposited only on the outer periphery of the insulating film on the inductor pattern that includes the upper electrode and the bonding part that define the bonding area. It is something.

Specific materials for the three-layer film of the lower electrode, tunnel barrier layer, and upper electrode are Nb/AlOx/Nb, Nb/AlOx/Nb, and
b/AlOx/NbN, NbN/N b2O5/N b
It is preferable that the configuration be one of N.

[Effect]

When a mask pattern is transferred onto a resist by exposure, differences in the surface reflectance of the underlying material and non-uniformity in the resist film thickness caused by steps can narrow the margins for exposure and development conditions, making it impossible to form a highly accurate resist pattern. .

The key point of the present invention is to form a resist pattern that defines the bonding area immediately after sputtering the Nb/AlOx/Nb three-layer film.゛That is.

Immediately after three-layer film sputtering, the surface reflectance is uniform and the surface is flat, so the resist film thickness can be made thinner, and the margin for exposure and development conditions is wider, making it possible to create highly accurate resist patterns with good reproducibility. It becomes possible to form.

In addition, in the pattern forming process including the bonding pattern and the bonding portion described above, the step of receding the cross-sectional shape of the remaining resist pattern after shaping after etching and removing the portion to be etched other than the resist pattern may be performed as described above, for example. , slight terrace portions are formed at the ends and corners of the upper electrode. As a result, when the insulating film is deposited and backfilled, the insulating film can be deposited on the outer periphery of the upper electrode, and the insulating film on the outer periphery can also serve as a protective film during Ar sputter cleaning. This completely protects the end face of the upper electrode and eliminates the possibility of micro-shorts occurring in the connection wiring.

Furthermore, when backfilling the inductor pattern including the bonding portion, it is possible to flatten the inductor pattern, thereby improving the reliability of the wiring and the upper electrode connection wiring.

〔Example〕

FIG. 1 shows the steps for forming a Josephson junction element according to the present invention.

First, as shown in Figure 1(a), the substrate has a diameter of 50cm.
φ, <100> Si substrate 11 with a thickness of 450 μm (Actually, a 300 nm SiO film is applied on a 200 nm thick Nb ground plane, but this is omitted in FIGS. 1(a) to (j)) A film thickness of 160 to form the lower electrode 12 on top.
A Nb film of 1.0 nm thick is deposited by DC magnetron sputtering. The deposition conditions were Ar pressure 0.27 Pa and deposition rate 3 nm.
/ seconds.

Next, in the same sputtering apparatus, the Si substrate 11 is moved directly below the target of Jul, and the A river is deposited to a thickness of 6 nm. The deposition rate of the AQ film was 0.4 nm/sec. After AQ deposition, 0□ gas at 100 Pa is introduced into the sputtering equipment, and natural oxidation is performed for 40 minutes at room temperature (24 to 26°C) to form an AQOx layer in which the surface oxide film of AQ becomes a tunnel barrier layer (in this implementation). In the example, x=2)13 is formed.

After evacuating the sputtering equipment again, the S
The i-substrate 11 is moved directly below the Nb target, and a film thickness of 80 mm is formed to become the upper electrode 14 by DC magnetron sputtering.
Deposit a nm Nb film.

The deposition conditions were Ar pressure 0.8 Pa, deposition rate 3 nm/
It was done in seconds. After successively forming the three-layer film, the Si substrate 11 is taken out from the sputtering apparatus.

Next, a resist film 15 for defining the bonding area is formed on the upper electrode 14 under the following conditions.

After spin-coating AZ1470 resist (trade name of Hoechst, USA) to a thickness of 0.8 μm, prebaking was performed at 90°C for 2
6. Next, as shown in FIG. 1(b), using a photomask with a bonding area of 2 μm square, a light intensity of 16 mW/aj was applied.
After pattern exposure for 2.5 seconds with ultraviolet light using the contact method, AZ Developer (trade name of Hoechst, Inc., USA)
:Development was carried out for 60 seconds at a liquid temperature of 24° C. with a composition ratio of water=1=1, and after washing with water for 120 seconds.

Spin drying is performed to form a resist pattern 16 having a bonding area of 2 μm square.

Next, as shown in FIG. 1(c), after the upper electrode 14 is inserted into a vacuum device and the pressure is reduced, the upper electrode 14 is etched except for the joint portion by reactive ion etching using CF4 gas until the AnOX layer 13 is exposed. Remove. The etching conditions at this time were CF4 gas pressure of 26 Pa and electric power of 10
This is done for 5 minutes under 0W conditions.

Next, as shown in FIG. 1(d), after being taken out of the vacuum apparatus, the resist pattern on the upper electrode 14 is subjected to surface hardening treatment by sputter etching with 08 gas under the following conditions: 02 gas pressure. 0.8 Pa, high frequency power of 300 W, processing time is 13 minutes. Next, plasma ashing treatment is performed at 0.2 gas pressure of 65 Pa, high frequency power of 300 W, and processing time of 5 minutes. As a result, the receding dimension of the resist is approximately 200 nm from the edge of the bonding pattern, and the resist surface is approximately 1100 nm.
n decreases, and a terrace portion (inside the dotted circle) is formed on the upper electrode 14. On the other hand, the cross-sectional dimensions of the resist pattern after processing are formed such that the lower width is smaller than the upper width by about 200 nm.

Next, as shown in FIG. 1(e), S is deposited by vacuum evaporation method.
The etched portion is backfilled using i as an insulating film. That is, using the resist pattern 16 on the upper electrode 14 after reactive ion etching as a lift-off task, an insulating film 17 with a thickness of 1300 nm is deposited over the entire surface. On this occasion,
An insulating film approximately 1.5 times as thick as the upper electrode 14 is deposited.

At this time, as is clear from FIG. 1, it can be seen that the insulating film 17 is also deposited on the terrace portion formed by removing the resist pattern 16 of the upper electrode 14.

Next, as shown in FIG. 1(f), the insulating film 1 for backfilling is
7 is formed as a protective film on the etched portion and a portion of the upper electrode 14. At this point, the junction area of the AQ oxide film AΩ○X layer is defined by the upper electrode 14 as a tunnel barrier layer.

Next, in FIG. 1(g), a resist pattern for forming an inductor including a bonding portion is formed under the following conditions.

After spin-coating AZ1350J resist (trade name of Hoechst, USA) to a thickness of 1.2 μm, prebaking was performed at 90°C.
Process for 20 minutes. Then, light intensity 16mW/a
# After pattern exposure for 6 seconds with UV light using the contact method, development was performed for 60 seconds in a liquid crystal at 24°C with the composition ratio of AZ developer:water = 1 = 1, washed with water for 120 seconds, and then spun. After drying, a resist pattern 18 for forming an inductor including a bonding portion is formed.

Next, in FIG. 1(h), the insulating film 17°AQOx
In order to perform etching on the upper and lower electrodes 12 of the layer 13, the resist pattern 18 is inserted into a vacuum device and the pressure is reduced, and then the resist pattern 18 is etched by reactive ion etching using CF and gas.
The remaining Si insulating film 17 is removed for 5 minutes.The formation conditions are the same as those for the bonding pattern described above.When the AQ surface oxide film AQ Ox layer 13 is exposed, switch to ion etching with Ar and use Ar gas. The AQ Ox layer 13 other than the resist pattern 18 is etched for 3 minutes under the conditions of a pressure of 2 mPa, an accelerating voltage of 600 eV, and an ion current density of 0.5 mA/d6.Next, the lower electrode 12 is etched with the above-mentioned upper electrode 14 and the Si insulator. Nb under the same conditions as the membrane
Etch the membrane for 10 minutes.

After the etching is completed, the resist pattern 18 on the Si insulating film 17 is removed from the vacuum apparatus and subjected to a combination of sputter etching using O gas and plasma ashing under the same conditions as the resist pattern for defining the bonding area described above. , the side walls of the resist pattern 18 are recessed to form terraces.

Next, a Si insulating film 19 having a thickness of 280 nm is deposited over the entire surface by vacuum evaporation to backfill the etched portion using Si as an insulating film.

Next, lift-off is performed with acetone in FIG. 1(i). As shown in the figure, an insulating film 19 for backfilling is formed on the etched portion and a portion of the first backfilling insulating film 17 for protection.

Next, in FIG. 1(j), in order to make a connection on the upper electrode 14, the surface is cleaned by sputter etching with Ar gas.Next, a Nb film 20 for wiring and connection wiring is formed with a thickness of 300 nm. to adhere to. The conditions for depositing the Nb film are as described above for lower electrode 12. Like the upper electrode 14, it is deposited by DC magnetron sputtering. After taking it out from the sputtering apparatus, a resist pattern (shown in the figure) for wiring and connection wiring is formed under the same conditions as the inductor pattern including the bonding part. Next, the Nb film 20 other than the resist pattern is etched by reactive ion etching using CF and gas under the same conditions as the bonding pattern and inductor pattern described above.
Remove by etching. After etching is completed, remove the resist from inside the vacuum equipment, remove the resist on the pattern with acetone, and place it! 20 and a wiring electrode 20' connected to the upper mold pi 14.

After completing the above steps, the formation of the Nb/AMOx/Nb Josephson junction element is completed.

Note that although Nb was used for the superconductor in this embodiment, the present invention is not limited to this, and NbN may be used.

Similar effects can be obtained even when a pb gold alloy is used.

C Effects of the invention] Comparing the finished area of the bonding resist pattern of the present invention and the resist pattern formed by the conventional method, in the case of the designed value of 2 μm square, there was a variation of ±20% in the conventional method, but this In the present invention, it has become possible to control ±600 nm in terms of zero-dimensional cell density, which has become possible to suppress it to ±5% or less.

In addition, the resist film thickness can be reduced by about 40% compared to conventional methods, and the margins for exposure and i-image conditions are about twice as wide, making it possible to form resist patterns with minute dimensions of 1 μm μm or less. .

In addition, micro-shorts that occur between the lower electrode and upper electrode connection wiring, which were problems in the past, or disconnections in the upper layer wiring pattern can be prevented by flattening the Nb/A Q Ox/Nb series Josephson, which has extremely high reliability. Son junction elements can be formed with good reproducibility.

For example, the distribution width of the superconducting critical current (I c) of 1,5 μm square Josephson junctions connected in series was within ±4% of the design value. This greatly improves reliability and expands the operating margin of Josephson integrated circuits made of microjunctions.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the manufacturing process of the Josephson junction element of the present invention, and FIG. 2 is a cross-sectional view showing the manufacturing process of the Josephson junction element of the conventional method. 11.21...Substrate, 12.22...Lower electrode, 1
3゜26...AQoX layer, 14.24・1 part electrode, 1
5゜25.27...Resist film, 16,18,26゜28...Resist pattern, 17,19,29...
Insulating film, 20... Wiring, 20', 30... Connection wiring electrode, A part... Inductor pattern including a joint part, B part... Wiring. ■ Diagram■ Diagram

Claims (1)

[Claims] 1. A method for forming a pattern of a Josephson junction element, characterized by comprising the following steps. (1) Step of continuously forming a three-layer film of a lower electrode, a tunnel barrier layer, and an upper electrode on a substrate. (2) A step of forming a resist pattern defining a bonding area on the upper electrode film, patterning the upper electrode film, and then backfilling the etched portion with an insulating film. (3) After forming an inductor resist pattern including a bonding portion on the upper electrode bonding pattern and the insulating film, and patterning the insulating film, tunnel barrier layer, and lower electrode film, the etched portion is backfilled with the insulating film. The process of doing. (4) A step of forming a superconducting film on the upper electrode bonding pattern and the insulating film, forming a resist pattern for wiring and upper electrode insulating wiring on the superconducting film, and performing pattern processing. 2. Above, the lower electrode, tunnel barrier layer and upper three-layer film are Nb/AlO_x/Nb, Nb/AlO_x/Nb
A method for forming a pattern of a Josephson junction element according to claim 1, characterized in that the patterning method comprises a three-layer film structure of one of N, NbN/Nb_2O_5/NbN. 3. The Josephson junction element according to claim 1, wherein the insulating film is backfilled by using the etched resist pattern as a lift-off mask after shaping and retreating it by oxygen plasma ashing treatment. pattern formation method. 4. The method for forming a pattern of a Josephson junction element according to claim 1, wherein the superconducting film is at least one selected from the group consisting of Nb, NbN, and Pb alloys.