JPS61136266A - Manufacture of bipolar type semiconductor device - Google Patents

Manufacture of bipolar type semiconductor device

Info

Publication number
JPS61136266A
JPS61136266A JP59258520A JP25852084A JPS61136266A JP S61136266 A JPS61136266 A JP S61136266A JP 59258520 A JP59258520 A JP 59258520A JP 25852084 A JP25852084 A JP 25852084A JP S61136266 A JPS61136266 A JP S61136266A
Authority
JP
Japan
Prior art keywords
film
conductivity type
etching
polycrystalline silicon
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59258520A
Other languages
Japanese (ja)
Other versions
JPH04590B2 (en
Inventor
Takao Ito
隆夫 伊藤
Yasuhiro Katsumata
勝又　康弘
Kiyoshi Takaoki
高沖　潔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59258520A priority Critical patent/JPS61136266A/en
Priority to DE8585109543T priority patent/DE3580206D1/en
Priority to EP19850109543 priority patent/EP0170250B1/en
Publication of JPS61136266A publication Critical patent/JPS61136266A/en
Publication of JPH04590B2 publication Critical patent/JPH04590B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To prevent a situation wherein a short circuit fails to be established between an external base region and activation base region by a method wherein a lamination of a non-single-crystal silicon film and metal silicide film is subjected to etching for the removal of the metal silicide film and the remaining silicon film is subjected to oxidation for the formation of a lead-out electrode. CONSTITUTION:On a P type silicon substrate 1, an N<+> type buried region 2, field oxide film 4, and N<+> type collector contact region 5 are formed. Then a polycrystalline silicon film 6, MoSi2 film 7 are deposited. Etching is accomplished for the formation of a lamination pattern of the films 6, 7. A process follows of the selective implantation of boron ions. An SiO2 film 8 is deposited, the films 7, 8 are subjected to etching with a resist 9 serving as a mask for the exposure of the polycrystalline silicon film 6. Thermal oxidation is accomplished for the conversion of the exposed portion of the film 6 into an oxide film 11 for an electrode 10 for leading out a base. Heat treatment follows wherein boron is diffused for the formation of a P<+> type external base region 12 and boron ions are implanted through the opening for the formation of a P type activation base region 13. With the surface of an epitaxial layer 3 being not affected by etching, the regions 12, 13 are ensured to be connected by a short circuit.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はバイポーラ型半導体装置の製造方法に関し、特
に、セルファライン方式により外部べ一ス／′エミッタ
間の距離を縮小してベース抵抗を下げ、高速動作を可能
としたバイポーラ型半導体装置を製造する方法の改良に
係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a bipolar semiconductor device, and in particular to a method for manufacturing a bipolar semiconductor device, in particular, a self-line method is used to reduce the distance between the external base and the emitter to lower the base resistance. This invention relates to an improvement in a method for manufacturing a bipolar semiconductor device that enables high-speed operation.

〔発明の技術的背景〕[Technical background of the invention]

バイポーラ型半導体装置の高速動作特性および高周緯特
性を改善するために従来行なわれている方法は、イオン
注入法による浅い接合の形成、溝切り構造等による基板
／コレクタ間の寄生容量の低減、自己整合法等の微細加
工技術によるベース／コレクタ間、ベース／エミッタ間
の寄生容量を低減することである。Conventional methods for improving the high-speed operation characteristics and high-frequency characteristics of bipolar semiconductor devices include forming shallow junctions using ion implantation, reducing parasitic capacitance between the substrate and collector using grooved structures, etc. The aim is to reduce the parasitic capacitance between base/collector and base/emitter using microfabrication techniques such as self-alignment methods.

例えば、特公昭５７−４１８２６号公報には、多結晶シ
リコン層からなる゛ベース取出し電極を採用することに
よりベース／コレクタ間の容ｉを低減する技術が開示さ
れている。For example, Japanese Patent Publication No. 57-41826 discloses a technique for reducing the capacitance i between the base and the collector by employing a base lead-out electrode made of a polycrystalline silicon layer.

また、特開昭５７−５３９７９号公報には、多結晶シリ
コン層からなるベース取出し電極を拡散源として外部ベ
ース領域を形成した後、このベース取出し電極側壁に形
成したサブミクロン膜厚の酸化膜を利用して活性ベース
領域とエミッタ領域とを自己整合で形成することにより
、ベース抵抗を低減する技術が開示されている。これと
同様な技術は、特公昭５６−４４５７号公報、特開昭５
７−１８６３６０号公報、特開暇５７−１８６３５９号
公報、特開昭５７−１８８８７２＠公報にも開示されて
いる。Furthermore, Japanese Patent Application Laid-Open No. 57-53979 discloses that after forming an external base region using a base extraction electrode made of a polycrystalline silicon layer as a diffusion source, a submicron-thick oxide film is formed on the side wall of the base extraction electrode. A technique has been disclosed for reducing base resistance by forming an active base region and an emitter region in self-alignment. Techniques similar to this are disclosed in Japanese Patent Publication No. 56-4457 and Japanese Patent Application Laid-open No. 5
It is also disclosed in JP-A No. 7-186360, JP-A-57-186359, and JP-A-57-188872@.

更に、特公昭５５−２６６３０号公報、特公昭５５−２
７４６９号公報、特公昭５７−３２５１１号公報には、
多結晶シリコン層からなるベース取出し電橋の形成に際
し、酸化膜等の段差を利用した自己整合技術を導入して
ベース／コーク９間容量を低減する技術が開示されてい
る。Furthermore, Japanese Patent Publication No. 55-26630, Japanese Patent Publication No. 55-2
In Publication No. 7469 and Japanese Patent Publication No. 57-32511,
When forming a base lead-out electric bridge made of a polycrystalline silicon layer, a technique has been disclosed in which a self-alignment technique using steps such as an oxide film is introduced to reduce the capacitance between the base and the coke 9.

上記の公知技術の他、本発明の関連５．術としては出願
人が特願昭５９−１６０５１８号として先に出願したも
のが挙げられる。この先願発明は、多結晶シリコン膜お
よび金属シリサイド膜の積層膜からなるベース取出し電
極を用いることによりベース抵抗を更に低減し、高速動
作および高周波特性を一段と向上することを可能とした
ものである。In addition to the above-mentioned known techniques, related to the present invention 5. An example of this technique is the one previously filed by the applicant as Japanese Patent Application No. 160518/1983. This prior invention makes it possible to further reduce base resistance and further improve high-speed operation and high-frequency characteristics by using a base lead-out electrode made of a laminated film of a polycrystalline silicon film and a metal silicide film.

〔背景技術の問題点〕[Problems with background technology]

ｔＪ掲の公知技術においても奇生容量の低減については
略満足できる程度に達成されていると考えられる。しか
し、多結晶シリコンの層抵抗は単結晶シリコンに同量の
不純物を添加した場合に比較して約３〜５＠の高い値に
なるため、多結晶シリュン層をベース取出し電極に用い
た公知技術では全体的なベース抵抗ｒ　ｂｂ’　が高く
ならざるを得ず、高速動作特性について満足できる結果
が得られない。そこで、ベース取出し電極用の多結晶シ
リコン層の膜厚を４０００〜６０００人と厚くしてベー
ス取出し１ｉ極の抵抗を下げるようにしているが、それ
でも５０〜５００Ω／口程度の値しか得られていない。It is considered that the known technique disclosed in tJ has also achieved a substantially satisfactory reduction in parasitic capacitance. However, since the layer resistance of polycrystalline silicon is about 3 to 5@ higher than that when the same amount of impurities is added to single crystal silicon, the known technology using a polycrystalline silicon layer as the base extraction electrode In this case, the overall base resistance r bb' must become high, and satisfactory results regarding high-speed operation characteristics cannot be obtained. Therefore, attempts were made to increase the thickness of the polycrystalline silicon layer for the base lead-out electrode by 4,000 to 6,000 layers to lower the resistance of the base lead-out 1i electrode, but even so, only a value of about 50 to 500 Ω/hole was obtained. do not have.

また、前掲の公知技術は製造プロセス上の観点から第１
０図〜第１２図に示すような問題があった。即ち、これ
らの公知技術においては、第１０図に示すように選択的
にフィールド酸化膜２２が形成されているＮ型エピタキ
シャルシリコン！！２１の上にベース−“取出し電極用
の多結晶シリコン層（ボロン添加）２３を堆積した後、
イオンミリング等の方法を用いて該多結晶シリコン層２
３に活性ベース領域形成用の拡散窓２４を開孔し、エピ
タキシャル層２１表面を露出する工程が含まれている。In addition, the above-mentioned known technology is the first technology from the viewpoint of manufacturing process.
There were problems as shown in Figures 0 to 12. That is, in these known techniques, as shown in FIG. 10, an N-type epitaxial silicon film on which a field oxide film 22 is selectively formed is used. ! After depositing a polycrystalline silicon layer (boron-doped) 23 for the base-extraction electrode on 21,
The polycrystalline silicon layer 2 is formed using a method such as ion milling.
Step 3 includes the step of opening a diffusion window 24 for forming an active base region and exposing the surface of the epitaxial layer 21.

この場合、多結晶シリコン層２３およびエピタキシャル
シリコン層２１が同一物質でエツチングされる速度が略
同じであることから、エツチング終了の判定が極めて困
難である。そのため、多結晶シリコン層２３の膜厚のバ
ラツキを考慮してオーバーエツチングすることが一般的
に行なわれる結果、第１１図に示したように、エピタキ
シャル１１２１の表面が多結晶シリコン層２３の膜厚（
４０００〜６０００人）の２０〜５０％、即ち、０．１
〜０．３戸程度削られてしまう事態が発生することにな
る。In this case, since the polycrystalline silicon layer 23 and the epitaxial silicon layer 21 are etched with the same material at substantially the same speed, it is extremely difficult to determine whether etching has finished. Therefore, over-etching is generally performed in consideration of the variation in the thickness of the polycrystalline silicon layer 23. As a result, as shown in FIG. (
20-50% of 4,000-6,000 people), i.e. 0.1
A situation will occur where approximately 0.3 houses will be removed.

その結果、多結晶シリコン層２３を拡散源としてＰ“型
の外部ベース領域２５を形成した後、開孔部２４からボ
ロンのイオン注入等によりＰ型活性ベース領域２６を形
成したとぎに、第１２図に示したように両頭１ｆｔ２５
．２６が短絡せずに分離してしまい、正常なトランジス
タ動作が得られなくなるという問題を生じていた。なお
、第１２図において、２７は層間絶縁膜としてのＣＶＤ
−８ｉ０２１Ｉ、２８ハＣＶＤ−３ｉ　０２　ＭＧ！２
７１．：開孔した拡散窓から燐をドープして形成された
Ｎ＋型エミッタ領域、２９はエミッタ電極である。As a result, after forming a P" type external base region 25 using the polycrystalline silicon layer 23 as a diffusion source, and forming a P type active base region 26 by implanting boron ions through the opening 24, Double head 1ft25 as shown in the figure
．． 26 is separated without being short-circuited, resulting in a problem that normal transistor operation cannot be obtained. In addition, in FIG. 12, 27 is a CVD film as an interlayer insulating film.
-8i021I, 28ha CVD-3i 02 MG! 2
71. : An N+ type emitter region formed by doping phosphorus through an open diffusion window; 29 is an emitter electrode;

なお、上記第１０図〜第１２図で説明した問題を防止す
る方法として、例えば特公昭５５−２６６３０号公報に
は、イオンミリングで前記開孔部２４を形成する際に多
結晶シリコン層２３を極り薄り残しく例えば１０００人
程度）、然る後にケミカルエツチングによりエピタキシ
ャル層表面を露出させ、或いは多結晶シリコン層を熱酸
化して除去する繰り返すことによりエピタキシャル層表
面を露出させる方法が記載されている。しかし、この方
法では工程が複雑化せざるを得ず、またケミカルエツチ
ングや熱酸化では等方的に多結晶シリコン層が除去され
るから開孔部２４の大きさにバラツキを生じるという問
題を有している。As a method for preventing the problems explained in FIGS. 10 to 12 above, for example, Japanese Patent Publication No. 55-26630 discloses a method for forming the polycrystalline silicon layer 23 when forming the opening 24 by ion milling. A method is described in which the surface of the epitaxial layer is exposed by chemical etching, or by repeatedly removing the polycrystalline silicon layer by thermal oxidation. ing. However, this method inevitably complicates the process, and chemical etching and thermal oxidation remove the polycrystalline silicon layer isotropically, resulting in variations in the size of the openings 24. are doing.

他方、出願人の先願に係る特願昭５９−１６０５１８号
の方法ではベース取出し電極を構成する多結晶シリコン
層の上に金属シリサイド膜を積層したから、高速動作特
性のためベース抵抗ｒ　ｂｂ’　を低減する課題は略達
成することができた。しかし、この場合にも開孔部２４
の形成に際してエピタキシャル層表面を０．１〜０．２
ＩＪ！ｒＬエツチングしてしまうことになり、第１０図
〜第１２図で説明した問題については既述の公知例と同
様の問題を有している。On the other hand, in the method of Japanese Patent Application No. Sho 59-160518 related to the applicant's earlier application, a metal silicide film is laminated on the polycrystalline silicon layer constituting the base lead-out electrode, so the base resistance r bb' is reduced due to high-speed operation characteristics. The task of reducing this was almost achieved. However, in this case as well, the opening 24
When forming the epitaxial layer surface to 0.1 to 0.2
IJ! This results in rL etching, and the problems explained in FIGS. 10 to 12 are similar to those of the previously mentioned known examples.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、全体的なベ
ース抵抗ｒ　ｂｂ’　を低減して高速動作特性および高
周波特性に優れたバイポーラ型半導体装置を製造するこ
とができ、且つ外部ベース領域と活性ベース領域とが短
絡しなくなる事態を回避できる安定した製造方法を提供
しようとするものである。The present invention has been made in view of the above circumstances, and it is possible to manufacture a bipolar semiconductor device that reduces the overall base resistance r bb' and has excellent high-speed operation characteristics and high-frequency characteristics, and that also has an external base region. The purpose is to provide a stable manufacturing method that can avoid short-circuiting with the active base region.

〔発明の概要］ 本発明によるバイポーラ型半導体装置の製造方法は、第
一８１電型半導体層の一部上に非単結晶シリコン膜およ
び金属シリサイド膜の積層膜パターンを形成する工程と
、この積層膜パターンに第二導電型不純物をドープする
工程と、前記積層膜パターンの一部分において、金属シ
リサイドに対し選択性を有するエツチング法により前記
金属シリサイド膜のみをエツチング除去し、当該部分に
おいて前記非単結晶シリコン膜を露出させる工程と、こ
の非単結晶シリコン膜の露出部分を酸化することにより
取出し電極を形成する工程と、熱処理により前記取出し
電極から前記第一導電型半導体層内に前記不純物を拡散
させて第二導電型高濃度不純物領域を形成する工程と、
前記非単結晶シリコン膜の酸化領域から前記第一導電型
半導体層に選択的に第二導電型不純物をドープすること
により、前記第二導電型高濃度不純物ｆｒ４域に接した
第二導電型低濃度不純物領域を形成する工程と、前記取
出し電極を覆う絶縁膜を堆積した後、該絶縁膜に対して
異方性エツチングを施すことにより前記取出し電極の側
壁に絶縁膜を残存させる工程と、前記第二導電型低濃度
不純物領域内に第一導電型高濃度不純物領域を形成する
工程とを具備したことを特徴とするものである。[Summary of the Invention] A method for manufacturing a bipolar semiconductor device according to the present invention includes a step of forming a laminated film pattern of a non-single-crystal silicon film and a metal silicide film on a part of a first 81-voltage type semiconductor layer; A step of doping the film pattern with a second conductivity type impurity, and etching away only the metal silicide film in a part of the laminated film pattern using an etching method that is selective to the metal silicide, and removing the non-single crystal in that part. a step of exposing a silicon film, a step of forming an extraction electrode by oxidizing the exposed portion of the non-single crystal silicon film, and a step of diffusing the impurity from the extraction electrode into the first conductivity type semiconductor layer by heat treatment. forming a second conductivity type high concentration impurity region;
By selectively doping a second conductivity type impurity from the oxidized region of the non-single crystal silicon film into the first conductivity type semiconductor layer, a second conductivity type low concentration impurity adjacent to the second conductivity type high concentration impurity fr4 region is doped. a step of forming a concentrated impurity region; a step of depositing an insulating film covering the extraction electrode and then anisotropically etching the insulating film to leave the insulating film on the sidewall of the extraction electrode; The method is characterized by comprising a step of forming a first conductivity type high concentration impurity region within the second conductivity type low concentration impurity region.

上記本発明の方法は出願人による前述の先願発明を改良
したもので、先願発明による効果をそのまま具備してい
る。即ち、非単結晶シリコン膜および金属シリサイド膜
の積層構造からなるベース取出しｉ！極としたことから
、ベース抵抗ｒ　ｂｂ’　を低減して高速動作特性を改
善できる。また、異方性エツチングで取出し電極の（ａ
ｌｌに形成したサブミクロン膜厚の絶縁膜を利用し、第
一導電型高濃度不純物領ｌｉｔ！（外部ベース領域）、
第二導電型低濃度不純物領域（活性ベース領域）および
第一導電型高濃度不純物領域（エミッタ領域）を自己整
合で形成できる。従って、素子を微細化が可能となり、
活性ベース領域の層抵抗を低減して高速動作特性を更に
向上できる。The method of the present invention is an improvement on the aforementioned earlier invention by the applicant, and has the effects of the earlier invention as they are. That is, the base extraction i! consists of a laminated structure of a non-single crystal silicon film and a metal silicide film. Since it is a pole, the base resistance r bb' can be reduced and high-speed operation characteristics can be improved. In addition, the extraction electrode (a
Using the submicron-thick insulating film formed in the first conductivity type high concentration impurity region lit! (external base area),
The second conductivity type low concentration impurity region (active base region) and the first conductivity type high concentration impurity region (emitter region) can be formed in a self-aligned manner. Therefore, it is possible to miniaturize the element,
The layer resistance of the active base region can be reduced to further improve high-speed operation characteristics.

上記の効果に加え、本発明では前記積層膜パターンから
取出し電極を形成する際のエツチングにおいて、前記金
属シリサイド膜のみを除去して前記非単結晶シリコン層
は残存させ、事後この残存非単結晶シリコン層部分を酸
化することとしてる。In addition to the above effects, in the present invention, only the metal silicide film is removed and the non-single crystal silicon layer is left in etching when forming the lead-out electrode from the laminated film pattern. The layer portion is oxidized.

従って、先行開示技術のように半導体層（エピタキシャ
ル層）の表面までオーバーエツチングする事態を回避で
き、外部ベース領域と活性ベース領域とが短絡しなくな
るといった問題の発生を防止することができる。Therefore, it is possible to avoid a situation where the surface of the semiconductor layer (epitaxial layer) is over-etched as in the prior art, and it is possible to prevent the occurrence of a problem in which the external base region and the active base region are not short-circuited.

〔発明の実施例〕[Embodiments of the invention]

以下、第１図〜第８図を参照して本発明の一実施例を説
明する。Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 to 8.

（１）先ず、Ｐ型シリコン基板１の一部に選択的にＮゝ
型型埋領領域２形成した後、全面にＮ型エピタキシャル
シリコンＩ！！３を成長させ、続いて選択酸化法により
膜厚６０００〜１００００人のフィールド酸化膜４を形
成する。次いで、フィールド酸化膜４に囲まれたエピタ
キシャル層３の一部にＮ型不純物をドープすることによ
り、Ｎ＋型コレクタコンタクト領域５を形成する。続い
て、ＬＰＣＶＤ法により全面に躾厚約５００人の不純物
無添加多結晶シリコン！１１６を堆積し、更にスパッタ
法により全面に膜厚約３０００人のＭＯ８ｉｚ１７を堆
積する（第１図々示）。(1) First, after selectively forming an N-type buried region 2 in a part of a P-type silicon substrate 1, N-type epitaxial silicon I! is formed on the entire surface. ! Then, a field oxide film 4 having a thickness of 6,000 to 10,000 oxides is formed by selective oxidation. Next, a part of the epitaxial layer 3 surrounded by the field oxide film 4 is doped with N type impurities to form an N+ type collector contact region 5. Next, the entire surface was coated with impurity-free polycrystalline silicon approximately 500 times thick using the LPCVD method! 116 is deposited, and MO8iz17 is further deposited to a thickness of about 3000 on the entire surface by sputtering (as shown in the first figure).

（′２Ｊ　　次に、ケミカルドライエツチング（ＣＤＥ
）或いは反応性イオンエツチング（ＲＩＥ）によりＭＯ
３ｉ２膜７および多結晶シリコン膜６を順次パターンニ
ングして積層膜パターンを形成した後、該積層膜パター
ンに対し、加速エネルギー４０〜５０ｋｅＶ、ドーズ１
１ｏ１５〜１０ＩＩＩ／ｃＩｉの条件で選択的にボロン
をイオン注入する。続いて、全面に膜厚３０００〜４０
００人のＣＶＤ−８ｉ　０２１１８を堆積する（第２図
々示）。('2J Next, chemical dry etching (CDE)
) or by reactive ion etching (RIE)
After sequentially patterning the 3i2 film 7 and the polycrystalline silicon film 6 to form a laminated film pattern, the laminated film pattern is subjected to an acceleration energy of 40 to 50 keV and a dose of 1.
Boron ions are selectively implanted under conditions of 1o15 to 10III/cIi. Subsequently, a film thickness of 3000 to 40
Deposit 00 CVD-8i 02118 (as shown in the second figure).

（３次に、活性ベース領域予定部上に開孔部を有するフ
ォトレジストパターン９を形成した後、これをマスクと
し、ＣＦ４を反応ガスとしたＲＩＥによりＣＶＤ−３＋
　０２　ＷＡ８をエツチングして開孔部を形成する。Ｍ
ｏ５ｉｚ膜７が露出した時点で反応ガスをＣｌ２１０２
の混合ガスに切替えてＲＩＥを続行し、ＭＯ８ｉｚ膜７
のみを除去して多結晶シリコン膜６を露出させる（第３
図々示）なお、Ｃｌ２１０２を反応ガスとしたＲＩＥに
よるＭＯ８ｉｚと多結晶シリコンのエツチング速度は第
９図に示す通りである。図示のように、このＲＩＥは多
結晶シリコンに比較してＭＯ３ｉｚに対する充分な選択
性を有しているから、第３図の状態でエツチングを停止
し、多結晶シリコン膜６を残存させることは容易に行な
うことができる。(Thirdly, after forming a photoresist pattern 9 having an opening on the planned active base region, using this as a mask, RIE using CF4 as a reaction gas was performed to form a CVD-3+
02 Etch WA8 to form openings. M
When the o5iz film 7 is exposed, the reaction gas is changed to Cl2102.
Continue RIE by switching to the mixed gas of
Only the polycrystalline silicon film 6 is removed to expose the polycrystalline silicon film 6 (third
Note that the etching rate of MO8iz and polycrystalline silicon by RIE using Cl2102 as a reaction gas is as shown in FIG. As shown in the figure, since this RIE has sufficient selectivity for MO3iz compared to polycrystalline silicon, it is easy to stop the etching in the state shown in FIG. 3 and leave the polycrystalline silicon film 6. can be done.

（勾　次に、レジストパターン９を除去した後、熱酸化
を行ない、多結晶シリコンｌ１１６の露出部分を酸化［
１１１に転化することにより、ベース取出し電極１０を
形成する。続いて、１０００〜１１００℃で熱処理を行
なうことによりＭＯ８ｉ２膜７および多結晶シリコン膜
６にド・−プされたボロンを拡散させ、Ｐ＋型外部ベー
ス領１ｉｉ！１２を形成する。更に、加速エネルギー４
０ｋｅＶ、ドーズ量１０１４／ｄの条件で、前記ＲＩＥ
で形成した開孔部から選択的にボロンをイオン注入する
ことによりＰ−型活性ベース領域１３を形成する（第４
図々示）。(Next, after removing the resist pattern 9, thermal oxidation is performed to oxidize the exposed portion of the polycrystalline silicon l116.
111, the base extraction electrode 10 is formed. Subsequently, by performing heat treatment at 1000 to 1100° C., the boron doped in the MO8i2 film 7 and the polycrystalline silicon film 6 is diffused to form a P+ type external base region 1ii! form 12. Furthermore, acceleration energy 4
The above RIE was carried out under the conditions of 0 keV and a dose of 1014/d.
A P-type active base region 13 is formed by selectively implanting boron ions through the opening formed in the fourth step.
(Illustrated).

こうして、Ｐ＋型外部ベース領域１２およびＰ−型活性
ベース領域１３が自己整合で形成され、しかもエピタキ
シャル層３の表面は従来のようにエツチングされていな
いから、両頭域１２．１３は確実に短絡接続して形成さ
れることになる。In this way, the P+ type external base region 12 and the P- type active base region 13 are formed in a self-aligned manner, and since the surface of the epitaxial layer 3 is not etched as in the conventional case, the double-headed regions 12 and 13 are reliably short-circuited. It will be formed as follows.

（５）　　次に、全面ニ脱厚３０００〜５０００人（７
）ＣＶＤ−５ｉ０２膜１４を堆積した後、９００〜１０
００℃で熱処理を行ない、ＣＶＯ−８ｉ０２膜１４のア
ニールと活性ベース領ｆｉｔ！１３のアニールを行なう
（第５図々示）。(5) Next, 3,000 to 5,000 people (7
) After depositing CVD-5i02 film 14, 900-10
Heat treatment is performed at 00°C to anneal the CVO-8i02 film 14 and fit the active base region! No. 13 annealing is performed (shown in Figure 5).

（６）　　次に、ＣＦ４を用いたＲＩＥによりＣＶＤ−
８ｉＯ２膜１４および熱酸化膜１１をエツチングするこ
とにより、取出し１１４１０およびＣＶＤ酸化膜８の側
壁に−ＣＶＤ−８ｉ　０２膜１４′を残存させる。続い
て、ＲＩＥにより活性ベース領域１３の表面に生じたダ
メージをアルカリウェットエツチングにより除去する（
第６図々示）。(6) Next, CVD-
By etching the 8iO2 film 14 and the thermal oxide film 11, the -CVD-8i02 film 14' remains on the lead-out 11410 and the sidewall of the CVD oxide film 8. Subsequently, damage caused to the surface of the active base region 13 by RIE is removed by alkali wet etching (
(shown in Figure 6).

（７）　　次に、全面に多結晶シリコン膜を堆積した後
、該多結晶シリコン膜に対し加速エネルギー４０〜５０
ｋｅＶ、ドーズ１１０１　Ｓ　〜１０１　”　／ｃＩｉ
の条件で燐もしくは砒素、或いは燐および砒素の両者を
イオン注入する。次いで、この多結晶シリコン脹をパタ
ーンニングしてＮ型多結晶シリ６ンパターン１５を形成
した後、８００〜９００℃で数１０分間熱処理を行なう
ことによりＮ型多結晶シリコンパターン１５から不純物
を拡散させ、Ｎ＋型エミッタ領域１６を形成する（第７
図々示）。(7) Next, after depositing a polycrystalline silicon film on the entire surface, an acceleration energy of 40 to 50% is applied to the polycrystalline silicon film.
keV, dose 1101 S ~ 101 ”/cIi
Phosphorus or arsenic, or both phosphorus and arsenic, are ion-implanted under these conditions. Next, after patterning this polycrystalline silicon bulge to form an N-type polycrystalline silicon pattern 15, impurities are diffused from the N-type polycrystalline silicon pattern 15 by heat treatment at 800 to 900°C for several tens of minutes. to form an N+ type emitter region 16 (seventh
(Illustrated).

（８）　　次に、ＣＶＤ−８ｉ○２膜８の所定位置を選
択的にエツチングしてコンタクトホールを加工した後、
全面に配線金属層を堆積し、これをパターンニングして
エミッタ電極１７、ベース電極１８およびコレクタ電極
１９を形成する（第８図々示）。続いて、全面にパッシ
ベーション膜を堆積し、表面安定化等の最終処理を施し
て目的のバイポーラ型半導体装置を得る。(8) Next, after selectively etching a predetermined position of the CVD-8i○2 film 8 to form a contact hole,
A wiring metal layer is deposited over the entire surface and patterned to form an emitter electrode 17, a base electrode 18, and a collector electrode 19 (as shown in FIG. 8). Subsequently, a passivation film is deposited on the entire surface, and final processing such as surface stabilization is performed to obtain the desired bipolar semiconductor device.

上記実施例によれば、既述したように外部ベース領域１
２と活性ベース領域１３とが短絡しないでオーブン状態
になる危具がない。しかも、Ｍ　０８１２Ｍ１７と多結
晶シリコン１１６とのエツチングレートが異なるためエ
ツチング終了時の判定が容易で、工程管理上も有利であ
る。また、ベース取出し電極１ｏを多結晶シリコン膜６
と高温熱処理に耐える〜Ｉｏｓ　１２１１７どの積層膜
で構成したため、抵抗率の低い〜１０３ｉ２膜７の寄与
により取出し電極１０の層抵抗を低減することができる
。According to the above embodiment, as described above, the external base region 1
2 and the active base region 13 are not short-circuited and there is no danger of an oven condition. Furthermore, since the etching rates of M0812M17 and polycrystalline silicon 116 are different, it is easy to determine when etching has finished, which is advantageous in terms of process control. In addition, the base lead-out electrode 1o is formed using a polycrystalline silicon film 6.
Since it is constructed with a laminated film of Ios 12117 which can withstand high temperature heat treatment, the layer resistance of the extraction electrode 10 can be reduced due to the contribution of the Ios 103i2 film 7, which has low resistivity.

例えば、多結晶シリコン膜６の厚さを５００人とし、〜
１Ｏ８ｉ２膜７の膜厚を３０００人をした場合、層抵抗
は３〜４Ω／口の値となり、多結晶シリコン膜のみで構
成された従来の取出し電極の約１／′５０〜１／２００
とすることができる。For example, if the thickness of the polycrystalline silicon film 6 is 500,
If the thickness of the 1O8i2 film 7 is 3000, the layer resistance will be 3 to 4 Ω/mouth, which is about 1/'50 to 1/200 of the conventional lead-out electrode made of only a polycrystalline silicon film.
It can be done.

なお、上記の実施例では活性ベース領［１３の形成に際
し、多結晶シリコン躾６の露出部分を酸化して形成した
酸化膜１１を通してボロンをイオン注入したが、酸化１
１１１をフッ化アンモン等のエツチングにより一旦除去
してエピタキシャル層表面を露出し、再度その表面を酸
化して形成した再酸化膜を通してボロンのイオン注入を
行なってもよい。この場合、再酸化膜は膜厚が均一にな
るためボロンが均一にドープされる効果が得られる。In the above embodiment, when forming the active base region 13, boron ions were implanted through the oxide film 11 formed by oxidizing the exposed portion of the polycrystalline silicon layer 6.
111 may be removed by etching with ammonium fluoride or the like to expose the surface of the epitaxial layer, and boron ions may be implanted through the re-oxidized film formed by oxidizing the surface again. In this case, since the re-oxidized film has a uniform thickness, the effect of uniform boron doping can be obtained.

また、上記の実施例では不純物を含まないＭ　０８ｉ２
膜７を形成した後にイオン注入により該ＭＯＳｉ２膜７
にボロンを添加したが、予めＰ型不純物をドープしたＭ
Ｏ８ｉｚｌを堆積することも可能である。Moreover, in the above example, M 08i2 containing no impurities
After forming the film 7, the MOSi2 film 7 is removed by ion implantation.
Boron was added to M, but M was doped with P-type impurities in advance.
It is also possible to deposit O8izl.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明によれば全体的なベース抵
抗ｒ　ｂｂ’　を低減して高速動作特性および高周波特
性に優れたバイポーラ型半導体装置を製造することがで
き、且つ外部ペース領域と活性ベース頭載とが短絡しな
くなる事態を回避できる等、顕著な効果が得られるもの
である。As described in detail above, according to the present invention, it is possible to manufacture a bipolar semiconductor device with excellent high-speed operation characteristics and high-frequency characteristics by reducing the overall base resistance r bb'. This provides remarkable effects such as avoiding the situation where the base head is no longer short-circuited.

【図面の簡単な説明】 第１図〜第８図は本発明の一実施例になるバイポーラ型
半導体装置の製造方法を工程を追って説明するための断
面図、第９図はＣｌ２１０２を反応ガスとしたＲＩＥに
よるＭＯＳｉ２膜と多結晶シリコン層のエツチングレー
トを示すＩｉ１図、第１０図〜第１２図は従来の製造方
法における問題点を説明するための断面図である。 １・・・Ｐ型シリコン基板、２・−・Ｎ“型埋込領域、
３・・・Ｎ型エピタキシャル層、４・・・フィールド酸
化膜、５・・・Ｎ＋型コレクタコンタクトＭｌａ、６・
・・多結晶シリコン層、７・・・ＭｏＳｉ２膜、８・・
・ＣＶＤ−８１０２躾、９・・・レジストパターン、１
０ベース取出し電極、１１・・・熱醒化躾、１２・・・
外部ペース領域、１３・・・活性ベースｖＡ域、１４．
１４’　・・・ＣＶＤ−８ｉ○２膜、１５・・・多結晶
シリコン膜パターン、１６・・・Ｎ＋型エミッタ領域、
１７・・・エミッタＮ陽、１８・・・ベース電極、１９
・・・コレクタ電極[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 to 8 are cross-sectional views for explaining step by step a method for manufacturing a bipolar semiconductor device according to an embodiment of the present invention, and FIG. FIG. 1i1 and FIGS. 10 to 12 showing the etching rates of the MOSi2 film and the polycrystalline silicon layer by RIE are cross-sectional views for explaining problems in the conventional manufacturing method. 1...P type silicon substrate, 2...N" type buried region,
3... N type epitaxial layer, 4... Field oxide film, 5... N+ type collector contact Mla, 6...
...Polycrystalline silicon layer, 7...MoSi2 film, 8...
・CVD-8102 training, 9...Resist pattern, 1
0 base extraction electrode, 11...heat awakening discipline, 12...
External pace area, 13... active base vA area, 14.
14'...CVD-8i○2 film, 15...Polycrystalline silicon film pattern, 16...N+ type emitter region,
17... Emitter N positive, 18... Base electrode, 19
...Collector electrode

Claims (2)

【特許請求の範囲】[Claims] （１）第一導電型半導体層の一部上に非単結晶シリコン
膜および金属シリサイド膜の積層膜パターンを形成する
工程と、この積層膜パターンに第二導電型不純物をドー
プする工程と、前記積層膜パターンの一部分において、
金属シリサイドに対し選択性を有するエッチング法によ
り前記金属シリサイド膜のみをエッチング除去し、当該
部分において前記非単結晶シリコン膜を露出させる工程
と、この非単結晶シリコン膜の露出部分を酸化すること
により取出し電極を形成する工程と、熱処理により前記
取出し電極から前記第一導電型半導体層内に前記不純物
を拡散させて第二導電型高濃度不純物領域を形成する工
程と、前記非単結晶シリコン膜の酸化領域から前記第一
導電型半導体層に選択的に第二導電型不純物をドープす
ることにより、前記第二導電型高濃度不純物領域に接し
た第二導電型低濃度不純物領域を形成する工程と、前記
取出し電極を覆う絶縁膜を堆積した後、該絶縁膜に対し
て異方性エッチングを施すことにより前記取出し電極の
側壁に絶縁膜を残存させる工程と、前記第二導電型低濃
度不純物領域内に第一導電型高濃度不純物領域を形成す
る工程とを具備したことを特徴とするバイポーラ型半導
体装置の製造方法。(1) a step of forming a laminated film pattern of a non-single crystal silicon film and a metal silicide film on a part of the first conductivity type semiconductor layer; a step of doping the laminated film pattern with a second conductivity type impurity; In a part of the laminated film pattern,
A step of etching away only the metal silicide film using an etching method that is selective to metal silicide and exposing the non-single crystal silicon film in the relevant portion, and oxidizing the exposed portion of the non-single crystal silicon film. a step of forming an extraction electrode; a step of diffusing the impurity from the extraction electrode into the first conductivity type semiconductor layer by heat treatment to form a second conductivity type high concentration impurity region; forming a second conductivity type low concentration impurity region in contact with the second conductivity type high concentration impurity region by selectively doping a second conductivity type impurity from the oxidized region into the first conductivity type semiconductor layer; , after depositing an insulating film covering the extraction electrode, anisotropic etching is performed on the insulating film to leave the insulating film on the side wall of the extraction electrode; and the second conductivity type low concentration impurity region. 1. A method of manufacturing a bipolar semiconductor device, comprising: forming a first conductivity type high concentration impurity region within the bipolar semiconductor device. （２）前記非単結晶シリコン膜として多結晶シリコン膜
を、前記金属シリサイド膜としてモリブデンシリサイド
を夫々用いると共に、前記金属シリサイドに対し選択性
を有するエッチング法として塩素ガス及び酸素ガスの混
合ガスを反応ガスとした反応性イオンエッチングを用い
ることを特徴とする特許請求の範囲第１項記載のバイポ
ーラ型半導体装置の製造方法。(2) A polycrystalline silicon film is used as the non-single crystal silicon film, molybdenum silicide is used as the metal silicide film, and a mixed gas of chlorine gas and oxygen gas is used as an etching method that is selective to the metal silicide. A method for manufacturing a bipolar semiconductor device according to claim 1, characterized in that reactive ion etching using a gas is used.
JP59258520A 1984-07-31 1984-12-07 Manufacture of bipolar type semiconductor device Granted JPS61136266A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP59258520A JPS61136266A (en) 1984-12-07 1984-12-07 Manufacture of bipolar type semiconductor device
DE8585109543T DE3580206D1 (en) 1984-07-31 1985-07-30 BIPOLAR TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF.
EP19850109543 EP0170250B1 (en) 1984-07-31 1985-07-30 Bipolar transistor and method for producing the bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59258520A JPS61136266A (en) 1984-12-07 1984-12-07 Manufacture of bipolar type semiconductor device

Publications (2)

Publication Number Publication Date
JPS61136266A true JPS61136266A (en) 1986-06-24
JPH04590B2 JPH04590B2 (en) 1992-01-08

Family

ID=17321350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59258520A Granted JPS61136266A (en) 1984-07-31 1984-12-07 Manufacture of bipolar type semiconductor device

Country Status (1)

Country Link
JP (1) JPS61136266A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02256242A (en) * 1989-03-29 1990-10-17 Toshiba Corp Semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02256242A (en) * 1989-03-29 1990-10-17 Toshiba Corp Semiconductor device and manufacture thereof

Also Published As

Publication number Publication date
JPH04590B2 (en) 1992-01-08

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