JPS6113617A - Vapor growth method - Google Patents

Vapor growth method

Info

Publication number
JPS6113617A
JPS6113617A JP13396784A JP13396784A JPS6113617A JP S6113617 A JPS6113617 A JP S6113617A JP 13396784 A JP13396784 A JP 13396784A JP 13396784 A JP13396784 A JP 13396784A JP S6113617 A JPS6113617 A JP S6113617A
Authority
JP
Japan
Prior art keywords
temperature
susceptor
vapor phase
phase growth
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13396784A
Other languages
Japanese (ja)
Inventor
Nobuo Kashiwagi
伸夫 柏木
Shigeru Suzuki
繁 鈴木
Yoshihiro Miyanomae
宮之前 芳洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shibaura Machine Co Ltd
Original Assignee
Toshiba Machine Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Machine Co Ltd filed Critical Toshiba Machine Co Ltd
Priority to JP13396784A priority Critical patent/JPS6113617A/en
Publication of JPS6113617A publication Critical patent/JPS6113617A/en
Pending legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52Controlling or regulating the coating process

Landscapes

  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent generation of crystal dislocation in a semiconductor substrate by a method wherein the temperature of the circumferential part of the supporting member which is heated up to the highest temperature is detected, the temperature is properly controlled, the distribution of temperature is made uniform, and the temperature is raised at the prescribed temperature gradient. CONSTITUTION:First, a supporting member 4 is high frequency-heated by applying a current on a coil 8, and the above is controlled in such a manner that temperature is raised at the prescribed gradient, the temperature of the circumference 4 of the supporting member 4 is detected 10, it is compared with the set value, and a power source 9 is controlled and adjusted in accordance with the comparison value. According to this constitution, the temperature difference of the supporting member 4 when temperature is going up can be precisely controlled, there is no partial rise in temperature even when the speed of rise in temperature is increased to 3.5 deg.C/sec, a uniform heating can be performed and a slip, which is a crystal dislocation, is not generated on a substrate when a vapor growth method is performed subsequently.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体基板に気相を成長させる気相成長方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a vapor phase growth method for growing a vapor phase on a semiconductor substrate.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

一般に、半導体基板(以下、ウェハという)の表面に気
相を成長させる場合にはウェハをサセプタ上の載置溝内
に載置し、このサセプタを加熱することにより上記ウェ
ハを間接的に加熱してその表面に気相を成長させるよう
にしている。
Generally, when growing a vapor phase on the surface of a semiconductor substrate (hereinafter referred to as a wafer), the wafer is placed in a mounting groove on a susceptor, and the wafer is indirectly heated by heating the susceptor. A gas phase is grown on the surface.

しかしながら、従来においてはウェハとサセプタとの温
度差によシ、ウェハが熱変形してサセプタから均等に熱
を受けることができず、結晶転位であるスリップを発生
してしまう不都合があった。
However, in the past, due to the temperature difference between the wafer and the susceptor, the wafer was thermally deformed and could not receive heat evenly from the susceptor, resulting in the occurrence of slip, which is crystal dislocation.

そこで、ウェハがサセプタから均一に熱を受けることが
できるように、前記サセプタのウェハ載置溝を種々考案
したシ、あるいはつ翼ハの裏面をサセプタで加熱してそ
の表面を赤外線ランプで加熱するなどしてサセプタとウ
ェハ間の温度差を極力なくするような方策が考案されて
い石。
Therefore, in order to ensure that the wafer can receive heat uniformly from the susceptor, various methods have been devised for the wafer mounting groove of the susceptor, or the back surface of the blade is heated by the susceptor and the surface thereof is heated by an infrared lamp. Measures have been devised to minimize the temperature difference between the susceptor and the wafer.

しかしながら、前者の場合には溝加工の精度が高く要求
され、後者の場合にはウェハの表裏間の温度制御が複雑
で、十分々改善が行なえないのが実情であった。
However, in the former case, high precision in groove processing is required, and in the latter case, temperature control between the front and back sides of the wafer is complicated, and the reality is that sufficient improvement cannot be made.

本願発明者らは、半導体基板の結晶転位の発生原因につ
き鋭意研究の結果、半導体基板の平面内における温度分
布の差が大きく原因していることを突止めた。さらに、
前記温度分布の差は、支持体の加熱構造が気相成長時の
一定温度に維持されている状態において支持体の全面を
均一にするように配慮されているため、加熱昇温時のよ
うにより強力な熱エネルギを供給している状態では支持
体の温度分布が不均一になシ、支持体の外周側が高温に
なってしまうことに起因していることが判明した。
As a result of intensive research into the causes of crystal dislocations in semiconductor substrates, the inventors of the present application have found that the main cause is a large difference in temperature distribution within the plane of the semiconductor substrate. moreover,
The difference in temperature distribution is caused by the fact that the heating structure of the support is designed to make the entire surface of the support uniform when the temperature is maintained at a constant temperature during vapor phase growth. It has been found that this is due to the fact that the temperature distribution of the support becomes uneven when strong thermal energy is supplied, and the outer peripheral side of the support becomes high temperature.

また、結晶転位は気相成長の直前に行なう半導体基板表
面のエツチングの度合(エツチングレート)にも関係し
ていることが判明した。
It has also been found that crystal dislocations are also related to the degree of etching (etching rate) of the surface of the semiconductor substrate performed immediately before vapor phase growth.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に着目してなされたもので、その目的
とするところは、支持体の溝形状の影響を受けたり、あ
るいは、半導体基板を支持体の反対側から特別に加熱す
ることなく、半導体基板の結晶転位を防止できるように
した気相成長方法を提供しようとするものである。
The present invention was made in view of the above-mentioned circumstances, and its purpose is to avoid being affected by the groove shape of the support or to heat the semiconductor substrate from the opposite side of the support. The present invention aims to provide a vapor phase growth method that can prevent crystal dislocations in a semiconductor substrate.

〔発明の概要〕[Summary of the invention]

本発明は上記目的を達成するため、気相成長前の支持体
の加熱昇温を、最も高温になる支持体の外周部の温度を
検出し、その検出値に基いて制御するととにより、部分
的な過度の昇温を防止し、半導体基板平面内の温度分布
のバラツキをできるだけ小さく押えつつ所定の温度勾配
で昇温させ、半導体基板の結晶転位を防止するようにし
たものである。
In order to achieve the above-mentioned object, the present invention detects the temperature at the outer periphery of the support where the highest temperature is reached and controls the heating temperature of the support before vapor phase growth based on the detected value. This is to prevent crystal dislocation of the semiconductor substrate by preventing excessive temperature rise, and raising the temperature at a predetermined temperature gradient while suppressing variations in the temperature distribution within the plane of the semiconductor substrate as small as possible.

さらに、気相成長の直前に行なうエツチングのエツチン
グレートを0.06μm/分に定め、結晶転位のほとん
どないよシ良好力気相成長層を得られるようにしたもの
である。
Further, the etching rate of the etching performed immediately before vapor phase growth is set to 0.06 μm/min, so that a highly efficient vapor phase growth layer with almost no crystal dislocations can be obtained.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明を図面に示す一実施例を参照して説明する
。第1図は気相成長装置を示すもので、図中1は、ペー
スである。このベース1にはベルジャ2が載置され、反
応室3が構成されている。前記反応室3内には支持体と
してのサセプタ4が設けられ、このサセプタ4上の載置
(図示せず)には複数枚の半導体基板としてのウェハ5
が載置されている。上記サセプタ4は中空状の回転軸6
によって支持され、この回転軸6内には反応ガスの供給
管1が挿通されている。また、上記サセプタ4の下部に
はワークコイル8が対向して設けられ、このワークコイ
ル8は高周波電源9に電気的に接続されている。
Hereinafter, the present invention will be described with reference to an embodiment shown in the drawings. FIG. 1 shows a vapor phase growth apparatus, and 1 in the figure is a pace. A bell jar 2 is placed on this base 1, and a reaction chamber 3 is configured. A susceptor 4 as a support is provided in the reaction chamber 3, and a plurality of wafers 5 as semiconductor substrates are placed on the susceptor 4 (not shown).
is placed. The susceptor 4 has a hollow rotating shaft 6
A reactant gas supply pipe 1 is inserted into the rotary shaft 6 . Further, a work coil 8 is provided opposite to the lower part of the susceptor 4, and this work coil 8 is electrically connected to a high frequency power source 9.

前記サセプタ4の外周部は気相成長過程においては反応
ガスとの接触により内周部よりも大きく、冷却され易す
いので、サセプタ4とワークコイル8の間隔を調整する
ことにより外周部が強く加熱されてサセプタ4の全面が
均温化されるようになっている。また、上記ベルジャ2
の上方部にはフォトセンサ10が設けられ、この7オト
センサ10は上記サセプタ4の外周部の温度を検出する
ようになっている。このフォトセンサ10は比較器11
を介して上記高周波電源9に接続されている。前記比較
器11はフォトセンサ10から送られる出力値を設定値
Aと比較し、その比較値に応じて前記高周波電源9の出
力を制御するようになっている。
The outer periphery of the susceptor 4 is larger than the inner periphery due to contact with the reaction gas during the vapor phase growth process and is easily cooled. Therefore, by adjusting the distance between the susceptor 4 and the work coil 8, the outer periphery can be heated strongly. The entire surface of the susceptor 4 is made to have a uniform temperature. In addition, the above Belljar 2
A photosensor 10 is provided above the susceptor 4, and this photo sensor 10 detects the temperature of the outer peripheral portion of the susceptor 4. This photosensor 10 is a comparator 11
It is connected to the high frequency power supply 9 via. The comparator 11 compares the output value sent from the photosensor 10 with a set value A, and controls the output of the high frequency power source 9 according to the comparison value.

なお、図中12はベルジャ2に形成された監視窓12で
ある。
In addition, 12 in the figure is a monitoring window 12 formed in the bell jar 2.

しかして、ウェハ5・・・に気相成長させる場合には、
壕ず、ワークコイル8に高周波電源を印加してサセプタ
4を加熱し、ウェノ15・・・を間接的に所定温度まで
加熱する。との、サセプタ4およびウェハ5の昇温過程
では、これらをできるだけ早く所定の温度に加熱するた
め、気相成長時のように所定の温度に維持するのみのと
きに比べ高い電力を前記ワークコイル8に供給し、かつ
第2図に示す温度曲線Hの右上9部分H1に示すように
、所定の勾配で昇温するように制御する。
However, when performing vapor phase growth on wafer 5...
A high frequency power source is applied to the work coil 8 to heat the susceptor 4, thereby indirectly heating the welding material 15 to a predetermined temperature. In the process of raising the temperature of the susceptor 4 and wafer 5, in order to heat them to a predetermined temperature as quickly as possible, a higher power is applied to the work coil than when only maintaining the predetermined temperature during vapor phase growth. 8, and the temperature is controlled to rise at a predetermined gradient as shown in the upper right 9 portion H1 of the temperature curve H shown in FIG.

前記の昇温勾配の制御は、サセプタ4の外周部の温度が
フォトセンサ10によって検出され、その出力値が比較
器11に送られ、これにより出力値と時間に関係して変
化する設定値Aとが比較され、その比較値に応じて高周
波電源9の出力をPID調整することによシ行なわれる
The temperature increase gradient is controlled by detecting the temperature at the outer circumference of the susceptor 4 by a photosensor 10, and sending its output value to a comparator 11, which sets a set value A that changes in relation to the output value and time. This is performed by PID adjusting the output of the high frequency power supply 9 according to the comparison value.

ところで、前記のように気相成長時には、サセプタ4は
、供給管7から噴出される反応ガスによって外周側が最
も冷却されるため、ワークコイル8とサセプタ4の間隔
を調整することによシ、外周側がよシ強く加熱されるよ
うになっている。なお、この外周側を強く加熱する度合
は、サセプタ4の温度が所定の気相成長温度に達し、昇
温過程に比較して低い電力を供給している状態でサセプ
タ4の全面が均一になるように定められている。そこで
、ワークコイル8によシ強い電力が供給される昇温時に
は、外周側の方が内周側に比較して相当高温になってし
まうO このため、従来のように、サセプタ4の内周側の温度を
検出して昇温制御を行った場合には、外周側の温度は制
御されず、該外周側は所定の昇温勾配に沿った温度に達
しているにもかかわらず、それが検出されずによシ強い
電力が供給され、サセプタ4の半径方向により大きな温
度勾配を生じ、これがウェハ5・・・内に結晶転位を発
生させる原因となっていた。
By the way, as mentioned above, during vapor phase growth, the outer circumferential side of the susceptor 4 is cooled the most by the reaction gas ejected from the supply pipe 7, so by adjusting the distance between the work coil 8 and the susceptor 4, The sides are heated more strongly. Note that the degree to which the outer circumferential side is strongly heated is such that the temperature of the susceptor 4 reaches a predetermined vapor phase growth temperature and the entire surface of the susceptor 4 becomes uniform while supplying low power compared to the temperature raising process. It is defined as follows. Therefore, when the temperature rises when strong power is supplied to the work coil 8, the outer circumferential side becomes considerably hotter than the inner circumferential side. When temperature increase control is performed by detecting the temperature on the outer circumferential side, the temperature on the outer circumferential side is not controlled, and even though the outer circumferential side has reached a temperature along a predetermined temperature increase gradient, Stronger power was supplied without being detected, creating a larger temperature gradient in the radial direction of the susceptor 4, which caused crystal dislocations to occur within the wafers 5.

しかるに、本発明は、前記のように、最も高温となるサ
セプタ4の外周側の温度を検出し、これによシ昇温を制
御しているため、昇温時におけるサセプタ4の半径方向
の温度差を的確にコントロールすることができ、従来で
は、昇温速度を0.3℃/秒とされていたものを、3.
5℃/秒にまで高めても、その後行なわれた気相成長層
に結晶転位は認められなかった。
However, as described above, the present invention detects the temperature on the outer circumferential side of the susceptor 4, which is the highest temperature, and controls the temperature increase accordingly. The difference can be precisely controlled, and the heating rate was conventionally set at 0.3°C/sec.
Even when the temperature was increased to 5° C./sec, no crystal dislocation was observed in the vapor-phase grown layer that was subsequently grown.

なお、第2図は、本発明による場合のサセプタ4の温度
の推移を示すもので、昇温から恒温への移行が的確に行
なわれるが、従来は、サセプタ4の最も高温になる部分
の温度を検出していなかったため、検出値に遅くれが出
て、第3図に示すような、オーバーシュート0を生じ、
短時間に温度変化が起こるため、これもウェハ5・・・
に結晶転位を生ずる原因となっていた。
Note that FIG. 2 shows the transition of the temperature of the susceptor 4 according to the present invention, and the transition from temperature increase to constant temperature is accurately performed, but conventionally, the temperature of the highest temperature part of the susceptor 4 is was not detected, there was a delay in the detected value, resulting in an overshoot of 0 as shown in Figure 3.
Because temperature changes occur in a short period of time, this is also the case with wafer 5...
This was the cause of crystal dislocations.

また、気相成長に先だって気相成長層の品質をよくする
ためにウェハ5・・・が例えば1150℃の如き温度に
安定したところで、塩化水素によシウェハ5の表面をエ
ツチングするが、このエツチングの度合によってもウェ
ハ5・・・にスリップが発生する。一般的にはエツチン
グレート0.1μm/分位で行われるが、種々実験の結
果0.06μm/分以下にするとウェハ5・・・にスリ
ップがよシ完全に発生しないことが判明した。
Furthermore, in order to improve the quality of the vapor-phase grown layer prior to vapor-phase growth, the surface of the wafer 5 is etched with hydrogen chloride when the temperature of the wafer 5 has stabilized at, for example, 1150°C. Slip occurs on the wafers 5 depending on the degree of . Generally, etching is carried out at an etching rate of about 0.1 .mu.m/min, but as a result of various experiments, it has been found that when the etching rate is set to 0.06 .mu.m/min or less, no slip occurs on the wafers 5.

また前述した昇温制御およびエツチングの後に行なわれ
た気相成長層のS−R曲線は第4図に示す如くであシ、
ウェハ5・・・と気相成長層とでは抵抗分布が急峻で何
んら問題がないことが解る。
Further, the S-R curve of the vapor-phase grown layer after the temperature increase control and etching described above is as shown in FIG.
It can be seen that the resistance distribution of wafer 5 and the vapor growth layer is steep and there is no problem.

上述したように、サセプタ4の外周側の温度を検出して
昇温を制御することによりサセプタ4の温度をより均一
化して各ウェハ5・・・の全面をよシ均一に加熱でき、
これによシ、ウェハ5・・・の結晶転位の発生が押えら
れ、さらに気相成長に先だって行なうウェハ5・・・の
表面の塩化水素によるエツチングレートを0.06μm
/分以下にすればウェハ5・・・の結晶転位であるスリ
、プの発生はよシ確実に防止されることになる。
As described above, by detecting the temperature on the outer peripheral side of the susceptor 4 and controlling the temperature increase, the temperature of the susceptor 4 can be made more uniform, and the entire surface of each wafer 5 can be heated more uniformly.
This suppresses the occurrence of crystal dislocations in the wafer 5, and further reduces the etching rate by hydrogen chloride on the surface of the wafer 5 to 0.06 μm prior to vapor phase growth.
If the heating time is less than 1 minute, the occurrence of slips and drops, which are crystal dislocations of the wafer 5, can be more reliably prevented.

なお、本発明は上記一実施例に限られることなく、その
要旨の範囲内で種々変形実施可能なことは勿論である。
It should be noted that the present invention is not limited to the above-mentioned embodiment, and it goes without saying that various modifications can be made within the scope of the invention.

〔発明の効果〕〔Effect of the invention〕

以上、説明したように本発明によれば、半導体基板を均
一的に加熱でき、半導体基板に結晶転位であるスリップ
が発生することを確実に防止することができるという効
果を発する。
As described above, according to the present invention, it is possible to uniformly heat a semiconductor substrate, and it is possible to reliably prevent slips, which are crystal dislocations, from occurring in the semiconductor substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の一実施例を示すもので、第1図は気相成
長装置を示す概略的構成図、第2図および第3図はサセ
プタの昇温、冷却曲線を示すグラフ図、第4図は成長層
の評価を示すS−R曲線を示すグラフ図である。 4・・・サセプタ(支持体)、5・・・ウェハ(半導体
基板)。 出願人代理人 弁理士 鈴 江 武 彦時間 第3図 特開昭Gl−13617(5)
The drawings show one embodiment of the present invention, and FIG. 1 is a schematic configuration diagram showing a vapor phase growth apparatus, FIGS. 2 and 3 are graphs showing temperature rise and cooling curves of a susceptor, and FIG. The figure is a graph showing an SR curve showing evaluation of a grown layer. 4... Susceptor (support body), 5... Wafer (semiconductor substrate). Applicant's representative Patent attorney Takehiko Suzue Time Figure 3 JP-A-Sho Gl-13617 (5)

Claims (2)

【特許請求の範囲】[Claims] 1.加熱される支持体上に半導体基板を載置して、該半
導体基板表面に気相成長させるに際し、気相成長前の前
記支持体の加熱昇温を、該支持体の外周部の温度を検出
し、その検出値に基いて制御することを特徴とする気相
成長方法。
1. When a semiconductor substrate is placed on a heated support and vapor phase growth is performed on the surface of the semiconductor substrate, the heating temperature increase of the support before vapor phase growth is detected, and the temperature of the outer periphery of the support is detected. and control based on the detected value.
2.加熱される支持体上に半導体基板を載置して、該半
導体基板表面に気相成長させるに際し、気相成長前の前
記支持体の加熱昇温を、該支持体の外周部の温度を検出
し、その検出値に基いて制御し、該支持体が所定温度に
達したところで行なう半導体基板表面のエッチングを、
0.06μm/分以下のエッチングレートで行なった後
、気相成長を行なうことを特徴とする気相成長方法。
2. When a semiconductor substrate is placed on a heated support and vapor phase growth is performed on the surface of the semiconductor substrate, the heating temperature increase of the support before vapor phase growth is detected, and the temperature of the outer periphery of the support is detected. and controlling the etching of the semiconductor substrate surface when the support reaches a predetermined temperature based on the detected value.
A vapor phase growth method characterized by performing vapor phase growth after etching at an etching rate of 0.06 μm/min or less.
JP13396784A 1984-06-28 1984-06-28 Vapor growth method Pending JPS6113617A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13396784A JPS6113617A (en) 1984-06-28 1984-06-28 Vapor growth method

Applications Claiming Priority (1)

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JPS6113617A true JPS6113617A (en) 1986-01-21

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62281423A (en) * 1986-05-30 1987-12-07 Hitachi Ltd Method and device for dry etching

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62281423A (en) * 1986-05-30 1987-12-07 Hitachi Ltd Method and device for dry etching

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