JPS61134792A - Binary image trimming apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a binary image border creation device that eliminates overlapping of border portions and eliminates the need for memory of border characters in border character conversion.

[Conventional technology]

As a conventional binary image border creation device, for example, the one shown in Fig. 6 (
There is a system that converts pixels that are a certain distance apart from a series of black pixels as shown in (a) to black, and frames them as shown in FIG. 6 (El).

[Problems to be solved by the invention] However, in the conventional binary image border creation device, the sixth
There is a problem in that the border lines intersect and overlap as shown by the broken line in Figure (η), making it difficult to see. Additionally, if you want to eliminate this overlap, special processing must be performed. Furthermore, when creating a character with a border, if you adopt the method of preparing all the bit patterns of the border character, a huge amount of memory capacity will be required to store it, and the configuration will become complicated. This has the disadvantage of increasing costs.

[Means and effects for solving the problems] The present invention has been made in view of the above, and aims to eliminate overlapping of border portions and eliminate the need for memory for storing bit patterns of border characters. To provide a binary image edging creation device which executes processing to thicken an image to be edged, then extracts the outline of the thickened image, and superimposes this outline on the original image.

〔Example〕

Hereinafter, the binary image border creation device according to the present invention will be explained in detail.

FIG. 1 shows an embodiment of the present invention, which includes an image memory 1 that stores image data of a document or the like read by a reading device using a CCD, etc., and executes general control of the entire device and access to the image memory 1. System control circuit 10
, a temporary image memory 20 that stores data obtained by thickening image data, and a system control circuit 1.
A thickening processing circuit 30 executes processing to thicken the pixels of data read out from the image memory 1 under the control of 0, and a contour extraction circuit 30 reads out the thickened data from the circuit 30 and extracts only its contour. It is composed of a circuit 40 and a superposition circuit 50 that superimposes the contour data extracted by the circuit 40 and the image data stored in the image memory 1 and then stores the resultant data in the image memory 1.

In the above configuration, dot patterns such as characters are stored in the image memory 1, and the thickening circuit 30 reads image data from the image memory 1 according to instructions from the system control circuit 10, and performs thickening processing on this data. The data subjected to thickening processing by the thickening processing circuit 30 is stored in the temporary image memory 20. Next, the thick processed data is read out from the temporary image memory 20 by the contour extraction circuit 40, and the contour of the thick processed data is extracted. The extracted data is sent to a superposition circuit 50, where it is superimposed on the original image data stored in the image memory 1. 1 This superimposed image data is stored in the image memory 1.

FIG. 2 is an explanatory diagram showing the data processing process shown in FIG. 1 using the alphabet "A" as an example.

Figure (a) is the original video stored in the image memory 1,
Process this to make it thicker to obtain figure (b). Figure (c) is obtained by further performing contour extraction. Figure (=) is a border-processed figure obtained by combining Figure (A) and Figure (C) by the superposition circuit 50.

FIG. 3 shows details of the thick processing circuit 30, including a parallel-to-serial conversion register 31 that stores data from the image memory 1 and converts it into a serial signal, and a 1-bit conversion register 31 that stores data from the image memory 1 and converts it into a serial signal. a shift control circuit 32 that transfers data one by one; a parallel shifter 33 that stores several words of data received from the circuit 32 and shifts several bits of black signal at a predetermined timing in response to input "1"data; A temporary register 34 that stores output data of an OR circuit 35 (described later), an OR circuit 35 that ORs the output data of the temporary register 34 and the output data of the parallel shifter 33, and one word output from the temporary register 34. Thick processing data for one note and parallel shifters 360 to 364 described later
An OR circuit 37 which takes a logical sum with one word of
The output data of the circuit 37 is stored in the temporary image memory 2.
It is composed of parallel shifters 360 to 364 that transfer data to zero.

In the above configuration, the thick processing circuit 30 converts one black dot into a black matrix of 5×5 dots, and one dot of this outline is extracted by the outline extraction circuit 40. In other words, a border image is one in which a line drawing with a width of one dot is formed two dots apart around the original image.

One word from the image memory l is stored in the parallel-to-serial conversion register 31, and in synchronization with the clock, the register 31 supplies one bit at a time to the shift control circuit 32 together with the clock. In the shift control circuit 32, the register 31
When a "1" level signal is applied, a timing signal to shift the parallel shifter 33 is generated, and the parallel shifter 33 is controlled by counting clocks and setting the number of shifts. The parallel shifter 33 has a length of 4 words, is shifted to the left, and is always set to black (level "1") in the topmost word.
These 5 bits are shifted to the left in accordance with the bit whose source has a "1" level signal. That is, within this parallel shifter 33, horizontal thickening processing for one bit is performed. Note that the lower three words in the parallel shifter 33 must be cleared to 0 before the shift process. After being shifted by the parallel shifter 33, the lower three words are supplied to the OR circuit 35 together with 414@ of the temporary register 34, and after performing a logical sum, they are stored in the temporary register 34 again. The temporary register 34 is a temporary register for 3 words, and is cleared when 1 word is stored from the image memory l into the parallel/serial conversion register 31, and processed by the OR circuit 35. The results are stored. Furthermore, the temporary register 34 includes the register 31
When the thickening process is applied to the last bit in
The result of the horizontal thickening process for one word is stored.

Parallel shifters 360-364 are each three words long and shift one word to the right.

For these, a shifter is input from the temporary register 20 (cleared to 0 in the initial state) so that the target word being processed at that time becomes the middle word of the shifter 362.
Five words are supplied to the lower words 360 to 364. Further, the parallel shifters 360 and 361 store two words located above the target word on the image, and the parallel shifters 363 and 364 store two words located below. Then, the output data of the temporary register 34, which is the thick processing result of each of the parallel shifters 360 to 364 and one word, is O.
The signals are supplied to the R circuit 37 and subjected to OR processing, and the respective processing results are stored again in each of the parallel shifters 360 to 364. That is, the parallel shifters 360 to 364 store the results of one word thickened in the vertical and horizontal directions.

At this point, the upper words of parallel shifters 360-364 are stored again in temporary image memory 20, and I21 minutes is shifted to the right. And temporary double image memory 20
5 to the lower word of parallel shifter 360-364
One word is replenished.

41st! 1 shows the details of the contour extraction circuit 40, which includes a parallel-to-serial conversion register 41 that reads out words from the temporary image memory 20, converts them into serial data, and outputs them.
42 and 43, 1-bit storage circuits 440 and 444 that store 1 bit output from each of the registers 41 and 43, and 1 bit storage circuits 440 and 444 that store 1 bit output from the parallel/serial conversion register 42 in 3 steps. NAND the memory circuits 441, 442 and 443 and the 1-bit memory circuits 440, 443 and 444.
An AND gate 44, an AND gate 45 that extracts the contour by ANDing the output of the NAND gate 44 and the output of the 1-bit storage circuit 442, and a superimposition circuit that converts the output data of the gate 45 into a parallel signal. 50, and a serial/parallel conversion register 46.

In the above configuration, the contour extraction algorithm is
The four dots above, below, left and right of the target dot are looked at, and if they are all black, it is determined that they are internal points, and these are rewritten to white as shown in FIG.

In this case, if even one of the four dots is white, no conversion processing is performed.

The image data thickened by the thickening circuit is transferred from the temporary image memory 20 to the parallel/serial conversion register 42, and the words located above and below the image sent to the register 42 are converted into parallel/serial converters. It is supplied to conversion registers 41 and 43. One bit from each of the registers 41 and 43 is manually inputted to each of the 1-bit storage circuits 440, 441 and 444, and the 1 bit output from the register 42 is stored in the 1-bit storage circuit B44.
1.442 and 443 are stored in three steps. When the target bit is stored in the 1-bit storage circuit 442, the timing is adjusted in the circuits 440 and 444 so that the bit is stored at the top and bottom of the image. . 1-bit storage circuit 440, 4
41. NAND gate 44 of 443 and 444
D, and this NAND output and] bit write circuit 442
The contour is extracted by ANDing with the output of ANr) gate 45. The contour extracted for each bit is stored in the serial/parallel conversion register 46.
The superimposed circuit 50 supplies serially converted data to
Output to. The superimposition circuit 50 matches the outline-extracted image and the seven dresses of the original image, and superimposes the two images. This superimposed image information, i.e.
The bordered image information is stored in the image memory 1.

In addition, in the above explanation, one dot is 5× in thick processing.
Although it is assumed that the matrix is converted into a 5-dot black matrix, it is also possible to convert this into a matrix of a different size or a shape other than a matrix, such as a rhombus or a circle.

Furthermore, when extracting the outline, four dots on the top, bottom, left and right sides were used as the criterion, but other than the four dots, for example, 8 bits may be used as the criterion.

Further, although the outline extracted line is assumed to have a width of one dot, it may be expressed with a width of two dots or more.

〔Effect of the invention〕

As explained above, according to the binary image border creation device of the present invention, the outline is extracted after the original image is thickened, and this is superimposed on the original image. Processing can be performed without distinguishing between
It is possible to prevent overlapping at the border portion. Furthermore, it is possible to eliminate the need for bit patterns for border characters.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
(), (0), (A), and (d) are explanatory diagrams showing the processing steps of the present invention, FIG. 3 is a detailed block diagram of the thick circuit 3o according to the present invention, and FIG. 4 is a contour according to the present invention. Extraction 1 Detailed block diagram of the circuit 40, Figure 5 is an explanatory diagram of contour extraction, Figure 6 ((), (n) is the conventional 2
(11! Explanatory diagram of image border creation. Explanation of symbols 1--Image memory, 10- System control circuit, 2
0- Temporary image memory, 30- Thick processing circuit,
40-contour extraction circuit, 5o-superposition circuit. Patent source: Fuji Xerox Co., Ltd. agent, patent attorney Shin Matsuhara, 2nd same village
Kiyoshi Dosage Dosei 1
) Tadashi Rikai Same as above Island
Jun - Same Suzuki
Figure 1 Figure 2 Figure 6 Figure 1 Ino C Rono Figure 3 Figure 4

Claims (1)

[Claims] In a binary image edging creation device that performs edging processing on binary image data, the binary image data is configured to convert one bit of black information into multiple bits to thicken a line or image. a thick processing circuit; and a contour extraction circuit that converts all points around a target pixel to white to form a contour when all points around a target pixel in the image processed by the thick processing circuit are black; A binary image border creation device, comprising a superimposition circuit that combines contour data output from the circuit with original image data.