JP2867663B2 - Line element direction extraction circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a line element direction extraction circuit, and more particularly to a line element direction extraction circuit used in an image processing apparatus that optically recognizes an object, a figure, a character, or the like.

2. Description of the Related Art Conventionally, extraction of line element direction features has been used as a basic procedure of image recognition. Many means have been devised as means for extracting the line element direction, such as a method using a mask such as a differential mask and a method using a tentacle. In addition, as a conventional technique, as a mask, Michio Yasuda, Hiromichi Fujisawa,
"Improvement of Correlation Method for Character Recognition" Transactions of the Institute of Electronics, Information and Communication Engineers '79 /3Vol.J62-DNo.3PP217-224. Handwritten Kanji Recognition by Direction Contribution Density Feature "'83 / 6 Vol.
J66-D No. 6, PP722-729.

By the way, high-speed processing is required in real-time image processing, high-speed character recognition, and large image processing such as satellite images. However, the conventional technique described above has a disadvantage that the processing speed becomes extremely slow if the size of the visual field to be cut out is larger than 3 × 3 bits. Further, even in the method using the 3 × 3 mask, when the input image is not a binary image, there is a disadvantage that the processing amount is much larger than in the case of the binary image, and the processing speed is reduced.

On the other hand, in terms of directional element extraction performance, the method using a 5 × 5 mask having a wider field of view is clearly better than the method using a 3 × 3 mask. The use of a 5 × 5 mask is more resistant to fluctuations in the resolution of the scanner, noise, and the like. In particular, when the original image is subjected to enlargement processing, it is difficult to extract directional elements using the 3 × 3 mask. There is a disadvantage that there is.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a line element direction extracting circuit which has better extraction performance than a method using a 3 × 3 mask and can perform processing at a higher speed than a conventional method using a 5 × 5 mask.

Configuration of the Invention A line element direction extraction circuit according to the present invention is a 3 ×
Means for specifying a first specific pixel group consisting of nine pixels of a binary two-dimensional image using a three-bit mask; and a method for specifying the specific pixel group from each of the specified first specific pixel groups A first directional element allocating means for allocating the directional element of the first specific pixel group and nine pixels each having a central pixel of eight pixels excluding the central part of the first specific pixel group. Means for specifying a second to a ninth specific pixel group, and a second directional element allocation for allocating, for each of the second to the ninth pixel groups, a directional element of the specific pixel group from each of the pixel groups constituting them Means, and means for determining a directional feature of the first specific pixel group from directional elements assigned to the first to ninth specific pixel groups.

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a line element direction extracting circuit according to the present invention.

In the figure, a line element direction extraction circuit according to an embodiment of the present invention performs a 3 × 3 bit mask operation on an input image 11 by two.
It is configured to perform stepwise, has better extraction performance than the method using a 3 × 3 bit mask once, and can obtain the directional image 71 faster than the method using a 5 × 5 bit mask. That is.

In this case, the first line element direction extraction is performed by a 3 × 3 mask operation unit.
The second line element direction extraction is realized by the feature extraction unit 41, the 3 × 3 mask operation unit 21, and the ROMs 52 to 67.
This is realized by any one of the following. Also, the image buffer
Reference numeral 51 stores the extraction result in the line element direction. Furthermore, the control unit 101 controls each of the above units.

In the following description, when performing 16-direction element extraction,
That is, as shown in FIG. 3 (b), if a line portion is defined in the direction of the arrow and a line portion is defined on the right side and an edge for viewing the background is defined on the left side, the pixel of interest becomes An example will be described in which corresponding values 0 to f are extracted as direction elements depending on which of the arrows corresponds.

When the input image 11, which is a binary two-dimensional image, is specified by a unit (not shown) in a unit of 3 × 3 bits and input to the arithmetic unit 21, the control unit 101 selects the ROM 31. The 3 × 3 mask operation unit 21 gives an array of nine 3 × 3 bits “1” or “0” to the ROM 31 as an address.

In this ROM 31, 511 kinds of directional element values (512-1 = 511 in order to remove all 1s) corresponding to 0 to 1FE [H] by a combination of an array of 9 bits are previously stored in 16 bits. , And the value of the direction element corresponding to the array of nine bits is read from the ROM 31. For example, if an arrangement of nine bits constitutes a horizontal line element whose upper part is a background, FIG.
"0" in it will be extracted as the value of the direction element,
Only the least significant bit of the 16 bits is “1”, and the other 15 bits are “0”.

The specification of a 3 × 3 bit mask unit by means not shown is performed on the entire input image 11 so as to shift the mask. That is, (a) to (h) of FIG.
As shown in Figure 1, one of the three
Around the array of × 3 bits (broken line portion), another 3 × 3 bits (solid line portion) consisting of 9 bits each having 8 bits excluding the center bit as the center bit (shaded portion)
Are present in duplicate. Since the value of the direction element has been extracted by the 3 × 3 mask operation unit 21 and the ROM 31 also for these eight surrounding 3 × 3 bit arrays, the values of the surrounding direction elements are also taken into account in the second stage. The method of the present invention is to perform line element direction extraction by expanding the field of view to 5 × 5 bits as shown in FIG. 2 (A) by mask processing.

As shown in FIG. 4, the 3 × 3 mask calculation unit 21 includes an input buffer 211 that temporarily holds a total of 9 bits of the extracted 3 × 3, and a 3 × 3 mask held in the input buffer 211.
A determination unit 212 that determines whether the bit value is 1FF [H], that is, whether it is all 1; an output buffer 214 that stores the value of the directional element from the ROM 31 described above; and a value held in the output buffer 214 is cleared to 0 And clear means 213 to be performed.

Each bit of the input buffer 211 shown in the figure corresponds to the pixels at the positions 0 to 8 in FIG. 5, and is 9 bits in total. That is, as described above, the value of the direction element corresponding to these 9-bit values is read from the ROM 31 and held in the output buffer 214.

That is, the value held in the input buffer 211 is
, And the 16-bit data described above is held in the output buffer 214.

When the value of the 3 × 3 bits held in the input buffer 211 is all 1, the held value in the output buffer 214 is cleared to 0 by the clearing unit 213 without reading out to the ROM 31. This is because the reading to the ROM 31 is omitted and the processing speed is increased.

The values of the direction elements extracted by the 3 × 3 mask operation unit 21 and the ROM 31 are sequentially stored in an input buffer in the feature extraction unit 41. The feature extraction unit 41 extracts a line element direction feature in which the visual field is expanded to 5 × 5 bits based on the value of the extracted direction element.

FIG. 6 is a block diagram showing the internal configuration of the feature extraction 41. In the figure, the feature extracting unit is a 3 × 3 mask calculating unit 21.
A large-capacity input buffer 411 for holding a 16-bit value of the direction element extracted by the ROM 31, buffers 421 to 429 for sequentially holding 16-bit output data from the input buffer 411, and an AND circuit 431; Buffer 421-42
The OR circuit 451 performs a logical OR operation on the data held in 4 and 426 to 429 for each corresponding bit, and a right-hand OR circuit 452 for shifting the OR operation result by the OR circuit 451 to the right.

When the data held in the buffer 425 is all zero, the feature extracting unit outputs all 1 (1FF [H]) to the output buffer 4.
1FF setting means 433 for setting to 81, and buffers 421 to 424
And 426 to 429, a clear unit 441 for transmitting a clear signal for clearing a predetermined buffer, a control unit 471 for controlling the AND circuit 431 and the clear unit 441, and an input buffer 41.
Control unit 461 that controls reading from 1 to buffers 421 to 429
It is comprised including. The positions of the buffers 421 to 429 correspond to the positions of the 3 × 3 mask.

In this feature extraction unit, the directional elements stored in the input buffer 411 are fetched in 9 × 16 bits at a time, and the information of directional features in a wide field of view taking into account surrounding directional elements is output to the output buffer 48
The process of storing in 1 is performed.

However, since the values of the direction elements sequentially taken out from the input buffer in the feature extraction unit are each 16 bits, the image capacity is increased 16 times and the processing amount is increased.
Therefore, in this embodiment, a predetermined buffer is masked as described below to reduce the processing amount.

In other words, as a result of the directional element being assigned to the pixel at the center of the 3 × 3 mask, the position in the mask that is necessarily noticed is limited. Further, it is not conceivable that the direction element largely changes depending on the relationship of the change rate of the direction element, so that the direction element to be noted can be limited.

For example, when the pixel at the center is in the horizontal direction as shown in FIG. 7 (a), 3 × 3 bits always correspond to any of FIGS. 7 (b) to (d). for that reason,
As long as the pixel at the center is in the horizontal direction (direction element "0"),
It is sufficient to pay attention to the direction element at any position of the pair of ○, the pair of ☆, and the pair of の in FIG. 7A, and it is not necessary to pay attention to the pixel and the pixel in FIG. This is because the directional elements of each pair are assigned directional elements in consideration of surrounding pixels, and if one focuses on any of them, the field of view is expanded to 5 × 5.

Here, referring again to FIG. 3, when the pixel at the center is in the horizontal direction, that is, “0”, the directional elements that can occur in each of the surrounding pixels due to the continuity of the image are: There are nine types, "c" to "f" and "0" to "4". Therefore, if the direction element of the pixel at the center is determined, the other 7 bits of the direction element expressed by 16 bits become unnecessary,
With the remaining 9 bits, information with a wide field of view can be stored.

Returning to FIG. 6, the direction element of 16 bits per pixel output from the mask operation unit and stored in the input buffer 411 is 3
The data is stored in buffers 421 to 429 corresponding to each position of the × 3 mask. In this storage state, the bit corresponding to the directional element of interest is sequentially extracted by the AND circuit 431 from the buffer 425 corresponding to the central portion.

The bit extraction mask (not shown) in the AND circuit 431 has an initial value of “1”, and performs a left-justification operation each time a signal is received from the control unit 471. The bit corresponding to the notable directional element is extracted by ANDing the bit extraction mask to be left-justified and the value of the buffer 425.

That is, since the initial value of the bit extraction mask is "1", the 0th bit, that is, the value of the bit corresponding to the horizontal direction is extracted first, and the 0th bit to the fth bit are sequentially extracted by the left-justification operation. Because

As a result of extracting the 0th bit to the fth bit, there is no directional element to be noticed at the center, that is, the buffer 425
Is “0”, it is determined that the edge is not an edge in the clearing unit 213 in the 3 × 3 mask calculation unit 21 as described above, so that the 1FF setting unit 4
33 sets 1FF [H], that is, all 1s, and shifts to the next processing. The determination unit 432 determines whether the value of the buffer 425 is “0”.

On the other hand, when a notable directional element is obtained, that is, when any bit of the buffer 425 is “1”, the determination unit 432 activates the clear unit 441. The clearing means 441 performs a mask process on the directional element of the portion that does not need to be noted, and clears a predetermined buffer. For example, when attention is paid to the 0th bit of the buffer 425 (when attention is paid in the horizontal direction), the positions of and in FIG.
clear. The other buffers remain as they are.

The clearing means 441 has a 16-byte ROM (not shown) therein, and each time a signal comes from the control unit 471, that is, every time a 0th to fth bit is extracted from the buffer 425, a mask corresponding to that bit is read out. From the ROM,
Set to corresponding bits of buffers 421-424 and 426-429.

When the AND condition in the AND circuit 431 is satisfied,
The OR circuit 451 performs a logical OR operation for each corresponding bit for a total of eight buffers, ie, the buffers 421 to 424 and 426 to 429 to which the mask has been applied. In general, since the line element direction does not change rapidly, the OR result for each corresponding bit is 16
Of the bits, only one bit or two bits becomes “1”, and three bits at most become “1”.

Of the 16 bits of the OR result, only the necessary 9 bits are extracted and stored as described above, so that the necessary 9 bits are shifted to the right in the right-justification OR circuit 452. The right offset amount also works in conjunction with the AND circuit 431, and is determined according to the bit position when the AND condition is satisfied, and is performed such that the 3 × 3 central portion is located at the fifth bit from the right. For example, when paying attention to the 0th bit of the buffer 425, the right offset amount is “12”.

When the required 9 bits are extracted by the right-hand OR circuit 452, it is written into the output buffer 481. In this manner, when attention is paid to the 0th bit to the fth bit of the buffer 425 in sequence, every time the line element direction is stored in the buffers 421 to 429, 9 bits are stored.
× 16 bits of information will be obtained. Buffer 421
When the information of 9 × 16 bits is obtained for the line element directions stored in .about.429, the processing shifts to the next processing.

Returning to FIG. 1, when all the processes in the feature extraction unit 41 are completed, the second line element direction in which the field of view is expanded to 5 × 5 bits by one of the 3 × 3 mask calculation unit 21 and the ROMs 52 to 67 An extraction is performed. In this case, the control unit 101 selects any one of the ROMs 52 to 67 according to the directional features obtained by the above-described processing.

Here, the directional features obtained by the above processing are 3
This is 9-bit information including the surrounding directional features of the 9 bits of 3 and is set in the input buffer 211 in the 3x3 mask operation unit 21. That is, the control unit 101 selects one of the ROMs 52 to 67 based on the 9-bit information.

Referring again to FIG. 4, the 9-bit information set in the input buffer 211 allows any one of the ROMs 52 to 67 to operate.
First, 16-bit information is output and held in the output buffer 214. This 16-bit information indicates one of the directions in FIG. 3 (a).

At this time, the direction feature is all 1, that is, 3 × 3 = 9.
If all bits are “1”, 1F in the feature extraction unit 41
The 1FF [H] all 1 is set by the F setting means 433. In this case, the held value of the output buffer 214 is cleared to 0 by the clearing unit 213 as described above.

Returning to FIG. 1, the values held in the output buffer 214 in the 3 × 3 mask calculation unit 21 are sequentially accumulated in the image buffer 51 by an arbitration circuit (not shown). The stored information is logically ORed for each corresponding bit by an OR circuit (not shown) in the image buffer 51 every 16 × 16 bits, and finally becomes 16-bit information for one pixel. This 16-bit information is obtained for all pixels, and is output as the direction image 71.

As described above, according to the present invention, the line element direction extraction is performed twice by a simple binary 3 × 3 mask processing, whereby
It is said that stable directional element extraction close to a × 5 mask can be performed faster than performing a 5 × 5 mask, and directional feature extraction in real-time image processing, large image processing, and high-speed character recognition can be realized with higher performance than before. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a line element direction extracting circuit according to an embodiment of the present invention, FIG. 2 is a schematic view showing an enlargement of a visual field by superimposing 3 × 3 masks, and FIG. FIG. 4 is a block diagram showing an internal configuration of a 3 × 3 mask operation unit, FIG. 5 is a bit correspondence diagram between a 3 × 3 mask and an input buffer in FIG. 4, and FIG. FIG. 7 is a block diagram showing the internal configuration of the feature extracting unit, and FIG. 7 is a schematic diagram showing the bit position relationship at the time of extracting the directional characteristics. Description of Signs of Main Parts 21... 3 × 3 Mask Calculation Unit 31, 52 to 67... ROM 41... Feature Extraction Unit 51.

Claims (1)

(57) [Claims] 1. A means for specifying a first specific pixel group consisting of nine pixels in a binary two-dimensional image using a 3 × 3 bit mask for specifying a pixel, and the first specified pixel group First direction element allocating means for allocating a direction element of the specific pixel group from each pixel of the specific pixel group, and eight pixels excluding the allocated directional element and the central part of the first specific pixel group, respectively. Means for specifying a second to a ninth specific pixel group consisting of nine pixels serving as a central pixel; and for each of the second to the ninth pixel groups, the specific pixel group Second direction element allocating means for allocating a direction element of
Means for determining a directional feature of the first specific pixel group from directional elements assigned to the first to ninth specific pixel groups.