JPS61132885A - Dc bias quantum interferometer - Google Patents

Dc bias quantum interferometer

Info

Publication number
JPS61132885A
JPS61132885A JP59254349A JP25434984A JPS61132885A JP S61132885 A JPS61132885 A JP S61132885A JP 59254349 A JP59254349 A JP 59254349A JP 25434984 A JP25434984 A JP 25434984A JP S61132885 A JPS61132885 A JP S61132885A
Authority
JP
Japan
Prior art keywords
inductance
branches
magnetic field
bias
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59254349A
Other languages
Japanese (ja)
Inventor
Kazunori Miyahara
一紀 宮原
Kenichi Kuroda
研一 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP59254349A priority Critical patent/JPS61132885A/en
Publication of JPS61132885A publication Critical patent/JPS61132885A/en
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00Arrangements or instruments for measuring magnetic variables
    • G01R33/02Measuring direction or magnitude of magnetic fields or magnetic flux
    • G01R33/035Measuring direction or magnitude of magnetic fields or magnetic flux using superconductive devices
    • G01R33/0354SQUIDS
    • G01R33/0358SQUIDS coupling the flux to the SQUID

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Measuring Magnetic Variables (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To improve the magnetic field sensitivity by constituting a magnetic field detecting part by connecting one or more of the third inductances in parallel to the first and the second inductances, in a loop of superconductive strip lines which have been arranged in a shape of a plane without being overlapped to each other. CONSTITUTION:The first and the second branches B1, B2 are connected in parallel to a bias current line, the respective connecting points of industances 3, 4 and Josephson junctions 1, 2 are connected to a control current line 6, and one or more of magnetic field detecting use inductance branches 8 are connected as the third inductance to the inductances 3, 4. Also, the branches 8 are arranged in a shape of a plane and without being overlapped to each other, and in one or more of planes surrounded by this branches 8 in a loop of a super conductive strip line, there is no ground surface in an inductance loop 7 constituted of the branches B1, B2, and a ground surface is provided on other circuit part. In this way, the sensitivity for measuring a magnetic field can be improved in proportion to the area sum of the planes surrounded by the branches 8.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、微小磁場検出に用いる直流バイアス量子干渉
計に関するものである。更に特定すれば本発明はジ璽セ
フノン集積回路良作に用いられる薄膜技術で構成できる
直流バイアス量子干渉計に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a direct current bias quantum interferometer used for detecting minute magnetic fields. More particularly, the present invention relates to a DC-biased quantum interferometer that can be constructed using thin film technology used in the production of integrated circuits.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来の薄膜技術で製作されるこの種の直流バイアス量子
干渉計は、第2図く示すごとくジ盲セ7ソン接合1とイ
ンダクタンス3が直列に接続されて第1のブランチB1
が構成され、ジlセフソン接合2とインダクタンス4が
直列に接続されて第2のブランチB2が構成され、第I
および第2のブランチBl、B2が並列に接続されて、
バイアス電流線5に接続され、インダクタンス3および
4と磁気的に結合する制御電流線6が設けられた構造を
している。Hは被測定磁界である。該直流バイアス量子
干渉計のジ夏セフソンを流制御特性即ちジ1セ7ソン電
流対制御電流特性には、第3図に示されるととくの量子
干渉・臂ターフが現われる。この量子干渉パターンは、
第2図の第1のツ2ンチBノと第2のブランチB2で構
成されるインダクタンスループ7に磁束が鎖交すると制
御電流軸忙沿りて遷移する。との遷移量Aは、インダク
タンスルーデフに鎖交する磁束量に比例するので、イン
ダクタンスルーデフの囲む面積と遷移量ムからインダク
タンスループ゛7に鎖交する磁場の強さを求めることが
できる。
This type of DC-biased quantum interferometer fabricated using conventional thin film technology consists of a first branch B1 in which a blind junction 1 and an inductance 3 are connected in series, as shown in Figure 2.
is configured, the second branch B2 is configured by connecting the I-Sefson junction 2 and the inductance 4 in series, and the I-th
and second branches Bl, B2 are connected in parallel,
It has a structure in which a control current line 6 is connected to the bias current line 5 and magnetically coupled to the inductances 3 and 4. H is the magnetic field to be measured. In the current control characteristics of the DC bias quantum interferometer, that is, the current versus control current characteristics, a particular quantum interference/arm turf appears as shown in FIG. This quantum interference pattern is
When the magnetic flux interlinks with the inductance loop 7 composed of the first branch B and the second branch B2 in FIG. 2, the flux changes along the control current axis. Since the amount of transition A is proportional to the amount of magnetic flux interlinked with the inductance through differential, the strength of the magnetic field interlinked with the inductance loop 7 can be determined from the area surrounded by the inductance through differential and the amount of transition A.

この従来例の直流バイアス量子干渉計は、ジ1セフソン
集積回路の論理r−)としても用いられている。したが
ってこの直流バイアス量子干渉計の磁場a度は、ノ1セ
7ソン集積回路で用いられる論理ゲートと同程度である
。故にこの直流バイアス量子干渉計で、ジ箇セ7ソン集
積回路が誤動作を生じない様な低磁場環境を精度良く測
定するには磁場感度が不十分である。
This conventional DC-biased quantum interferometer is also used as a logic r-) of a Ji1 Cefson integrated circuit. Therefore, the magnetic field a degree of this DC bias quantum interferometer is comparable to that of a logic gate used in an integrated circuit. Therefore, the magnetic field sensitivity of this DC bias quantum interferometer is insufficient to accurately measure a low magnetic field environment that will not cause malfunction of the integrated circuit.

磁場感度を高くするためには、磁束が鎖交するインダク
タンスループ7の面積を大きくすれば良いのであるが、
その場合には、ループ1のループインダクタンスの値も
大きくなるため第3図に示す量子干渉パターンのモード
の重なりが多くなり、モードの区別がつけにくくなると
ともに、量子干渉/4ターンの遷移量もループインダク
タンスに逆比例して小さくなるので測定感度が高くなら
ない。この様に従来例の直流バイアス量子干渉計では磁
場感度なジ1セ7ソン論理f−)の磁場感度に較べて桁
違いに向上させることができないという重大な欠点を有
していた。
In order to increase the magnetic field sensitivity, it is sufficient to increase the area of the inductance loop 7 where the magnetic flux interlinks.
In that case, the value of the loop inductance of loop 1 will also increase, so the modes of the quantum interference pattern shown in Figure 3 will overlap more, making it difficult to distinguish between modes, and the quantum interference/four-turn transition amount will also increase. The measurement sensitivity does not increase because it decreases in inverse proportion to the loop inductance. As described above, the conventional DC bias quantum interferometer has a serious drawback in that it cannot improve the magnetic field sensitivity by an order of magnitude compared to the magnetic field sensitivity of the logic f-).

〔発明の目的〕[Purpose of the invention]

本発明はこの欠点を解決するために、ループインダクタ
ンスを並列に接続して、磁界が鎖交するインダクタンス
ループの囲む面積を増大させるとともに、実効ループイ
ンダクタンスをループインダクタンスの並列合成値とし
て低減化させることにより磁場感度を向上させたもので
、以下図面について詳細に説明する。
In order to solve this drawback, the present invention connects loop inductances in parallel to increase the area surrounded by the inductance loops interlinked with magnetic fields, and to reduce the effective loop inductance as a parallel composite value of the loop inductances. The magnetic field sensitivity has been improved by the following, and the drawings will be explained in detail below.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例は第1図に示す如く、第1のジ冒セ7
ソン接合1と、超伝導ストリップ線で構成された第1の
インダクタンス3が直列忙接続されて第1のブランチB
1が形成され、第2のジ首セフノン接合2と超伝導スト
リップ線で構成された第2のインダクタンス4が直列に
接続されて第2のブランチB2が形成され、第1および
第2のブランチBl、B2が並列に接続されて、バイア
ス電流を供給するz4イアス電流線5に接続され、イン
ダクタンス3とジョセフソン接合、lの&[点、インダ
クタンス4とゾ璽セフソン接合2の接続点にそれぞれ制
御電流を注入する制御電流線6が接続され、第3のイン
ダクタンスとして磁場検出用インダクタンスブランチ8
がインダクタンス3およびインダクタンス4に並列に少
なくとも1つ以上接続される。
One embodiment of the present invention is as shown in FIG.
A Son junction 1 and a first inductance 3 composed of a superconducting strip wire are connected in series to form a first branch B.
1 is formed, a second di-neck Cefnon junction 2 and a second inductance 4 made of a superconducting strip wire are connected in series to form a second branch B2, and the first and second branches Bl , B2 are connected in parallel to the z4 current line 5 which supplies the bias current, and the inductance 3 and the Josephson junction, the &[ point of l, and the connection point of the inductance 4 and the Josephson junction 2 respectively. A control current line 6 for injecting current is connected, and an inductance branch 8 for magnetic field detection is connected as a third inductance.
are connected in parallel to inductance 3 and inductance 4.

前記インダクタンスブランチ8は平面状に互いに重複す
ることなく並べられた超伝導ス) 17、f線のループ
によ多構成され、このインダクタンスブランチ8の囲む
少なくとも、1つ以上の平面のうち第1および第2のブ
ランチBl 、B2で構成されるインダクタンスループ
7に含まれる部分を除く部分の下側には接地面が無く、
他の回路部分の下側には接地面を設けた構造をしている
The inductance branch 8 is composed of multiple superconducting conductors (17) arranged in a plane without overlapping with each other, and has a plurality of loops of f-rays, and the inductance branch 8 surrounds at least one of the first and second planes. There is no ground plane on the lower side of the part other than the part included in the inductance loop 7 composed of the second branch Bl and B2,
It has a structure in which a ground plane is provided below the other circuit parts.

Fは超伝導体よシなる接地面の無い領域であシ、このよ
うに接地面の無い領域Fを設けるのは次の理由による。
F is a region without a ground plane, such as a superconductor, and the reason for providing such a region F without a ground plane is as follows.

即ち、もし、領域Fにも超伝導体よシなる接地面がある
と検出しようとする接地面に垂直な磁場が接地面で乱れ
てしまい、正確に磁場を検出することができないためで
ある。また、領域F以外の回路部分の下側には超伝導体
よシなる接地面を設けるのは、この部分に垂直方向に磁
場が通ると磁場の検出時に誤差が生じ名ため、領域F以
外の回路部分の下側には接地面を設けて、この接地面で
接地面に垂直方向に磁場が通るのを防止して磁場の検出
時に誤差が生じるのを防止するためである。
That is, if there is a ground plane such as a superconductor in region F, the magnetic field perpendicular to the ground plane to be detected will be disturbed by the ground plane, making it impossible to accurately detect the magnetic field. Also, the reason why a ground plane such as a superconductor is provided below the circuit parts other than area F is because if a magnetic field passes perpendicularly to this part, an error will occur when detecting the magnetic field. This is because a ground plane is provided below the circuit portion, and this ground plane prevents the magnetic field from passing in a direction perpendicular to the ground plane, thereby preventing errors from occurring when detecting the magnetic field.

本実施例の素子構造は、従来のジ1セ7ソン集積回路製
作に用いられている薄膜技術によシ製作可能であるので
、ジ曹セフソン集積回路のチ、f内にジ1セ7ソン集積
回路と同時に製作できるという大きな利点を有している
The element structure of this example can be manufactured using the thin film technology used in the production of conventional integrated circuits. It has the great advantage of being able to be manufactured simultaneously with integrated circuits.

本実施例によれば被測定磁界は複数個のインダクタンス
ブランチ8の囲む平面の総和に印加される量が磁束とし
て測定されるため、インダクタンスブランチ8の囲む平
面の面積和に比例して磁場測定感度が向上する。また本
実施例においては、量子干渉計のゾ璽セフンン電流制御
特性をきめるループインダクタンスの実効値は、インダ
クタンスブランチ8の並りリインダクタン、スとなるた
め、インダクタンスブランチ8の数を増大させても、ル
ープインダクタンスの実効値は増加しない。故にジlセ
7ソン電流制御特性のモードの重なシが増加することは
ないので、モードの判別がしK<くなることはなく、ま
た    1量子干渉ノーターンの遷移量も小さくなる
ことはない。したがりて本実施例によれば直流パイプス
量子干渉計の磁場感度を−)!セフンン論理r−トの磁
場感度に較べて桁違いに向上させることが可能となる。
According to this embodiment, since the magnetic field to be measured is measured as the magnetic flux, which is the amount applied to the sum of the planes surrounded by a plurality of inductance branches 8, the magnetic field measurement sensitivity is proportional to the sum of the areas of the planes surrounded by the inductance branches 8. will improve. In this embodiment, the effective value of the loop inductance that determines the current control characteristics of the quantum interferometer is equal to the inductance of the inductance branches 8, so even if the number of inductance branches 8 is increased, The effective value of the loop inductance does not increase. Therefore, the number of overlapping modes in the current control characteristics will not increase, so the mode discrimination will not become K<, and the amount of transition of one-quantum interference no-turn will not become smaller. . Therefore, according to this embodiment, the magnetic field sensitivity of the DC Pipes quantum interferometer is -)! It is possible to improve the magnetic field sensitivity by an order of magnitude compared to that of the standard logic circuit.

また本実施例では、制御電流線°6から、量子干渉計の
インダクタンスルーf7に第1および第2のインダクタ
ンスを介して直接制御電流を注入しているが、これは制
御電流線6とインダクタンスループ7との磁気結合定数
を実効的に11Cして、測定における不確定・9ラメー
タを少なくしたもので、第2図の従来例におけるように
インダクタンス3.4と制御電流線6とを磁気的に結合
して制御電流を供給する構造も可能であることは言うま
でもない。
Further, in this embodiment, the control current is directly injected from the control current line 6 to the inductance through f7 of the quantum interferometer via the first and second inductances, but this is because the control current line 6 and the inductance loop The magnetic coupling constant between the inductance 3.4 and the control current line 6 is effectively set to 11C to reduce the uncertainty and 9 ram in measurement, and the inductance 3.4 and the control current line 6 are magnetically connected as in the conventional example shown in Fig. 2. It goes without saying that a structure in which the control current is supplied by coupling is also possible.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本実施例によれば直流バイアス量
子干渉計の磁場測定感度を大幅に向上できるという利点
があるとともに、本実施例は、従来のジlセフソン集積
回路製作技術で製作可能な高感度磁界測定素子であるた
め、本素子をジ1セフンン集積回路チップ内にジ冒セ7
ソン集積回路と同時に製作すれば、ジ嘗セフソン集積回
路を動作させながらその磁場環境を測定できるという従
来の磁場測定素子では考えられなかった利用法が可能と
なる。
As explained above, this embodiment has the advantage that the magnetic field measurement sensitivity of the DC bias quantum interferometer can be significantly improved. Since it is a highly sensitive magnetic field measuring element, this element can be easily installed within an integrated circuit chip.
If manufactured at the same time as a Sefson integrated circuit, it becomes possible to use it in ways unimaginable with conventional magnetic field measuring elements, such as being able to measure the magnetic field environment of the Sefson integrated circuit while it is operating.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の構成図、第2図は従来の直
流バイアス量子干渉計の構成図、第3図は直流バイアス
量子干渉計のジョセフソン電流制御特性図である。 1.2・・・ジ冒セフソン接合、3.4・・・インダク
タンス、Bl、82・・・それぞれ第1および第2のブ
ランチ、5・・・バイアス電流線、6・・・制御電流線
、7・・・インダクタンスループ、8・・・磁場検出用
インダクタンスブランチ。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional DC bias quantum interferometer, and FIG. 3 is a Josephson current control characteristic diagram of the DC bias quantum interferometer. 1.2... Diverse Sefson junction, 3.4... Inductance, Bl, 82... First and second branches, respectively, 5... Bias current line, 6... Control current line, 7... Inductance loop, 8... Inductance branch for magnetic field detection.

Claims (2)

【特許請求の範囲】[Claims] (1)第1のジョセフソン接合と超伝導ストリップ線で
構成された第1のインダクタンスで第1のブランチが形
成され、第2のジョセフソン接合と超伝導ストリップ線
で構成された第2のインダクタンスで第2のブランチが
形成され、第1および第2のブランチが並列に接続され
て、バイアス電流線よりバイアス電流が供給され、第1
および第2のインダクタンスを介して直接制御電流が注
入されるかあるいは磁気的結合により制御電流が供給さ
れた直流バイアス量子干渉計において、平面状に互いに
重複することなく並べられた超伝導ストリップ線のルー
プにより構成された少なくとも1つ以上の第3のインダ
クタンスが第1あるいは第2のインダクタンスと並列に
接続されて磁場検出部が構成されたことを特徴とする直
流バイアス量子干渉計。
(1) A first branch is formed by a first inductance composed of a first Josephson junction and a superconducting strip line, and a second inductance is composed of a second Josephson junction and a superconducting strip line. A second branch is formed in the first branch, the first and second branches are connected in parallel, a bias current is supplied from the bias current line, and the first
and a direct current bias quantum interferometer in which a control current is directly injected through a second inductance or supplied by magnetic coupling, in which superconducting strip lines are arranged in a plane without overlapping each other. A direct current bias quantum interferometer, characterized in that a magnetic field detection section is constructed by connecting at least one third inductance formed by a loop in parallel with the first or second inductance.
(2)第1のジョセフソン接合と超伝導ストリップ線で
構成された第1のインダクタンスで第1のブランチが形
成され、第2のジョセフソン接合と超伝導ストリップ線
で構成された第2のインダクタンスで第2のブランチが
形成され、第1および第2のブランチが並列に接続され
て、バイアス電流線よりバイアス電流が供給され、第1
および第2のインダクタンスを介して直接制御電流が注
入されるかあるいは磁気的結合により制御電流が供給さ
れた直流バイアス量子干渉計において、平面状に互いに
重複することなく並べられた超伝導ストリップ線のルー
プにより構成された少なくとも1つ以上の第3のインダ
クタンスが第1あるいは第2のインダクタンスと並列に
接続されて磁場検出部が構成され、かつこの第3のイン
ダクタンスの囲む少なくとも1つ以上の平面のうち前記
第1および第2のブランチで構成されるインダクタンス
ループに含まれる部分を除く部分の下側には接地面がな
く、他の回路部分の下側には接地面を設けたことを特徴
とする直流バイアス量子干渉計。
(2) A first branch is formed by a first inductance composed of a first Josephson junction and a superconducting strip wire, and a second inductance is composed of a second Josephson junction and a superconducting strip wire. A second branch is formed in the first branch, the first and second branches are connected in parallel, a bias current is supplied from the bias current line, and the first
and a direct current bias quantum interferometer in which a control current is directly injected through a second inductance or supplied by magnetic coupling, in which superconducting strip lines are arranged in a plane without overlapping each other. At least one or more third inductances constituted by a loop are connected in parallel with the first or second inductance to constitute a magnetic field detection section, and at least one or more planes surrounded by this third inductance are connected in parallel with the first or second inductance. There is no ground plane below the portion of the circuit excluding the portion included in the inductance loop constituted by the first and second branches, and a ground plane is provided below the other circuit portions. DC bias quantum interferometer.
JP59254349A 1984-12-01 1984-12-01 Dc bias quantum interferometer Pending JPS61132885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59254349A JPS61132885A (en) 1984-12-01 1984-12-01 Dc bias quantum interferometer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59254349A JPS61132885A (en) 1984-12-01 1984-12-01 Dc bias quantum interferometer

Publications (1)

Publication Number Publication Date
JPS61132885A true JPS61132885A (en) 1986-06-20

Family

ID=17263755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59254349A Pending JPS61132885A (en) 1984-12-01 1984-12-01 Dc bias quantum interferometer

Country Status (1)

Country Link
JP (1) JPS61132885A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370089U (en) * 1986-10-28 1988-05-11
JPH0792247A (en) * 1993-09-22 1995-04-07 Chodendo Sensor Kenkyusho:Kk Squid magnetometer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57167691A (en) * 1981-03-31 1982-10-15 Fujitsu Ltd Josephson junction logistic gate
JPS5896786A (en) * 1981-12-04 1983-06-08 Yokogawa Hokushin Electric Corp Thin film rf squid

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57167691A (en) * 1981-03-31 1982-10-15 Fujitsu Ltd Josephson junction logistic gate
JPS5896786A (en) * 1981-12-04 1983-06-08 Yokogawa Hokushin Electric Corp Thin film rf squid

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370089U (en) * 1986-10-28 1988-05-11
JPH0792247A (en) * 1993-09-22 1995-04-07 Chodendo Sensor Kenkyusho:Kk Squid magnetometer

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