JPS61131906A - Power amplifier - Google Patents

Power amplifier

Info

Publication number
JPS61131906A
JPS61131906A JP59253520A JP25352084A JPS61131906A JP S61131906 A JPS61131906 A JP S61131906A JP 59253520 A JP59253520 A JP 59253520A JP 25352084 A JP25352084 A JP 25352084A JP S61131906 A JPS61131906 A JP S61131906A
Authority
JP
Japan
Prior art keywords
negative feedback
amplifier circuit
gain
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59253520A
Other languages
Japanese (ja)
Inventor
Fumiyuki Niwa
丹羽 史幸
Kenji Izumi
健二 泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC Corp
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC IC Microcomputer Systems Co Ltd filed Critical NEC Corp
Priority to JP59253520A priority Critical patent/JPS61131906A/en
Publication of JPS61131906A publication Critical patent/JPS61131906A/en
Pending legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)

Abstract

PURPOSE:To realize a low distortion factor and to decrease a DC voltage difference between outputs by placing a non-inverting negative feedback amplifier circuit to the 1st stage and inverting the phase by an inverting negative feedback amplifier circuit so as to decrease the variance in the voltage gain. CONSTITUTION:When a signal is inputted to an input terminal 115, a non-inverting negative feedback amplifier circuit 101 having a gain 0dB inputs a signal having the same amplitude and in phase with the input signal to a negative feedback circuit 103, from which a signal amplified by a factor of the gain is outputted to an output terminal 117. On the other hand, a signal inputted to an inverting negative feedback amplifier circuit 102 with gain 0dB via the circuit 101 becomes an inverted signal with the same amplitude as the input signal, amplified by a negative feedback circuit 104 and outputted to an output terminal 118. In this case, the gain of the circuits 101, 102 is the unity, the feedback rate is the unity and the voltage gain variation and distortion factor of each amplifier circuit are decreased to 1/(1+Avo) with respect to those at no feedback and then the circuit is stabilized, where Avo is the voltage gain. Further, the voltage gain variance is compressed to stabilize the DC voltage difference between output terminals thereby realizing a low distortion factor.

Description

【発明の詳細な説明】 (通常BTLと言い、以下この略号を使う)方式増幅回
路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION This invention relates to a BTL (usually referred to as BTL and this abbreviation will be used hereinafter) type amplifier circuit.

〔従来の技術〕[Conventional technology]

いわゆるBTL方式の増幅回路とは、2組の増幅器を用
い、それぞれの増幅器の出力における信号の位相が互に
逆になる様に駆動し、その出力熾子間に負荷を接続する
ことにより単体増幅器の2倍の出力電圧を負荷に供給で
きる嫌にし、負荷のインピーダンスが同じなら、単体増
幅器の4倍の電力信号を取り出すことができる様に構成
した増幅器のことである。
The so-called BTL type amplifier circuit uses two sets of amplifiers, drives the outputs of each amplifier so that the phases of the signals are opposite to each other, and connects a load between the output terminals to create a single amplifier. This is an amplifier configured so that it can supply twice the output voltage to the load, and if the impedance of the load is the same, it can extract four times the power signal of a single amplifier.

従来のBTL方式増幅回路の一例を示すと第2図の様な
回路構成となっている@ この回路は、エミッタが共通で定電流源11に接続され
たPNP)?ンジスタ1,2のコレクタに、それぞれ負
荷抵抗3,4を接続し、PNP)ランラスタ20ベース
に入力端子16を介して人力信号を加え、PNP)ラン
ジスタ1,2のコレクタをそれぞれ第1.第2の出力と
する差動構成の差動増幅器50と、Lの差動増幅器50
0第10出力を人力とし、帰還抵抗5,7およびコンデ
ンサ6を有する第10負帰還増幅回路13と、第2の出
力を人力とし、帰還抵抗8,10およびコンデンサ9を
有する第2の負帰還増幅回路14とで構成されている。
An example of a conventional BTL type amplifier circuit has a circuit configuration as shown in Fig. 2. This circuit has a common emitter connected to a constant current source 11 (PNP)? Load resistors 3 and 4 are connected to the collectors of transistors 1 and 2, respectively, and a human input signal is applied to the base of PNP) run raster 20 via the input terminal 16. A differential amplifier 50 with a differential configuration as a second output, and an L differential amplifier 50
A tenth negative feedback amplifier circuit 13 whose tenth output is human powered and has feedback resistors 5, 7 and a capacitor 6, and a second negative feedback circuit whose second output is human powered and has feedback resistors 8, 10 and a capacitor 9. It is composed of an amplifier circuit 14.

この回路は、入力端子16に信号が入力されると、差動
増幅器50o第1.第2の出力には、それぞれ逆位相の
信号が出力されその第1.第2の出力信号は、それぞれ
第1.第2の負帰還増幅回813.14にて増幅され、
出力端子18と出力端子19に、もそれぞれ逆位相の信
号が出力される。
In this circuit, when a signal is input to the input terminal 16, the first . Signals with opposite phases are output to the second outputs, respectively, and the first... The second output signals are respectively the first . Amplified by the second negative feedback amplification circuit 813.14,
Signals with opposite phases are also output to the output terminal 18 and the output terminal 19, respectively.

従って、出力亀子18.19間接続された負荷抵抗15
に単体増幅器の4倍の出力電力を得ることができる。
Therefore, the load resistor 15 connected between the output terminals 18 and 19
It is possible to obtain four times the output power of a single amplifier.

なお、コンデンサ6.9は、それぞれ第1.第2の負帰
還増幅回wr13.14に直流電圧利得をもたせないた
めのもので、定電流源11は、差動増幅器50を動作さ
せるためのものであプ、また、定電圧源12は、PNP
)ランジスタ1のペースをバイアスするためのものであ
る。
Note that the capacitors 6.9 and 1. This is to prevent the second negative feedback amplifier circuit wr13.14 from having a DC voltage gain, the constant current source 11 is for operating the differential amplifier 50, and the constant voltage source 12 is for PNP
) is for biasing the pace of transistor 1.

〔発明が解決するための手段〕[Means for the invention to solve the problem]

このBTL方式の増幅回路を用いた場合、初段の差動m
@器50には、帰還がかかつていないため、帰還による
圧縮効果がなく、この差動増幅器50におVlて、電圧
利得のバラツキが大きく、また、この差動増幅器50の
第1.第2の出力の直流電圧差が大きく、歪率におりて
も低歪率は望めない。つtシ、この差動増幅器50を用
いるpjk夛。
When using this BTL type amplifier circuit, the first stage differential m
In the differential amplifier 50, since there has never been feedback, there is no compression effect due to the feedback, and the voltage gain of the differential amplifier 50 has large variations in voltage gain. The DC voltage difference between the second outputs is large, and a low distortion rate cannot be expected even if the distortion rate is low. Then, a pjk system using this differential amplifier 50.

BTL方式の増幅回路としても電圧利得のノ(ラツキが
大きく、また、出力端子18.19間の[fi電圧差も
大きく、また、歪率においても限界が出てくる。
Even as a BTL type amplifier circuit, the voltage gain is large, the voltage difference between the output terminals 18 and 19 is large, and there is a limit to the distortion rate.

本発明の目的は、電圧利得のバラツキを小さくでき、ま
た、出力端子間の直R,電圧差も小さくでき、さらに、
低歪率を実現できるBTL方式増幅回路を提供すること
にある。
It is an object of the present invention to reduce variations in voltage gain, reduce direct R and voltage differences between output terminals, and further,
An object of the present invention is to provide a BTL type amplifier circuit that can realize a low distortion rate.

〔問題点を解決するための手段〕[Means for solving problems]

本発明によれば、入力信号受ける負帰還人力増幅器と、
負帰還人力増幅器の出力を増幅する第10負帰還型電力
増幅器と、負帰還入力増幅器の出力を受ける利得111
0反転塁負帰還増幅器と、反転製負帰還増幅回路器の出
力を増幅する第2の負帰還型電力増幅器と、第1および
f742の負帰還電力増幅器の出力端子間に接続された
負荷とを含む電力増幅器を得る。
According to the present invention, a negative feedback human power amplifier receiving an input signal;
a tenth negative feedback power amplifier that amplifies the output of the negative feedback human power amplifier; and a gain 111 that receives the output of the negative feedback input amplifier.
A zero inversion base negative feedback amplifier, a second negative feedback power amplifier that amplifies the output of the inversion negative feedback amplifier circuit, and a load connected between the output terminals of the first and f742 negative feedback power amplifiers. Get a power amplifier containing.

〔実施例〕〔Example〕

以下、本発明の具体的実施例を第1図を用いて説明する
Hereinafter, specific embodiments of the present invention will be described using FIG. 1.

入力端子115には、利得OdBの非反転型負帰還増幅
回路101が接続され、その出力には、帰還抵抗107
と109およびコンデンサ108を有した負帰還増幅回
路103と利得OdBの反転製負帰還増幅回路102を
介して、帰還抵抗110と112およびコンデンサ11
1を有する負帰還増幅回路104が接続される。負帰還
増幅回路103.104の出力端子117と118の両
熾に負荷抵抗114が接続される。負帰還増幅回路10
3.104は非反転製として構成されており、負帰還増
幅回路102は反転型として構成されているO このBTLm成された増幅回路は、入力端子115に信
号が人力されると、非反転型負帰還増幅回路101は、
利得Odeであるため、入力信号と同振幅で同相の信号
が負帰還増幅回路103に人力され、負帰還増幅回路1
03でその利得倍された信号が出力端子117に出力さ
れる。一方、非反転型負帰還増幅回路101を介して反
転型負帰還増幅回路102に人力された信号は反転型負
帰還増幅回路102の利得はOdBなので人力信号と同
振幅で逆相O信号となシ、負帰還増幅回路104で増−
され出力端子11Bに出力される。
A non-inverting negative feedback amplifier circuit 101 with a gain of OdB is connected to the input terminal 115, and a feedback resistor 107 is connected to the output of the non-inverting negative feedback amplifier circuit 101.
and 109 and a capacitor 108 and an inverted negative feedback amplifier circuit 102 with a gain of OdB, feedback resistors 110 and 112 and a capacitor 11
1 is connected to the negative feedback amplifier circuit 104. A load resistor 114 is connected to both output terminals 117 and 118 of the negative feedback amplifier circuits 103 and 104. Negative feedback amplifier circuit 10
3. 104 is configured as a non-inverting type, and the negative feedback amplifier circuit 102 is configured as an inverting type. The negative feedback amplifier circuit 101 is
Since the gain is Ode, a signal having the same amplitude and the same phase as the input signal is input to the negative feedback amplifier circuit 103, and the negative feedback amplifier circuit 1
The signal multiplied by the gain at 03 is output to the output terminal 117. On the other hand, since the gain of the inverting negative feedback amplifier circuit 102 is OdB, the signal input manually to the inverting negative feedback amplifier circuit 102 via the non-inverting negative feedback amplifier circuit 101 becomes an O signal with the same amplitude and opposite phase as the human input signal. Increased by the negative feedback amplifier circuit 104
and output to the output terminal 11B.

つtシ、出力端子117,118には、互に逆位相の信
号が出力され、負荷114’を接続すれば、単体増幅器
に比べて4倍の電力が得られる。これは、BTL方式増
幅回路としては、第2図で示し九従米回路と同様で、そ
の動作もほぼ同じであるがこの実施例においては、初段
に、非反転型負帰還増幅回路101を用い、また、位相
反転に、反転型負帰還増幅回路1′02を用い、第2図
の従来回路の場合は、初段の差動増幅器50が無帰還で
あることが異っている。
In addition, signals having mutually opposite phases are output to the output terminals 117 and 118, and if a load 114' is connected, four times the power can be obtained compared to a single amplifier. As a BTL type amplifier circuit, this is similar to the nine-conductor circuit shown in FIG. Furthermore, an inverting negative feedback amplifier circuit 1'02 is used for phase inversion, and the difference from the conventional circuit shown in FIG. 2 is that the first stage differential amplifier 50 is non-feedback.

一般的に負帰還増幅回路の場合、無帰還時の電圧利得を
Avo帰還率をβとした場合、負帰還増幅回路の電圧利
得の変動は無帰還時の電圧利得Av。
Generally, in the case of a negative feedback amplifier circuit, if the voltage gain without feedback is Avo and the feedback rate is β, then the fluctuation of the voltage gain of the negative feedback amplifier circuit is the voltage gain Av without feedback.

の変動のl / (1+Avoβ)に圧縮され、ひずみ
率も無帰還時のひずみ率の17 (1+Avoβ)に感
じられることは公知である。
It is well known that the fluctuation of the signal is compressed to 1/(1+Avoβ), and the distortion rate is felt to be 17(1+Avoβ), which is the distortion rate when there is no feedback.

したがって本実施例では、非反転型負帰還増幅回路10
1反転型負帰還増幅回路102の利得は11′なので帰
還率β=1となシ各々の増幅回路の電圧利得の変動及び
ひずみ率は無帰還時のl/1 +Avo に感じられ安
定化される。
Therefore, in this embodiment, the non-inverting negative feedback amplifier circuit 10
Since the gain of the 1-inverting negative feedback amplifier circuit 102 is 11', the feedback factor β = 1. The voltage gain fluctuation and distortion rate of each amplifier circuit are felt and stabilized as l/1 + Avo when there is no feedback. .

また電圧利得の変動が1 / 1+Avoに圧縮される
為出力熾子間の直流電圧差も安定化されることになシ、
BTL方式増幅回路としても電圧利得の変動が小さくま
た出力抱子117,118の直流電圧差も小さくひずみ
率においても低ひずみ率が実現できる。
In addition, since fluctuations in voltage gain are compressed to 1/1+Avo, the DC voltage difference between the output terminals is also stabilized.
Even as a BTL type amplifier circuit, fluctuations in the voltage gain are small, and the DC voltage difference between the output brackets 117 and 118 is also small, making it possible to achieve a low distortion rate.

〔発明の効果〕〔Effect of the invention〕

以上の様に、本発明によれば、BTL方式増幅回路にお
いて、初段に非反転製負帰還増幅回路をおき、また、位
相反転を、反転型負帰還増幅回路で行なうことによシ、
電圧利得のバラツキを小さくし、出力量直流電圧差を小
さくシ、また、低歪率を実現することができる。
As described above, according to the present invention, in a BTL type amplifier circuit, a non-inverting negative feedback amplifier circuit is provided at the first stage, and phase inversion is performed by an inverting negative feedback amplifier circuit.
It is possible to reduce variations in voltage gain, reduce output amount DC voltage difference, and achieve low distortion.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例によるBTL方式増幅回路を
示す結線図、第2図rC従来のBTL方式増幅回路の結
線図である。 1.2・・・・・・PNP)ツンジスタ、3,4,5,
7゜8.10,105,106,107,109,11
0゜112・・・・・・抵抗、6,9,108,111
・・・・・・コンデンサ、11・・・・・・定電流源、
12,113・・・・・・定電圧源、13,14,10
1,102,103,104・・・・−負帰還増幅回路
、15,114・・・・・・負荷、16,115・・・
・・・入力端子、17,116・・・・・・電源層子、
18゜19.117,118・・・・・・出力趨子、2
0,119・・・・・・接地趨子。 1、・−)、。
FIG. 1 is a wiring diagram showing a BTL type amplifier circuit according to an embodiment of the present invention, and FIG. 2 is a wiring diagram of a conventional BTL type amplifier circuit. 1.2...PNP) Tunjista, 3, 4, 5,
7゜8.10,105,106,107,109,11
0°112...Resistance, 6,9,108,111
... Capacitor, 11 ... Constant current source,
12,113... Constant voltage source, 13,14,10
1,102,103,104...-negative feedback amplifier circuit, 15,114...load, 16,115...
...Input terminal, 17,116...Power supply layer,
18゜19.117,118... Output trend, 2
0,119... Grounding trend. 1,・-),.

Claims (1)

【特許請求の範囲】 入力端子に加えられる入力信号受ける第10負帰還増幅
回路と、該第1の負帰還増幅回路の出力を増幅する第2
の負帰還増幅回路と、前記第1の負帰還増幅回路の出力
を受ける利得“1”の反転型負帰還増幅回路と、該反転
型負帰還増幅回路。 出力を増幅する第3の負帰還増幅回路と、前記第1およ
び第2の負帰還増幅回路の出力間に接続された負荷とを
有することを特徴とする電力増幅器。
[Claims] A tenth negative feedback amplifier circuit that receives an input signal applied to an input terminal, and a second negative feedback amplifier circuit that amplifies the output of the first negative feedback amplifier circuit.
an inverting negative feedback amplifier circuit with a gain of "1" that receives the output of the first negative feedback amplifier circuit; and the inverting negative feedback amplifier circuit. A power amplifier comprising: a third negative feedback amplifier circuit that amplifies an output; and a load connected between the outputs of the first and second negative feedback amplifier circuits.
JP59253520A 1984-11-30 1984-11-30 Power amplifier Pending JPS61131906A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59253520A JPS61131906A (en) 1984-11-30 1984-11-30 Power amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59253520A JPS61131906A (en) 1984-11-30 1984-11-30 Power amplifier

Publications (1)

Publication Number Publication Date
JPS61131906A true JPS61131906A (en) 1986-06-19

Family

ID=17252508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59253520A Pending JPS61131906A (en) 1984-11-30 1984-11-30 Power amplifier

Country Status (1)

Country Link
JP (1) JPS61131906A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0486320U (en) * 1990-11-30 1992-07-27

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0486320U (en) * 1990-11-30 1992-07-27

Similar Documents

Publication Publication Date Title
KR960000774B1 (en) Bridge amp
US4406990A (en) Direct coupled DC amplification circuit
US3914703A (en) Half-bridge audio amplifier
JPS62199105A (en) Integrated low frequency power amplifier
JPS59207712A (en) Amplifier
JPS61131906A (en) Power amplifier
JPS5947486B2 (en) Pulse width modulation amplification circuit
JP2696986B2 (en) Low frequency amplifier
US4167708A (en) Transistor amplifier
JPS60239108A (en) Improved mutual conductance amplifier
JPS631768B2 (en)
US20020097093A1 (en) Compact variable gain amplifier
JPS5836005A (en) Amplifying circuit
JPH0527282B2 (en)
JPS5840370B2 (en) Zoufuku Cairo
JPH0434843B2 (en)
JPH062335Y2 (en) Balanced amplifier
JPS6017935Y2 (en) amplifier
JPH0440886B2 (en)
JP2507029B2 (en) amplifier
JPH01268302A (en) Amplifier circuit
JPH0124363B2 (en)
JPH03255711A (en) Intermediate frequency amplifier circuit
JPS5811057Y2 (en) mixing circuit
JPH0336100Y2 (en)