JPH0440886B2 - - Google Patents

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Publication number
JPH0440886B2
JPH0440886B2 JP56174495A JP17449581A JPH0440886B2 JP H0440886 B2 JPH0440886 B2 JP H0440886B2 JP 56174495 A JP56174495 A JP 56174495A JP 17449581 A JP17449581 A JP 17449581A JP H0440886 B2 JPH0440886 B2 JP H0440886B2
Authority
JP
Japan
Prior art keywords
output
amplification stage
differential
amplifier
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56174495A
Other languages
Japanese (ja)
Other versions
JPS5877310A (en
Inventor
Shigeru Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP56174495A priority Critical patent/JPS5877310A/en
Publication of JPS5877310A publication Critical patent/JPS5877310A/en
Publication of JPH0440886B2 publication Critical patent/JPH0440886B2/ja
Granted legal-status Critical Current

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  • Amplifiers (AREA)

Description

【発明の詳細な説明】 本発明はバランスド・トランスホーマレス(以
下BTLと略記する)増幅器に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a balanced transformerless (hereinafter abbreviated as BTL) amplifier.

低電源電圧で大出力を得ることのできる増幅器
としてBTL増幅器が用いられる。
BTL amplifiers are used as amplifiers that can obtain high output with low power supply voltage.

従来のBTL増幅器はたとえば第1図に示す如
く、反転増幅器1、電圧増幅段2および電流増幅
段3からなる第1の電力増幅器4、第1の電力増
幅器と同様に構成された第2の電力増幅器5を必
要とし、部品点数が多く、回路が複雑になる欠点
があつた。なお6は負荷としてのスピーカであ
る。
A conventional BTL amplifier includes, for example, as shown in FIG. 1, a first power amplifier 4 consisting of an inverting amplifier 1, a voltage amplification stage 2, and a current amplification stage 3, and a second power amplifier configured similarly to the first power amplifier. The disadvantage is that the amplifier 5 is required, the number of parts is large, and the circuit is complicated. Note that 6 is a speaker as a load.

本発明は上記にかんがみなされたもので上記の
欠点を解消して、部品点数が少なくかつ回路構成
が簡単なBTL増幅器を提供することを目的とす
る。
The present invention has been made in view of the above, and it is an object of the present invention to eliminate the above-mentioned drawbacks and provide a BTL amplifier with a small number of parts and a simple circuit configuration.

以下、本発明を実施例により説明する。 The present invention will be explained below with reference to Examples.

第2図は本発明の一実施例の回路図である。 FIG. 2 is a circuit diagram of one embodiment of the present invention.

10は電圧増幅段を、11および12は電圧増
幅段10からの出力および反転出力で駆動されス
ピーカ6を駆動する電流増幅段であり、13は負
帰還回路である。
10 is a voltage amplification stage, 11 and 12 are current amplification stages driven by the output and inverted output from the voltage amplification stage 10 to drive the speaker 6, and 13 is a negative feedback circuit.

電圧増幅段10は入力電圧が印加されるトラン
ジスタQ1および負帰還回路13の出力電圧が印
加されるトランジスタQ2および定電流源回路I
とからなる初段の差動増幅器Aと、初段の差動増
幅器Aの出力をそれぞれ増幅するトランジスタ
Q3およびQ4からなる第2段の差動増幅器Bとか
らなつている。すなわち、第1入力端子(入力端
子N)としてのトランジスタQ1のベースと、
第2入力端子としてのトランジスタQ2のベース
には、それぞれ入力電圧、および負帰還回路13
の出力電圧が印加される。
The voltage amplification stage 10 includes a transistor Q 1 to which an input voltage is applied, a transistor Q 2 to which an output voltage of the negative feedback circuit 13 is applied, and a constant current source circuit I.
and a transistor that amplifies the output of the first-stage differential amplifier A, respectively.
It consists of a second stage differential amplifier B consisting of Q3 and Q4 . That is, the base of the transistor Q 1 as the first input terminal (input terminal N),
The input voltage and the negative feedback circuit 13 are connected to the base of the transistor Q 2 as the second input terminal, respectively.
An output voltage of is applied.

電流増幅段11は第2段の差動増幅器Bのトラ
ンジスタQ4の出力を電流増幅するコンプリメン
タリ接続のトランジスタQ5,Q6,Q7およびQ8
からなつている。また電流増幅段12は第2段の
差動増幅器BのトランジスタQ3の出力を電流増
幅するコンプリメンタリ接続のトランジスタQ9
Q10,Q11およびQ12とからなつている。
The current amplification stage 11 consists of complementary connected transistors Q 5 , Q 6 , Q 7 and Q 8 for current amplifying the output of the transistor Q 4 of the second stage differential amplifier B. Further, the current amplification stage 12 includes complementary-connected transistors Q 9 , which amplify the current of the output of the transistor Q 3 of the second stage differential amplifier B;
It consists of Q 10 , Q 11 and Q 12 .

一方、負帰還回路13は電流増幅段11の出力
端E点の信号が、電流増幅段12の出力端F点の
信号と逆相のため、F点の信号を反転してE点の
信号と混合して増幅し、電圧増幅段10の初段の
差動増幅器Aの第2入力端子に反転入力として帰
還するための回路である。
On the other hand, since the signal at the output terminal E point of the current amplification stage 11 is in reverse phase with the signal at the output terminal F point of the current amplification stage 12, the negative feedback circuit 13 inverts the signal at the F point and generates the signal at the E point. This is a circuit for mixing and amplifying the mixed signals and feeding them back to the second input terminal of the first-stage differential amplifier A of the voltage amplification stage 10 as an inverting input.

いま電圧増幅段10の入力端子INに入力信号
が印加された場合、各段の信号の状態は第2図に
おいて正弦波状の図で示してある。
When an input signal is now applied to the input terminal IN of the voltage amplification stage 10, the state of the signal at each stage is shown by a sine wave diagram in FIG.

入力信号は電圧増幅段10で電圧増幅される
が、その出力段である第2段の差動増幅器Bから
平衡出力として取り出される。すなわち、トラン
ジスタQ3の出力点D点には、トランジスタQ4
出力点C点の信号と逆相であつて振幅の全く等し
い信号が発生している。従つてこのトランジスタ
Q3,Q4の出力信号を電流増幅段11および12
で電流増幅することにより、別途に反転増幅器を
必要としなくなり、BTL回路が簡単となり、部
品点数が減少することになる。
The input signal is voltage amplified in the voltage amplification stage 10, and is taken out as a balanced output from the second stage differential amplifier B, which is the output stage. That is, a signal is generated at the output point D of the transistor Q 3 that is in opposite phase to the signal at the output point C of the transistor Q 4 and has exactly the same amplitude. Therefore this transistor
The output signals of Q 3 and Q 4 are transferred to current amplification stages 11 and 12.
By amplifying the current with , there is no need for a separate inverting amplifier, which simplifies the BTL circuit and reduces the number of components.

また負帰還をかける場合においても、第3図に
示す如くE点の信号をトランジスタQ13で反転
し、F点の信号と加えるようにすることで、負帰
還回路を簡略化することもできる。
Furthermore, even when negative feedback is applied, the negative feedback circuit can be simplified by inverting the signal at point E with transistor Q13 and adding it to the signal at point F, as shown in FIG.

以上説明した如く本発明によれば、入力信号を
増幅する電圧増幅段を差動増幅器で構成し、前記
差動増幅器を構成するトランジスタからそれぞれ
反転出力を取り出し、電流増幅するようにしたこ
とにより、従来のBTL増幅器の如く別途反転回
路を必要とせず、回路構成が簡単になつて、部品
点数も減少する。
As explained above, according to the present invention, the voltage amplification stage for amplifying the input signal is composed of a differential amplifier, and the inverted output is taken out from each transistor constituting the differential amplifier and current amplified. Unlike conventional BTL amplifiers, there is no need for a separate inverting circuit, which simplifies the circuit configuration and reduces the number of parts.

また、従来のBTL増幅器の如く一方の電力増
幅器にのみ反転増幅器を通した信号を印加して電
力増幅する必要もないために、2つの電力増幅器
間における時間遅れも生じることはなくなる。さ
らに、負荷の両端の電位差を検出してこれを帰還
しているので、負荷に流れる信号の入力信号と一
致させることができ、また、入力端に入力抵抗器
を接続する必要がないことから、ノイズの増加が
なくS/Nを悪化を防止できる等の効果を有する
ものである。
Further, unlike the conventional BTL amplifier, there is no need to apply a signal passed through an inverting amplifier to only one power amplifier to amplify the power, so there is no time delay between the two power amplifiers. Furthermore, since the potential difference between both ends of the load is detected and fed back, it is possible to match the input signal of the signal flowing to the load, and there is no need to connect an input resistor to the input terminal. This has the effect of preventing the S/N from deteriorating without increasing noise.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のBTL増幅器の回路図、第2図
は本発明の一実施例の回路図、第3図は第2図に
おける負帰還回路の他の例を示す回路図である。 10……電圧増幅段、11および12……電流
増幅段、13……負帰還回路、A……初段の差動
増幅器、B……第2段の差動増幅器、I……定電
流源回路。
FIG. 1 is a circuit diagram of a conventional BTL amplifier, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a circuit diagram showing another example of the negative feedback circuit in FIG. 2. 10... Voltage amplification stage, 11 and 12... Current amplification stage, 13... Negative feedback circuit, A... First stage differential amplifier, B... Second stage differential amplifier, I... Constant current source circuit .

Claims (1)

【特許請求の範囲】 1 第1、第2入力端子を有する差動トランジス
タによる第1差動増幅器と、該第1差動増幅器の
出力をそれぞれ増幅する差動トランジスタによる
第2差動増幅器とを備え、入力信号が前記第1ベ
ース入力端子に入力され、該入力信号を電圧増幅
する電圧増幅段と、 前記電圧増幅段の第2差動増幅器の差動トラン
ジスタから出力される第1および第2出力がそれ
ぞれ入力され、各第1、第2出力を電流増幅する
第1、第2電流増幅段と、 該各第1、第2電流増幅段の出力間に接続され
る負荷と、 前記第1電流増幅段よりの出力から前記第2電
流増幅段よりの出力を減算し、これを前記電圧増
幅段の第1差動増幅器の差動トランジスタの第2
入力端子に入力することにより、該差動トランジ
スタに対して負帰還するようにした負帰還回路
と、 を具備したことを特徴とするバランスド・トラン
スホーマレス増幅器。
[Claims] 1. A first differential amplifier made of differential transistors having first and second input terminals, and a second differential amplifier made of differential transistors each amplifying the output of the first differential amplifier. a voltage amplification stage, the input signal being input to the first base input terminal and voltage amplifying the input signal; and first and second differential transistors output from the differential transistor of the second differential amplifier of the voltage amplification stage. first and second current amplification stages to which the outputs are respectively input and which amplify the respective first and second outputs; a load connected between the outputs of the first and second current amplification stages; and a load connected between the outputs of the first and second current amplification stages; The output from the second current amplification stage is subtracted from the output from the current amplification stage, and this is subtracted from the output from the second differential transistor of the first differential amplifier of the voltage amplification stage.
A balanced transformerless amplifier comprising: a negative feedback circuit configured to provide negative feedback to the differential transistor by inputting it to an input terminal.
JP56174495A 1981-11-02 1981-11-02 Balanced transformerless amplifier Granted JPS5877310A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56174495A JPS5877310A (en) 1981-11-02 1981-11-02 Balanced transformerless amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56174495A JPS5877310A (en) 1981-11-02 1981-11-02 Balanced transformerless amplifier

Publications (2)

Publication Number Publication Date
JPS5877310A JPS5877310A (en) 1983-05-10
JPH0440886B2 true JPH0440886B2 (en) 1992-07-06

Family

ID=15979484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56174495A Granted JPS5877310A (en) 1981-11-02 1981-11-02 Balanced transformerless amplifier

Country Status (1)

Country Link
JP (1) JPS5877310A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4806813A (en) * 1986-03-20 1989-02-21 Canon Kabushiki Kaisha Motor
JPH0486320U (en) * 1990-11-30 1992-07-27
US5399986A (en) * 1993-12-20 1995-03-21 Yen; Wailit Isolated multi-output power amplifier

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5478956A (en) * 1977-12-07 1979-06-23 Hitachi Ltd Amplified output circuit
JPS5615607A (en) * 1979-07-14 1981-02-14 Iseki Agricult Mach Detector for tilling depth and direction control in tiller
JPS5757621B2 (en) * 1972-09-13 1982-12-06 Bosch Gmbh Robert

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5757621U (en) * 1980-09-19 1982-04-05

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5757621B2 (en) * 1972-09-13 1982-12-06 Bosch Gmbh Robert
JPS5478956A (en) * 1977-12-07 1979-06-23 Hitachi Ltd Amplified output circuit
JPS5615607A (en) * 1979-07-14 1981-02-14 Iseki Agricult Mach Detector for tilling depth and direction control in tiller

Also Published As

Publication number Publication date
JPS5877310A (en) 1983-05-10

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