JPS61131154U

JPS61131154U -

Info

Publication number: JPS61131154U
Application number: JP1372685U
Authority: JP
Priority date: 1985-02-04
Filing date: 1985-02-04
Publication date: 1986-08-16

Description

[Brief explanation of the drawing]

第１図は本考案一実施例の回線変換器の構成図
。第２図はその回線切替データのフオーマツトを
示す図。第３図はそのＮＡＮＤゲート及びカウン
タの入出力の信号波形を示す図。第４図はその回
線切替データ信号の各種の切替パターンを示す図
。第５図はその切替パターンを採つたときの副Ｉ
／Ｆの個別選択のタイムチヤートを示す図。第６
図及び第７図は本考案実施例回線変換器の主Ｉ／
Ｆをオン・オフ回路に選択的に接続する例を示す
図。１０：回線変換器、１７：Ｄフリツプフロツプ
（検出手段）、２２：レジスタ（データ格納手段
）、３２：誤りチエツカ（誤りチエツク手段）、
５０：主シリアルインターフエース、６０：副シ
リアルインターフエース、７０：リレー回路（オ
ン・オフ回路）。 FIG. 1 is a block diagram of a line converter according to an embodiment of the present invention. FIG. 2 is a diagram showing the format of the line switching data. FIG. 3 is a diagram showing input/output signal waveforms of the NAND gate and counter. FIG. 4 is a diagram showing various switching patterns of the line switching data signal. Figure 5 shows sub-I when that switching pattern is adopted.
The figure which shows the time chart of individual selection of /F. 6th
7 and 7 show the main I/O of the line converter according to the embodiment of the present invention.
The figure which shows the example which connects F selectively to an on-off circuit. 10: line converter, 17: D flip-flop (detection means), 22: register (data storage means), 32: error checker (error checking means),
50: Main serial interface, 60: Sub serial interface, 70: Relay circuit (on/off circuit).

Claims

[Claims for Utility Model Registration] (1) A single main serial interface for transferring digital binary serial data, control signals and timing signals in data transmission, and a plurality of sub serial interfaces and/or on/off In a line converter selectively connected to at least a single secondary serial interface or on/off circuit in the circuit, detecting an inactive state of a single transmission request or reception authorization control circuit output of the main serial interface. detection means; and line switching data including control selection bits and error control bits for the secondary serial interface or on/off circuit, which are sent from the primary serial interface when the detection means detects an inactive state of the control output. and error checking means for feeding back the correct/incorrect signal of the transmission information based on the error control bit to a single transmission permission or reception request control input of the main serial interface, A line converter characterized in that it is configured to control at least a single sub-serial interface or on/off circuit based on a control selection bit of line switching data. (2) When the main serial interface receives data from the secondary serial interface or on/off circuit, two or more secondary serial interfaces or on/off circuits are assigned to the control selection bit of line switching data at the same time. Claim 1 of Claim 1 of the Utility Model Registration System, which is configured such that, in the event of a failure, either one of the secondary serial interface or the on/off circuit is preferentially selected, and the main serial interface receives only the data of the preferentially selected one. Line converter described in .