JPS61131140A - Buffer memory access system - Google Patents

Abstract

PURPOSE:To reduce access time to a buffer memory by starting access to all ways not in access at the same time between the detection of a hit way. CONSTITUTION:When a hit WAY is in use by a preceding access. a comparator 36 outputs a coincidence signal. Thus, buffer address register BAR 38,41 and buffer memory ways BMWAY 37,40 continue the accessing so far. Then the access to the hit BMWAY is awaited until the access of any WAY is finished When the access of one WAY is finished, a bit of a WAY of an accessing wait register (AWR) 35 is reset, a comparator 36 compares the content of a high way register HWR 34 with the content of the AWR 35 to discriminate again when the bit WAY is in use. When in use, the procedure is awaited until the access of a preceding address as to the hit WAY is finished.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides an access method for a sofa memory consisting of a plurality of ways, more specifically, an access method for a sofa memory consisting of a plurality of ways that can be accessed in parallel. In contrast, we have developed a buffer memory system that reduces the access time to the buffer memory by starting access to all ways that are not being accessed at the same time before detecting a hit way.
Regarding access methods.

[Prior art]

In order to improve the address hint rate and shorten access time, buffer memory is generally configured with multiple ways, such as multiple associative levels, and multiple ways are configured in parallel. Some have been made accessible.

FIG. 3 is a diagram illustrating a conventional parallel-accessible multiple-way buffer memory access method using a two-way example.

In Figure 3, 1) is the tag address register (T
AR), the address to access the buffer memory is sent. 12 is the tag part, TAG-WAYo 1
It consists of two ways: 20 and TAG-WAYl 121. 13 is a comparison section, which includes comparators 130 and 131;
TAG・WA Yo 120 and TAG-WA respectively
Address read from Yt 121 and TARI
Compare the upper addresses of . 14 is a hit way register (HWR) in which information regarding hit ways is set. 15 is a select circuit (SEL), HW
Based on the information in R14, the buffer memory way of the buffer memory accessed by the address (BM-W
Select AY). 16 is a buffer memory way o (BM-WAYo) that constitutes a buffer memory.
), TAG-WAY.

Data corresponding to each address stored in 120 is stored. 17 is the buffer address register (BAR
In o), the address for accessing the BM-WAYo 16 is set. On the 1st, the read data register (
RDRo), the data read from BM-WAYo16 is set.

19 is a buffer memory that constitutes a buffer memory.
In way 1 (BM-WAYt), TAG・WAYl
Data corresponding to each address stored in 121 is stored. 20 is the buffer address register (B
ARl), the address for accessing BM-WAYl 19 is set. The data read from the BM-WAYl 19 is stored in the read data register (RDRl) 21. 22 is a selection circuit.

Next, the operation of FIG. 3 will be explained with reference to the timing chart of FIG. 4. The horizontal axis in Figure 4 is the time axis, 'rt,
The intervals 'r2... are machine cycle time T as a unit.

At time Tl, an address is set in TARII (Fig. 4 ■), and its lower bit indicates 1, T A G-
WA Yo 120 and T A G-WA Yt
121 are accessed at the same time (Fig. 4 ■). Each TAG
-WAY reads the upper focus of the address corresponding to the lower bit (TAG-Read ■ in FIG. 4).

Comparators 130 and 131 are TAG/WA Y
o Each upper bit read from TAG-WAYl 120 and TAG-WAYl 121 is compared with the upper bit of TARII, and when they match, a hint signal is output. Now, T
Hit 7 on A G-WA Yo 120 and comparator 1
30 outputs a hit signal. The HWR 14 receives a hit signal from the comparator 130.
Set the information of o (Fig. 4 ■).

At time T2, the select circuit 15 sets the address of TAR II in the BARo 17 based on the contents of the HWR 14 (FIG. 4 (■)) and accesses BM.WA Y o (FIG. 4 (■)). Access to BM-WA Y o is performed within 2T time from time T2 to T4 (Fig. 4
).

At time T, data corresponding to the accessed address is set in the RDRo 18, and the select circuit 22
is transferred to a CPU (not shown) via (Fig. 4 ■)
.

At time T2, in parallel with the above operation, the next TAG
-WAY access operation is performed (■ to ◎ in Fig. 4). In this case, the TAG-WA Yt 121 is hit, and at time T3, the address of TAR II is set in the BARl 20, and the BM-WAYz 19 is accessed ((2) and (4) in FIG. 4).

At time T5, data at the accessed address is read out from the RDRl 21C and transferred to the CPU (not shown) (FIG. 4@). These operations are similar to the above-mentioned BM-W.
Since the access operation is similar to AYo 16,
Detailed explanation will be omitted.

Thereafter, the accessed BM-WAY data is read out in the same manner every hour at times Te, Tv, . . . .

In this way, in the buffer memory access method shown in FIG. 3, the TAG-WAY section can access each TAG-WAY at the same time, but each B of the buffer memory
If you try to access M-WAY and TAG at the same time,
Since the existing BM-WAY is being accessed, the BM
- Since the address of WAY will be destroyed, each BM
- You cannot start accessing WAYs at the same time. Therefore, the TAG-WAY unit 12 is accessed first, detects the WAY to be accessed from among the BM-WAYs constituting the Huffer memory, and then
- A method of starting WAY access is adopted. This method is common to other conventional buffer memory access methods consisting of multiple ways that can be accessed in parallel.

[Problem that the invention seeks to solve]

In the conventional buffer memory access method, as mentioned above, the TAG-WAY section is first accessed, the BM-WAY to be accessed in the buffer memory is detected, and then the BM-WAY is accessed. Since the start method is adopted, the buffer memory access time is the sum of the time to access the TAG/WAY section and the time to access the BM-WAY section (in the case of Figure 3, the access time for the buffer memory is As shown in Fig. 4, there is a problem that the access time becomes long (3T).

[Means for solving problems]

The present invention solves the above-mentioned problems in the conventional buffer memory access method and provides a buffer memory access method that shortens the access time to the buffer memory. In an access method for a buffer memory consisting of multiple accessible ways, when access is started and it is not known which way is to be accessed, access is started to all unused ways at the same time, and the way to be accessed is determined. After that, processing for selecting the way is performed.

[Effect]

When accessing a buffer memory consisting of a plurality of ways that can be accessed in parallel, all ways other than the way that is being used due to prior access are accessed simultaneously at the start of the access. At this point, it is not yet known which way will be accessed. For example, when the way to be accessed is determined by accessing the tag ways in each way in parallel,
For example, when the way in question is not in use due to prior access, the process to select the way in question continues to access the way in question, and accesses to other ways are discontinued. Furthermore, if the way is in use due to prior access, the way is accessed again after waiting for the end of that way.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram of an embodiment of the present invention, and FIG. 2 is an operation timing chart of the embodiment.

In FIG. 1, 31 is a tag address register (T
AR) sets the address for accessing the buffer memory. 32 is a tag (TAG) part, which is T in the figure.
A G-WA Yo 320 and TAG-WAYt 3
21 2WAYs are shown, but generally multiple WAYs are shown.
Consisting of 33 is a comparison unit having comparators 330 and 331, respectively TA G-WA Yo 320 and TA
Address read from G-WAYt 321 and T
Compare with the upper address of AR31. In general, TAG
- A plurality of them are provided corresponding to the number of WAYs. 34 is a hit way register (HWR) in which information regarding hit ways is set. 35 is an accessing way register (AWR), which is a buffer memory (B
M) has a bit width according to the number of WAYs, and the number of WAYs in use
Instruct Y. 36 is a comparator, HWR34 and AWR3
5 is compared, and it is determined whether the bit WAY is being used (accessed) by prior access. 37 is a buffer memory way that constitutes the buffer memory
(BM-WA Yo) TAG-WA Yo 3
The data of the address hit in step 20 is stored. 38
is the bathopher address register (BARo), and BM
-The address for accessing WAY37 is set.

39 is the read data register (RDRo), BM
-WAY, the data read from 37 is sent. 40 is a buffer memory way (BM-WAYl)
), data corresponding to the address stored in T A G = W A Y 1321 is stored. In general,
The above-mentioned BM-WAYo 3 corresponds to the number of TAG-WAYs.
7, a plurality of them are provided, and they are configured to have associative levels of a plurality of ways. 41 is the buffer address
The address for accessing the BM-WAYl 40 is set in the register (BARD). 42 is the read data register (RD Rx), B M-WA Y140
The data read from is set. A select circuit 43 selects a BAR to set an address based on inputs from the comparator 36 and the AWR 35. 4
4 is a select circuit, and 45 and 46 are AND circuits.

Next, the operation of FIG. 1 will be explained with reference to the timing chart of FIG. 2. The horizontal axis in FIG. 2 is the time axis, and the unit is machine cycle time T, similar to FIG. 4. The operation will be explained below in various cases, taking as an example the case where the buffer memory is 2-way as shown in the figure.

(A) When there is no BM-WAY in use In this case, A
All bits in WR35 are off. The select circuit 43 selects the BM- being accessed based on the contents of the AWR35.
After determining that there is no WAY, AND circuits 45 and 46
, and allow the address to be sent to BARo38 and BARl 41.

(A-1) Time T! In the step, the address for accessing the buffer memory is set in TAR31, and the address is also set in BARo38 and BARt41 via AND circuits 45 and 46 (second tooth ■).
.

(A-2) TAG-W by the lower bit of TAR31
AYo 320 and TAG-WAYl 321 are accessed simultaneously, and BM-WAYo 37 and BM-
WA Y140 is also accessed at the same time (second tooth ■).

(A-3) TAG-WAYo 320, TAG-WA
'The upper bit of the address corresponding to the lower bit is read from Y+321 (second tooth ■).

(A-4) Comparators 330 and 331 each have TAG-
The upper bits read from the WAYo 320 and TAG-WAY+ 321 are compared with the upper bits of the address of the TAR 31, and when they match, the hinted WAY information is set in the HWR 34. Now, BM-
Suppose that WA Yt is hit (second tooth ■).

(A-5) The comparator 36 compares the contents of the HWR 34 and AWR 35 and finds a hit B M-W AY.

320 is in use. WA in use
Since there is no Y, the comparator 36 determines that the hit WAYo is not in use and transfers the hit WAYo in the HWR 34.
The information of Y o is sent to the select circuit 43, and furthermore, the information of A
Enable WR35.

(A-6) When enabled by the comparator 36, the AWR 35 determines the T A G based on the contents of the HWR 34.
- Turn on the bit corresponding to WA Yo 320 (
2nd tooth ■). This on bit is BM WAYo 3
It is held until the access to 7 is completed.

(A-7) The select circuit 43 includes the comparator 43 and the AWR
Based on the input from 35, only the access operation of the hit WAY, that is, BM-WA Yo 37, is continued, and the access of the other WAY, that is, BM-WAY1 40 is interrupted (second tooth 3).

■).

Access to BM-WAYo 37 is from T1 to T3.
(2nd tooth ■).

(A-8) The data read from the BM-WAYo 37 is read to the RDRo 39 at time T3 (second tooth ■), and is passed through the select circuit 44 to the CP (not shown).
Transferred to U. At this point, the bit corresponding to W AY o set in AWR 35 is reset from on to off. This reset operation is performed by, for example, RDRo.
This can be done by using a data set end signal to No. 39 (not shown).

(B) There is a BM-WAY in use, but when another WAY is hit, it is assumed that BM-WA Yo is currently being accessed and in use. This case corresponds to a case where, following the operation (A) described above, an access operation to the next address is performed at time T2.

Also, the address to access is B M-W AY
Suppose that it is l.

In this case, since the B5-WAYo 37 is being accessed, the bit corresponding to the WAYo of the AWR 35 is on. The select circuit 43 is AWR35
Based on the contents of , only the AND circuit 45 is closed and the other AN
The D circuit, that is, the AND circuit 46 is opened.

(B-1) At time T2, the next address to access the buffer memory is set in TAR 31, and also set in BARi 41 via AND circuit 46. Since the AND circuit 45 is closed, no address is set in BARo38, and the above-mentioned (
The access to the preceding B M-WA Yo 37 described in A) continues ((2), (2) in FIG. 2).

(B-2) The lower bit of TAR31 allows TAG-W
A Yo 320 and T A G-WA Y+ 32
1 is accessed simultaneously, and BM-WAY+ 40
are also accessed at the same time (Fig. 2 @).

(B-3) TAG-WAYo 320 and TAG-WAY
The upper bits of the address corresponding to the lower bits of TAR31 are read from +321 (FIG. 2, 0).

(B-4) Comparators 330 and 331 each have TAG
-The upper bits read from WA Ya 320 and TAG-WAY+ 321 are compared with the upper bits of the address of TAR 31, and when they match, the information of the hit WAY is sent to HWR 34 (FIG. 2).

(B-5) Comparator 36 compares the contents of HWR 34 and AWR 35 and determines whether the hit BM-WAY 321 is in use. Since only the bit corresponding to WAYo is on, the comparator 36
It is determined that A Y 1 is not in use, and HWR34
Information about the hit W AY + is sent to the select circuit 43, and further the AWR 35 is enabled.

(B-6) AWR 35, when enabled by comparator 36, determines T A based on the contents of HWR 34.
Turn on the bit corresponding to G-WA Y+ 321 (Fig. 2 [Phase]). This on bit is held until the access to address BM-WAY+ 40 is completed.

(B-7) The select circuit 43 includes the comparator 43 and the AWR
Based on the input from 35, the access operation of the hit WAY, ie, BM-WAY Y+40, and the WAY currently in use, ie, BM-WAYo 37, is not interrupted due to the preceding access (FIG. 2 [phase], ■). In addition, BM-
WAYo 37 is in use only between Tl and T3. In addition, access to B M-W AY 140 is as follows:
It is carried out within 2T time from T2 to T4.

(B9) The data at the address accessed for BM-WAY+ 40 is stored in RDRl at time T.
42 (FIG. 2 O), and is transferred to a CPU (not shown) via a select circuit 44. at this point
The bit corresponding to WAYl set in AWR35 is reset from on to off.

Thereafter, in the same manner, the accessed BM-WAY data is sequentially read out every time T, such as Te, Tt, . . . .

In this way, as is clear from a comparison of FIGS. 2 and 4, in the conventional Banofa memory access method, it takes 3T time from the TAG address readout until the buffer memory access is completed. However, according to the present invention, this can be shortened to 2T time.

(C) When the hit WAY is in use due to advance access In this case, the comparator 36 outputs a match signal.

Therefore, each BAR and BM-WAY continue their previous access operations. Then, the access to the hit BM-WAY is made to wait until the access to one of the WAYs is completed.

When the access for one WAY ends, the bit of the WAY in the AWR 35 is reset from on to off. The comparator 36 compares the contents of the HW R 34 with the contents of the reset AWR 35, and re-determines whether the hinted WAY is in use. If it is no longer in use, the above-mentioned access operation (B) is performed for the hit WAY. If it is in use, the hit W
This means that the user will have to wait until the access to the preceding address for AY is completed.

The access operation in case (C) also applies when all WAYs are in use.

Note that if the accessed address does not exist in any WAY, the memory one level higher, for example, the main memory, is accessed. Since this method of accessing the main memory is well known, detailed explanation will be omitted.

Although the above description has been made using an example of a buffer memory consisting of a 2-way associative level, the present invention is not limited to this, and can generally access a buffer memory consisting of a plurality of WAYs. be.

〔Effect of the invention〕

As explained above, according to the present invention, for a buffer memory consisting of a plurality of WAYs that can be accessed in parallel, all WAYs that are not being accessed are started to be accessed at the same time before the detection of a hit WAY. -WAY
The buffer memory can be accessed in the time required to access the buffer memory, and the time required to access the buffer memory can be shortened.

[Brief explanation of the drawing]

1 is an explanatory diagram of an embodiment of the present invention, FIG. 2 is a timing chart illustrating the operation of the embodiment, FIG. 3 is an explanatory diagram of a conventional buffer memory access method, and FIG. 4 is a diagram illustrating the conventional buffer memory access method. 4 is a timing chart illustrating the operation of FIG. 3. FIG. In the figure, 1) and 31 are tag address registers (TAR
), 12 and 32 are tag (TAG) parts, 13 and 33
is the comparison part (C), l 4 and 34 are Hi Nodo Way.
Register (HWR), 15 is select circuit (SEL)
, 16 and 37 are buffer memory ways o (B
M-WAYo), 17 and 38 are buffer address registers o (BARo), and 18 and 39 are read registers.
Data register o (RDR.), 19 and 40 are buffer memory way l (BM
-WAYt), 20 and 41 are buffer addresses.
Register 1 (BAR+), 21 and 42 are read/
Data register l (RDR+), 22 and 44 select circuit (SEL), 35 accessing way register (AWR), 36 comparator (C), 43
45 and 46 represent a select circuit (SEL) and an AND circuit, respectively. Figure 1 PU Figure 2 Figure 4 Figure 3 PU

Claims (3)

[Claims] (1) In a buffer memory access method consisting of multiple ways that can be accessed in parallel, when it is not clear which way will be accessed at the start of access, access is started simultaneously to all ways that are not in use by advance access. 1. A buffer memory access method characterized in that after a desired way is determined, processing for selecting that way is performed. (2) If the process accessing the way is not in use due to previous access, the process continues to access the way and stops accessing other ways that started accessing at the same time as the way. A buffer memory access control system according to claim 1, characterized in that: (3) The process of accessing the way is characterized in that, if the way is in use due to a preceding access, subsequent access is temporarily interrupted, and access is made again after waiting for the completion of the subsequent access. A buffer memory access method according to claim 1.