JPS61128646A - Bus circuit - Google Patents
Bus circuitInfo
- Publication number
- JPS61128646A JPS61128646A JP25075384A JP25075384A JPS61128646A JP S61128646 A JPS61128646 A JP S61128646A JP 25075384 A JP25075384 A JP 25075384A JP 25075384 A JP25075384 A JP 25075384A JP S61128646 A JPS61128646 A JP S61128646A
- Authority
- JP
- Japan
- Prior art keywords
- driver
- common signal
- signal line
- output
- transmitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bidirectional Digital Transmission (AREA)
- Small-Scale Networks (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子制卸装置において、装置間または制御回路
間のデータ送受信を共通の信号線を介して行うバス方式
を構成するためのバス回路(=関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bus circuit for configuring a bus system in which data is transmitted and received between devices or control circuits via a common signal line in an electronic control device. (=It is related to.
この種のバス回路として、たとえば第3図に示すような
ドライバ1にトライステート出力端子を用いたバス回路
が知られている。(たとえば特開昭56−76654号
公報、特開昭57−55455号公報)ドライバ1の出
力とレシーバ2の入力を接続して送受信回路5−1〜5
−ル を形成し、共通信号#J5C;複数の送受信回路
)−1〜5−r&が接続される。共通信号線3は、反射
現象による伝送波形の乱れを防止するため、およびドラ
イバ1が高インピーダンスのときCニデータ′の論理が
不定になることを防止するために共通信号線3の両端に
終端抵抗4を介して地気(GND )に接続されている
。なおデータの論理は、しV−パ2の論理判定レベルに
より決定理“L″と判定するものとする。各送受信回路
5−1〜5−r&のドライバ1の出力は、マスクとなる
送受信回路が1個しかないように制MJH7と出力制御
回路6により制御され、マスクとして選択された送受信
回路のドライバのみ“H”または“L”レベルの低イン
ピーダンス状態(それぞれ約yc、(V)。As this type of bus circuit, for example, a bus circuit as shown in FIG. 3 using a tri-state output terminal for the driver 1 is known. (For example, JP-A No. 56-76654, JP-A-57-55455) The output of the driver 1 and the input of the receiver 2 are connected to transmit/receive circuits 5-1 to 5-5.
-1 to 5-r& are connected to form a common signal #J5C; a plurality of transmitting/receiving circuits). The common signal line 3 is provided with terminating resistors at both ends of the common signal line 3 in order to prevent the transmission waveform from being disturbed due to reflection phenomena and to prevent the logic of the Cnidata' from becoming unstable when the driver 1 has a high impedance. Connected to earth (GND) via 4. It is assumed that the logic of the data is deterministically determined to be "L" based on the logic determination level of V-PA2. The output of the driver 1 of each transmitting/receiving circuit 5-1 to 5-r& is controlled by the control MJH 7 and the output control circuit 6 so that there is only one transmitting/receiving circuit serving as a mask, and only the driver of the transmitting/receiving circuit selected as a mask “H” or “L” level low impedance state (approximately yc, (V), respectively).
約0[:V))になり、スレーブとして選択された送受
信回路のドライバの出力は高インピーダンス状態となる
。従って共通信号線3は、マスクとなった送受信回路の
ドライバ1の出力に従った論理となり、各スレーブは共
通信号線5を介してデータを受信することができる。0[:V)), and the output of the driver of the transmitting/receiving circuit selected as the slave becomes a high impedance state. Therefore, the common signal line 3 has a logic according to the output of the driver 1 of the transmitting/receiving circuit which is a mask, and each slave can receive data via the common signal line 5.
従来の構成によるバス回路は、出力制御回路6に何らか
の異常が生じ、複数の送受信回路がマスクとして選択さ
れた場合(二は、複数のドライバ1が低インピーダンス
状態になり、一方が論理“H”。In the bus circuit with the conventional configuration, when some abnormality occurs in the output control circuit 6 and multiple transmitting/receiving circuits are selected as a mask (second, multiple drivers 1 enter a low impedance state and one of them becomes a logic "H" state). .
他方が論理“L”であると、′r側から“L”側に向け
て大きな電流が流れ、ドライバ1が劣化したり、破壊し
たりするという問題がある。If the other logic is "L", a large current will flow from the 'r side to the "L" side, causing a problem that the driver 1 will deteriorate or be destroyed.
〔問題点を解決するための手段〕
本発明は従来の問題点を解決するため、共通信号線の両
端は終端抵抗を介して電源(Vcc)または地気(GN
j) )に接続し、各送受信回路のドライバの出力をダ
イオードまたは同等の機能を有する非線形素子を介して
共通信号線に接続し、各送受信回路のレシーバの入力を
直接共通信号線に接続して構成したことを特徴としてい
る。[Means for Solving the Problems] In order to solve the conventional problems, the present invention aims to connect both ends of a common signal line to a power supply (Vcc) or ground voltage (GN) via a terminating resistor.
j) ), connect the output of the driver of each transmitting/receiving circuit to the common signal line via a diode or a nonlinear element with an equivalent function, and connect the input of the receiver of each transmitting/receiving circuit directly to the common signal line. It is characterized by its composition.
本発明(二よると、ドライバの出力をダイオードなどの
非線形素子を介して共通信号線に接続することで、複数
の送受信回路がマスタC二なってドライバの出力同志が
低インピーダンス状態で接続されても過大な電流の流れ
ることがなく、かつレシーバの入力を共通信号lR+=
直接接続し、共通信号線の両端にはダイオードなどの非
線形素子の導通方向に応じてVCC側またはGND側に
終端抵抗を接続して論理判定を正常(二行うことができ
る。以下図面により詳細【二説明する。According to the present invention (2), by connecting the output of the driver to a common signal line through a nonlinear element such as a diode, multiple transmitting/receiving circuits become a master C2, and the outputs of the drivers are connected in a low impedance state. Also, no excessive current flows, and the input of the receiver is connected to the common signal lR+=
Connect directly and connect a terminal resistor to the VCC side or GND side depending on the conduction direction of a nonlinear element such as a diode at both ends of the common signal line to make a logical judgment. 2.Explain.
第1図C:本発明の一実施例を示す。ドライバ1の出力
はダイオード8を介して共通信番線6を二接続し、レシ
ーバ2は共通信号線3C二直接接続する。Figure 1C: shows an embodiment of the invention. The output of the driver 1 is connected to two common communication lines 6 via a diode 8, and the receiver 2 is directly connected to two common signal lines 3C.
共通信号線3の両端は終端抵抗4を介して電源のycc
側C二接続され、共通信号線3C二はドライバ1゜レシ
ーバ2.ダイオード8で構成される送受信回路5−1〜
5−ルが複数接続される。なおデータの論理は、レシー
バ2の論理判定レベル(二より決定さと判定するものと
する。各送受信回路5−1〜5−かのドライバ1の出力
は、マスクとなる送受信回路が1個しかなりよう(二制
御線7と出力制御回路6C二より制御され、マスクとし
て選択された送受信回路のドライバのみ“H”または“
L”レベルの低インピーダンス状態(それぞれ約Vca
LV) 、約0〔V〕フとなり、スレーブとして選択
された送受信回路のドライバの出力を高インピーダンス
状態となる。Both ends of the common signal line 3 are connected to the power supply YCC via a terminating resistor 4.
side C2 is connected, and the common signal line 3C2 is driver 1, receiver 2. Transmitting/receiving circuit 5-1 consisting of diode 8
Multiple 5-rules are connected. Note that the logic of the data is determined by the logic judgment level of the receiver 2 (determined from 2). (Controlled by the second control line 7 and output control circuit 6C2, only the driver of the transmitting/receiving circuit selected as a mask is set to "H" or "
L” level low impedance state (approximately Vca
LV) becomes about 0 [V], and the output of the driver of the transmitting/receiving circuit selected as the slave becomes a high impedance state.
本実施例の構成(二おいて、送受信回路5−1がマスク
となったとき(二は、ドライバ1は低インピーダンス状
態となり、ドライバ1の出力が論理“L”の場合、電源
VCCから終端抵抗4とダイオード8を介してドライバ
1C二電流が流れ込み、共通信号線3の電圧は、ダイオ
ード8の順電圧降下yBxcV)とドライバ1の電圧降
下Vcc lj’) (約0 (T’) )を加Ycc
の電圧を決めておけば、共通信号線3の電圧を各スレー
ブとして選択された送受信回路のレシーバは論理“L′
と判定する。Configuration of this embodiment (2) When the transmitting/receiving circuit 5-1 serves as a mask (2) When the driver 1 is in a low impedance state and the output of the driver 1 is logic "L", the terminal resistor is connected to the power supply VCC. Two currents flow into the driver 1C through the driver 4 and the diode 8, and the voltage of the common signal line 3 is the sum of the forward voltage drop yBxcV) of the diode 8 and the voltage drop Vcc lj') (approximately 0 (T')) of the driver 1. Ycc
If the voltage of the common signal line 3 is determined in advance, the receiver of the transmitting/receiving circuit selected as each slave receives the voltage of the common signal line 3 as a logic "L'
It is determined that
−1ドライバ1の出力が論理“H”の場合には、ダイオ
ード8C二よってドライバ1の出力は阻止されるので、
共通信号線3の電圧は終端抵抗41;より約VccCV
、]となり、各スレーブとして選択された送受信回路の
レシーバは論理“H”と判定する。-1 When the output of driver 1 is logic "H", the output of driver 1 is blocked by diode 8C2, so
The voltage of the common signal line 3 is approximately VccCV from the terminating resistor 41.
, ], and the receiver of the transmitting/receiving circuit selected as each slave is determined to be logic "H".
上述の判定動作(二より、スレーブとして選択された送
受信回路の関係が正常であれば、データはマスクの送受
信回路からスレーブの送受信回路に正しく送受信される
。According to the above-described determination operation (2), if the relationship between the transmitting and receiving circuits selected as slaves is normal, data is correctly transmitted and received from the mask's transmitting and receiving circuit to the slave's transmitting and receiving circuit.
たとえば、出力制御回路6C二何らかの異常が生じ、送
受信回路5−1と5−ルの2個の送受信回路がマスクと
なり、送受信回路5−1のドライバ1の出力が“(、n
、送受信回路5− nのドライバ1の出力が“HN3;
なっている場合を考えると、送受信回路5−ルのドライ
バ1の出力はダイオード8C二よって阻止されているの
で、共通信号線3(二は電流は流れ込まず、送受信回路
5−1のドライバ1の出力〈二は正常時の“L″レベル
ときの電流しか流れない。送受信回路5−1のドライバ
1の出力が“H”、送受信回路5−かのドライバ1の出
力がL″の場合(二も同様(二正常時の電流しか流れな
い。また複数のマスクとして選択された送受信回路の出
力が”L”の場合は、正常の“L”レベルのときC:流
れる一定の礒流乞複数のドライバで分流させるだけで、
過大な電流が流れることはす<、一方複数のマスクとし
て選択された送受信回路の出力が“H”の場合C二は、
ダイオードl二よりドライバから共通信号線への電流は
阻止されるので、同様(二過大な電流が流れることはな
い。従って複数の送受信回路がマスタC:=なった場合
でも、過電流C二よるドライバの素子の劣化や破壊を防
止できることC二なる。For example, if some abnormality occurs in the output control circuit 6C2, the two transmitting/receiving circuits 5-1 and 5-R become masks, and the output of the driver 1 of the transmitting/receiving circuit 5-1 becomes "(,n
, the output of the driver 1 of the transmitting/receiving circuit 5-n is “HN3;
Considering the case where the output of the driver 1 of the transmitting/receiving circuit 5-1 is blocked by the diode 8C2, no current flows into the common signal line 3 (2), and the output of the driver 1 of the transmitting/receiving circuit 5-1 is blocked by the diode 8C2. Only the current at the normal "L" level flows through the output (2).If the output of the driver 1 of the transmitting/receiving circuit 5-1 is "H" and the output of the driver 1 of the transmitting/receiving circuit 5-1 is "L" (2 Similarly (2) Only the normal current flows.Also, if the output of the transmitter/receiver circuit selected as multiple masks is "L", when the output is at the normal "L" level, C: A constant current flows. Simply divert the flow with a driver,
There is no possibility that an excessive current will flow. On the other hand, if the outputs of the transmitter/receiver circuits selected as multiple masks are "H", C2 is
Since the current from the driver to the common signal line is blocked by the diode L2, an excessive current will not flow. Therefore, even if multiple transmitter/receiver circuits become master C:=, the overcurrent C2 C2: Deterioration and destruction of driver elements can be prevented.
第2図は本発明の第2の実施例である。第1の実施例と
異なる点は、終端抵抗4¥GND側に接続し、ドライバ
ーから共通信号線61ニダイオード8を介して接続する
ときのダイオード8の導通方向を逆方向C;したことで
ある。本実施例では、マスクとして選択された送受信回
路の出力が“L″の場合は、共通信号線3の終端抵抗4
(二より“L”レベルとなり、マスクとして選択された
送受信回路の出力が“H″の場合C二は、ドライバーか
らダイオード4を介して終端抵抗4イニ電流が流れ、ド
ライバーの出力インピーダンスが低いので共通信号線6
の電圧y、(y)は約Vat T’JJ(V)となり
、yl≧−VCCとなるよう(二Vccの電圧を決めて
おけば、各スレーブとして選択された送受信回路の7ン
ーバは論理“H”と判定できる。マスクとして複数の送
受信回路が選択されたときi;、過大な電流が流nるの
を防止できることは第1の実施例の場合と同様である。FIG. 2 shows a second embodiment of the invention. The difference from the first embodiment is that the direction of conduction of the diode 8 is reversed when the terminal resistor 4 is connected to the GND side and the driver is connected to the common signal line 61 via the diode 8. . In this embodiment, when the output of the transmitting/receiving circuit selected as a mask is "L", the terminal resistor 4 of the common signal line 3
(If C2 becomes "L" level and the output of the transmitting/receiving circuit selected as a mask is "H", current flows from the driver through the terminating resistor 4 through the diode 4, and the output impedance of the driver is low. Common signal line 6
The voltage y, (y) is approximately Vat T'JJ (V), and if the voltage of 2Vcc is determined so that yl≧−VCC, the 7 members of the transmitting and receiving circuit selected as each slave will be logical “ When a plurality of transmitting/receiving circuits are selected as masks, it is possible to prevent excessive current from flowing, as in the case of the first embodiment.
本実施例の構成C二よれば、′L”レベルが終端抵抗の
みで決まるので、TTLのレシーバなど論理判定電圧が
低い素子でも使用可能になるという利点がある。According to configuration C2 of this embodiment, since the 'L' level is determined only by the terminating resistor, there is an advantage that it can be used even with elements having a low logic determination voltage such as a TTL receiver.
またマスクとして選択された送受信回路が動作していな
いときの共通信号線の論理は、第1の実施例の場合は“
H”レベル、@2の実施例の場合は“L”レベルである
ので、装置ζ;より都合のよい論理を選択することが可
能である。In addition, the logic of the common signal line when the transmitter/receiver circuit selected as a mask is not operating is "
In the case of the embodiment @2, it is the "H" level, so it is possible to select a more convenient logic for the device ζ.
なお上記の実施例では、ドライバと共通信号線をダイオ
ードを介して接続した例について説明したが、ダイオー
ドに限定されるものではなく、ダイオードと同等の機能
を有する非線形素子であればよい。またドライバ、レシ
ーバ、ダイオードからなる送受信回路について説明した
が、本発明はこれと同等の機能を備えた装置を含むもの
である。Note that in the above embodiment, an example was explained in which the driver and the common signal line were connected through a diode, but the present invention is not limited to a diode, and any nonlinear element having the same function as a diode may be used. Further, although the transmitting/receiving circuit consisting of a driver, a receiver, and a diode has been described, the present invention includes a device having functions equivalent to this.
以上述べたように、本発明によればドライバの出力をダ
イオードなどの非線形素子を介して共通信号線に接続し
たので、複数のドライバが同時に出力しても過大な電流
が流れることがなくなり。As described above, according to the present invention, the output of the driver is connected to the common signal line via a nonlinear element such as a diode, so that even if multiple drivers output simultaneously, an excessive current will not flow.
ドライバ素子の劣化や破壊が防止できる。またCMOS
やTTLのトーテムポール出力などで“H”または“L
ルベルの状態しかとり得ない出力素子でも、送受信回路
がマスクとして選択されたときのみ共通信号線の定常論
理(第1の実施例では“H”、第2の実施例では“L”
)と逆の論理を出力するよう(:制御すればバス回路
を構成することが可能となり利用価値が大きい。Deterioration and destruction of the driver element can be prevented. Also CMOS
“H” or “L” for TTL totem pole output, etc.
Even if the output element can only take the level state, the steady state logic of the common signal line (“H” in the first embodiment, “L” in the second embodiment) is applied only when the transmitter/receiver circuit is selected as a mask.
), it is possible to configure a bus circuit by controlling it to output the opposite logic (:), which has great utility value.
第1図は本発明の第1の実施例、第2図は本発明の第2
の実施例、第3図は従来のバス回路の構成を示す図であ
る。
路、7・・・制御線、8・・・ダイオードまたは同等の
機能を有する非線形素子FIG. 1 shows a first embodiment of the present invention, and FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a diagram showing the configuration of a conventional bus circuit. 7... Control line, 8... Diode or nonlinear element with equivalent function
Claims (2)
るバス回路において、前記共通信号線の両端に終端抵抗
を接続し、前記複数の各送受信回路のドライバの出力を
ダイオードまたは同等の機能を有する非線形素子を介し
て前記共通信号線に接続し、前記複数の各送受信回路の
レシーバの入力を前記共通信号線に直接接続してなるこ
とを特徴とするバス回路。(1) In a bus circuit configured by connecting a plurality of transmitting/receiving circuits to a common signal line, a terminating resistor is connected to both ends of the common signal line, and the output of the driver of each of the plurality of transmitting/receiving circuits is connected to a diode or equivalent function. A bus circuit characterized in that the bus circuit is connected to the common signal line through a nonlinear element having a nonlinear element, and the input of a receiver of each of the plurality of transmitting/receiving circuits is directly connected to the common signal line.
ル出力素子またはトライステート出力素子のいずれかを
用いてなることを特徴とする特許請求の範囲第1項記載
のバス回路。(2) The bus circuit according to claim 1, wherein the driver uses either a CMOS, a TTL totem pole output element, or a tristate output element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25075384A JPS61128646A (en) | 1984-11-28 | 1984-11-28 | Bus circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25075384A JPS61128646A (en) | 1984-11-28 | 1984-11-28 | Bus circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61128646A true JPS61128646A (en) | 1986-06-16 |
Family
ID=17212524
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25075384A Pending JPS61128646A (en) | 1984-11-28 | 1984-11-28 | Bus circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61128646A (en) |
-
1984
- 1984-11-28 JP JP25075384A patent/JPS61128646A/en active Pending
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