JPS6033643Y2 - half duplex digital communication equipment - Google Patents
half duplex digital communication equipmentInfo
- Publication number
- JPS6033643Y2 JPS6033643Y2 JP8653478U JP8653478U JPS6033643Y2 JP S6033643 Y2 JPS6033643 Y2 JP S6033643Y2 JP 8653478 U JP8653478 U JP 8653478U JP 8653478 U JP8653478 U JP 8653478U JP S6033643 Y2 JPS6033643 Y2 JP S6033643Y2
- Authority
- JP
- Japan
- Prior art keywords
- line
- voltage
- communication
- resistor
- communication line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Bidirectional Digital Transmission (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
【考案の詳細な説明】
本考案は半二重ディジタル通信装置の改良に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in half-duplex digital communication equipment.
半二重ディジタル通信装置の従来例としては第1図のよ
うなものがある。A conventional example of a half-duplex digital communication device is as shown in FIG.
すなわち2線1対の通信線りの一線に両局側においてそ
れぞれ抵抗R□を介してプル・アップ電EEVCCを与
え、このプル・アップ電圧EVCCが与えられた通信線
に両局側においてそれぞれドライバDRの出力端とレシ
ーバRVの入力端を接続し、両局におけるプル・アップ
電圧Vccのコモン点G同志を他方の通信線によって接
続するようにしたものがある。In other words, a pull-up voltage EEVCC is applied to one line of a pair of two-wire communication lines at both stations via a resistor R□, and a driver is applied to the communication line to which this pull-up voltage EVCC is applied at both stations. There is a system in which the output end of the DR and the input end of the receiver RV are connected, and the common point G of the pull-up voltage Vcc in both stations is connected by the other communication line.
このような装置において、一方の局のドライバDRがロ
ーレベル・アクティブの信号を送信すると、見かけ上通
信線りは送信側端が短絡されたようになり、受信側から
見た等他回路は第2図のようになる。In such a device, when the driver DR of one station transmits a low-level active signal, the transmission end of the communication line appears to be short-circuited, and other circuits, such as those seen from the reception side, appear to be short-circuited. It will look like Figure 2.
したがってレシーバRVの入力電圧は、通信線りの片道
の抵抗をrとすると2rVCC/R1+ガとなる。Therefore, the input voltage of the receiver RV is 2rVCC/R1+ga, where r is the one-way resistance of the communication line.
ここでrをR1よりも充分小さく選らぶことにより、レ
シーバRVの入力電圧をそのスレッショルド・レベルよ
りある程度余裕をもって小さくし、ローレベル・アクテ
ィブの信号が確実に受信されるようにしている。By selecting r to be sufficiently smaller than R1, the input voltage of receiver RV is made lower than its threshold level by some margin, so that a low-level active signal is reliably received.
しかし、抵抗rは通信距離の増加にともなって増加する
ので、通信距離を長くするにつれてスレッショルド・レ
ベルに対スる余裕が減少しノイズの影響を受けやすくな
る。However, since the resistance r increases as the communication distance increases, as the communication distance increases, the margin for the threshold level decreases, making it more susceptible to noise.
本考案の目的は、ローレベル・アクティブ信号のレベル
が通信線等の抵抗に影響されない半二重ディジタル通信
装置を提供することにある。An object of the present invention is to provide a half-duplex digital communication device in which the level of a low-level active signal is not affected by the resistance of a communication line or the like.
本考案は、
2線一対の通信線、
この通信線の両端において、2つの線のうちの第1の線
にそれぞれ抵抗を介してそれぞれプルアップ電圧を与え
、第2の線をそれぞれコモン点に接続する手段、
前記通信線の両端において、第1の線と第2の線との間
にそれぞれの出力回路が接続され、それぞれアクティブ
・レベルの信号を送信するとき線間を実質的に短絡する
2つのドライバ、
前記通信線の両端において、それぞれの線間に接続され
た、ダイオードのような非直線素子と抵抗とからなる2
つの直列回路であって、これらの直列回路におけるそれ
ぞれの非直線素子の電圧降下が、前記ドライバがアクテ
ィブ・レベルの信号を送信したときに2つの通信線にそ
れぞれ生じる電圧降下の和よりも大きく定められた2つ
の直列回路、
及び
前記通信線の両端において、前記直列回路における抵抗
の両端電圧をそれぞれの入力信号とする入力インピーダ
ンスが高い2つのレシーバを具備する半二重ディジタル
通信装置
によって上記の目的を遠戚したものである。The present invention consists of a pair of two-wire communication lines, at both ends of which a pull-up voltage is applied to the first of the two lines through a resistor, and the second line is connected to a common point. means for connecting, at both ends of the communication line, respective output circuits are connected between the first line and the second line, each substantially shorting the lines when transmitting active level signals; two drivers, each consisting of a non-linear element such as a diode and a resistor connected between each line at both ends of the communication line;
two series circuits, the voltage drop of each non-linear element in these series circuits being greater than the sum of the voltage drops that occur on each of the two communication lines when the driver transmits an active level signal; The above object is achieved by a half-duplex digital communication device comprising: two series circuits connected to each other, and two receivers at both ends of the communication line, each having a high input impedance and whose respective input signals are the voltages across the resistors in the series circuit. is a distant relative.
以下図面によって本考案を説明する。The present invention will be explained below with reference to the drawings.
第3図は本考案実施例の概念的構成図である。FIG. 3 is a conceptual diagram of the embodiment of the present invention.
第3図において、DRはドライバ、RVはレシーバ、L
は通信線である。In Figure 3, DR is a driver, RV is a receiver, and L
is a communication line.
通信線りの一線に対しA、 B両局においてそれぞれ抵
w1を介してプル・アップ電圧Vccが与えられ、通信
線の他方の線は両局におけるそれぞれのコモン点Gに接
続される。A pull-up voltage Vcc is applied to one line of the communication line at both stations A and B through a resistor w1, and the other line of the communication line is connected to the respective common point G at both stations.
通信線りの線間には両局においてダイオードDと抵抗R
2の直列回路が接続される。A diode D and a resistor R are installed between the communication lines at both stations.
Two series circuits are connected.
通信線りの線間にはまた両局においてドライバDRの出
力回路が接続される。The output circuits of the drivers DR are also connected between the communication lines at both stations.
ドライバDRに例えばオープン・コレクタ形のTTL回
路であってローレベル・アクティブの信号を生じるもの
である。The driver DR is, for example, an open collector type TTL circuit that generates a low-level active signal.
両局において抵抗R2の両端の電圧降下がそれぞれのレ
シーバRVの入力信号となる。At both stations, the voltage drop across resistor R2 becomes an input signal to each receiver RV.
このように構成された装置の動作は次のとおりである。The operation of the device configured in this way is as follows.
一方の局のドライバがローレベル・アクティブの出力信
号を生じると、通信線りは送信側端が見かけ上短絡され
たようになり、そのとき受信側から見た等価回路は第4
図のようになる。When the driver of one station generates a low-level active output signal, the transmitting end of the communication line appears to be short-circuited, and the equivalent circuit seen from the receiving end is
It will look like the figure.
すなわちダイオードDと低損B2の直列回路と通信線り
の往復抵抗玄は互いに並列関係となって抵抗R□とコモ
ン点Gの間に接続される。That is, the series circuit of the diode D and the low-loss B2 and the reciprocating resistance of the communication line are connected in parallel between the resistance R□ and the common point G.
ここでダイオードDと抵抗R2の直列回路に流れる重連
、と通信線抵抗Δに流れる電流12を考えてみると、ダ
イオードDの電圧電流特性は非直線的なので、通信線抵
抗Δにおける電圧降下がダイオードDの順方向降下電圧
■、を越えないうちはダイオードDは事実上オフとみな
すことができ、プル・アップ電圧Vccによる電流は事
実上全部玄を流れる。If we consider the current 12 flowing through the series circuit of diode D and resistor R2, and the current 12 flowing through communication line resistance Δ, the voltage-current characteristics of diode D are non-linear, so the voltage drop across communication line resistance Δ is Until the forward drop voltage of the diode D exceeds 1, the diode D can be considered to be virtually off, and virtually all of the current due to the pull-up voltage Vcc flows through the diode D.
またレシーバRVとして入力インピーダンスの高いもの
を用いることにより、レシーバRVの入力端から抵抗R
2に流れる電流はきわめて小さくされる。Also, by using a receiver RV with high input impedance, it is possible to connect the resistor R from the input end of the receiver RV.
The current flowing through 2 is made extremely small.
したがって抵抗R2の電圧降下は事実上零となり、レシ
ーバRVのスレッショルド・レベルに対して充分な余裕
を持つローレベル・アクティブの入力信号が得られる。Therefore, the voltage drop across resistor R2 becomes virtually zero, and a low-level active input signal with sufficient margin for the threshold level of receiver RV is obtained.
ダイオードDが導通しないうちはこの状態が維持され、
レシーバRVのローレベル・アクティブ入力信号は通信
線抵抗玄及び抵抗R2の影響を受けない。This state is maintained as long as diode D does not conduct.
The low level active input signal of the receiver RV is not affected by the communication line resistance and the resistance R2.
したがってダイオードDを適切に選択することにより、
通信線抵抗玄の値ヲ従来ならレシーバRVのスレッショ
ルド・レベル上許容できなかった大きな値まで増加させ
ることができる。Therefore, by appropriately selecting the diode D,
The value of the communication line resistance can be increased to a large value that was previously unacceptable due to the threshold level of the receiver RV.
すなわち信号伝送の距離を延ばすことができる。In other words, the distance of signal transmission can be extended.
なおダイオードDのかわりに必要に応じてゼナーダイオ
ードを用いてもよい。Note that a Zener diode may be used in place of the diode D, if necessary.
送信側のドライバDRがローレベル・アクティブの信号
の発生をやめると受信側から見た等価回路は第5図のよ
うになり、両局の回路条件がバランスしていれば、レシ
ーバRVにはプル・アップ電圧VccとダイオードDの
順方向降下電圧■、との差を抵ju1.R2によって分
圧した電圧が与えられる。When the driver DR on the transmitting side stops generating low-level active signals, the equivalent circuit seen from the receiving side becomes as shown in Figure 5. If the circuit conditions of both stations are balanced, there is no pull to the receiver RV. - The difference between the up voltage Vcc and the forward drop voltage (■) of the diode D is determined by the resistor ju1. A divided voltage is given by R2.
抵抗R□、R2の値を適切に定めることにヨリ、この分
電圧はレシーバRVのスレッショルド・レベルより充分
大きな値とされる。In addition to appropriately determining the values of the resistors R□ and R2, this voltage is set to a value sufficiently larger than the threshold level of the receiver RV.
以上のように、本考案によれば、ローレベル・アクティ
ブ信号のレベルが通信線等の抵抗に影響されない通信装
置が得られる。As described above, according to the present invention, it is possible to obtain a communication device in which the level of a low-level active signal is not affected by the resistance of a communication line or the like.
第1図は従来例の概念的構成図、第2図は第1図の装置
の動作時の等価回路図、第3図は本考案実施例の概念的
構成図、第4図および第5図は第3図の装置の動作時の
等価回路図である。
DR・・・・・・ドライバ、Rv・・・・・・レシーバ
、L・・・・・・通信線、R1,R2−・・・・・抵抗
、D・・・・・・ダイオード。Fig. 1 is a conceptual block diagram of the conventional example, Fig. 2 is an equivalent circuit diagram of the device shown in Fig. 1 during operation, Fig. 3 is a conceptual block diagram of the embodiment of the present invention, and Figs. 4 and 5. is an equivalent circuit diagram of the device shown in FIG. 3 when it is in operation; DR...Driver, Rv...Receiver, L...Communication line, R1, R2-...Resistance, D...Diode.
Claims (1)
にそれぞれ抵抗を介してそれぞれプルアップ電圧を与え
、第2の線をそれぞれコモン点に接続する手段、 前記通信線の両端において、第1の線と第2の線との間
にそれぞれの出力回路が接続され、それぞれアクティブ
・レベルの信号を送信するとき線間を実質的に短絡する
2つのドライバ、 前記通信線の両端において、それぞれの線間に接続され
た、ダイオードのような非直線素子と抵抗とからなる2
つの直列回路であって、これらの直列回路におけるそれ
ぞれの非直線素子の電圧降下が、前記ドライバがアクテ
ィブ・レベルの信号を送信したときに2つの通信線にそ
れぞれ生じる電圧降下の和よりも大きく定められた2つ
の直列回路、 及び 前記通信線の両端において、前記直列回路における抵抗
の両端電圧をそれぞれの入力信号とする入力インピーダ
ンスが高い2つのレシーバを具備する半二重ディジタル
通信装置。[Claims for Utility Model Registration] A pair of two-wire communication lines, at both ends of which a pull-up voltage is applied to the first of the two lines through a resistor, and the second line is means for connecting each to a common point; at both ends of the communication line, respective output circuits are connected between the first line and the second line, and when transmitting active level signals, the lines are substantially connected to each other; two drivers that are short-circuited, each consisting of a non-linear element such as a diode and a resistor connected between each line at both ends of the communication line;
two series circuits, the voltage drop of each non-linear element in these series circuits being greater than the sum of the voltage drops that occur on each of the two communication lines when the driver transmits an active level signal; a half-duplex digital communication device, comprising: two series circuits arranged in series, and two receivers at both ends of the communication line, each having a high input impedance and whose input signal is a voltage across a resistor in the series circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8653478U JPS6033643Y2 (en) | 1978-06-23 | 1978-06-23 | half duplex digital communication equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8653478U JPS6033643Y2 (en) | 1978-06-23 | 1978-06-23 | half duplex digital communication equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS553588U JPS553588U (en) | 1980-01-10 |
JPS6033643Y2 true JPS6033643Y2 (en) | 1985-10-07 |
Family
ID=29011209
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8653478U Expired JPS6033643Y2 (en) | 1978-06-23 | 1978-06-23 | half duplex digital communication equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6033643Y2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6139277A (en) * | 1985-04-05 | 1986-02-25 | Hitachi Maxell Ltd | Tape cartridge |
JPH087572Y2 (en) * | 1985-09-19 | 1996-03-04 | 松下電器産業株式会社 | Tape cassette |
JPH0427021Y2 (en) * | 1986-06-19 | 1992-06-29 |
-
1978
- 1978-06-23 JP JP8653478U patent/JPS6033643Y2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS553588U (en) | 1980-01-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5243623A (en) | Switchable multi-mode transceiver interface device | |
US4493092A (en) | Interface circuit for digital signal transmission system | |
US4317232A (en) | Fiber optic signal conditioning circuit | |
US5408694A (en) | Receiver squelch circuit with adjustable threshold | |
EP0100177B1 (en) | A differential signal receiver | |
US4149030A (en) | Multi-drop communications device | |
JPS6033643Y2 (en) | half duplex digital communication equipment | |
US4178569A (en) | Hybrid for two-wire full-duplex transmission of digital signals | |
US4012590A (en) | Circuit arrangement for two-wire full duplex data transmission | |
US4037065A (en) | 20 Hz Ringdown solid state two-wire/four-wire converter | |
US10187229B2 (en) | Bi-directional, full-duplex differential communication over a single conductor pair | |
US4785467A (en) | Transmission system employing high impedance detection for carrier detection | |
US6181167B1 (en) | Full duplex CMOS communication | |
EP1597677B1 (en) | Arrangement for compensation of ground offset in a data bus system | |
US4768191A (en) | Digital data and orderwire combiner apparatus | |
JPS6361816B2 (en) | ||
US6603805B1 (en) | Transceiver circuit transmitting/receiving a tenary pulse signal | |
US2636942A (en) | Hub telegraph repeater | |
KR20000074847A (en) | Low voltage differential signal communication system | |
US4055775A (en) | Transmission circuit for direct current data transmission | |
JPS58219826A (en) | Bilateral transmitting/receiving circuit | |
US6366976B1 (en) | Device for connecting a subscriber to a bus line | |
US3710021A (en) | Circuit arrangement for the connection of a low voltage direct current data transmission systems to a data exchange | |
KR20040031054A (en) | Transmitter/receiver for bidirectional communication | |
JPS60253341A (en) | Transmission and reception circuit for data transmission |