JPS61127210A - Am detector - Google Patents

Am detector

Info

Publication number
JPS61127210A
JPS61127210A JP24877784A JP24877784A JPS61127210A JP S61127210 A JPS61127210 A JP S61127210A JP 24877784 A JP24877784 A JP 24877784A JP 24877784 A JP24877784 A JP 24877784A JP S61127210 A JPS61127210 A JP S61127210A
Authority
JP
Japan
Prior art keywords
signal
amplifier
intermediate frequency
output
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24877784A
Other languages
Japanese (ja)
Inventor
Tadashi Takeda
正 竹田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP24877784A priority Critical patent/JPS61127210A/en
Publication of JPS61127210A publication Critical patent/JPS61127210A/en
Pending legal-status Critical Current

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  • Circuits Of Receivers In General (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To obtain stable AM demodulation with less noise even if a small input signal is given or the modulation of an AM modulation signal is increased by using an ultra-narrow band filter amplifier to select a carrier only and multiplying it with an AM intermediate frequency signal to apply synchronous detection. CONSTITUTION:The AM intermediate frequency signal is amplified by an IF amplifier 1' and divided into two. One signal is inputted to a base of a transistor 13 constituting the ultra-narrow band filter amplifier and the carrier component of the extracted AM intermediate frequency signal is fed as one input of a multiplier 2. In this case, the other output of the IF amplifier 1' is fed to one input of the multiplier 2, where multiplication is applied and synchronous detection is attained. A DC component proportional to the intensity of the carrier is extracted from the output, the result is amplified and fed back to the IF amplifier 1' as an AGC control signal so as to obtain an AMIF signal at a prescribed output level and an AF demodulation output is obtained through a low pass filter comprising capacitors 3, 5 and a resistor 4.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はAM受信機の特性向上を計るためのAM復調方
式、とくにそのAM検波器に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an AM demodulation method for improving the characteristics of an AM receiver, and particularly to an AM detector thereof.

(従来例の構成とその問題点) 第1図は従来のPLL回路による搬送波検出とその信号
による乗算器を使用した同期検波方式によるAM検波器
の概略図を示すものである。第1図においてAM中間周
波信号(AMIF信号)を中間周波増幅器(IF増幅器
)1において増幅した後その信号を2つの系統に分離し
て一方を位相比較器6と低域フィルタ7 (LPF)と
電圧制御発振器(VCO)8で構成するP L L回路
に供給してAM信号波の搬送波に同期したVCO8の出
力を得て、この信号とAM中間周波増幅器のもう一方の
信号とを乗算器2によって乗算を行ないその出力をコン
デンサ5.抵抗4で構成する低域フィルタによってA、
M復調信号のAP出力信号を取り出している。この場合
、小入力信号の場合や、AM変調信号の変調度が大きく
なった時、PLL回路のロック外れが起こりやすくなり
、AM復調が出来なくなる。又不要な雑音を発生する原
因となる等の欠点があった。
(Constitution of Conventional Example and Problems thereof) FIG. 1 is a schematic diagram of an AM detector using a synchronous detection method using a conventional PLL circuit to detect a carrier wave and a multiplier based on the signal. In FIG. 1, an AM intermediate frequency signal (AMIF signal) is amplified by an intermediate frequency amplifier (IF amplifier) 1, and then the signal is separated into two systems, one of which is connected to a phase comparator 6 and a low-pass filter 7 (LPF). The signal is supplied to a PLL circuit composed of a voltage controlled oscillator (VCO) 8 to obtain the output of the VCO 8 synchronized with the carrier wave of the AM signal wave, and this signal is combined with the other signal of the AM intermediate frequency amplifier to the multiplier 2. The output is multiplied by capacitor 5. A by the low-pass filter composed of resistor 4,
The AP output signal of the M demodulated signal is extracted. In this case, when the input signal is small or the degree of modulation of the AM modulation signal becomes large, the PLL circuit is likely to lose lock, making AM demodulation impossible. Further, there is a drawback that it causes unnecessary noise to be generated.

(発明の目的) 本発明はシンセサイザ受信機において上記従来の問題点
を解決すること、即ち入力信号が小さい場合やAM変調
信号の変調度が大きくなった場合にも安定した雑音の少
ないAM復調を得ることを目的とする。
(Object of the Invention) The present invention is to solve the above-mentioned conventional problems in a synthesizer receiver, that is, to achieve stable AM demodulation with less noise even when the input signal is small or when the modulation degree of the AM modulation signal becomes large. The purpose is to obtain.

(発明の構成) 上記目的を達するために、本発明はAM中間周波信号の
復調のため乗算器を使用した同期検波を行う。この時の
同期信号を作りだすために、強力な高速AGC回路によ
ってAMIF信号を入力信号レベルの変化に無関係に一
定レベルに押さえて、これから搬送波のみを選択する超
狭帯域フィルタ増幅器を使用して一定レベルの搬送波信
号を取りだしている。
(Structure of the Invention) In order to achieve the above object, the present invention performs synchronous detection using a multiplier for demodulating an AM intermediate frequency signal. In order to create a synchronization signal at this time, a powerful high-speed AGC circuit suppresses the AMIF signal to a constant level regardless of changes in the input signal level, and then an ultra-narrowband filter amplifier that selects only the carrier wave is used to keep the AMIF signal at a constant level. The carrier wave signal is extracted.

即ち、本発明は、AM信号復調回路を、AM中間周波増
幅器の出力を2つの系統に分けて、一方を超狭帯域フィ
ルタ増幅器によって搬送波のみを選択してAM中間周波
信号と乗算して同期検波を行い、この同期検波器の条件
を入力変化に無関係とするために検波出力を利用した高
速AGCをAM中間周波増幅器にかけるように構成して
いる。
That is, in the present invention, the AM signal demodulation circuit divides the output of the AM intermediate frequency amplifier into two systems, and one selects only the carrier wave using an ultra-narrow band filter amplifier and multiplies it with the AM intermediate frequency signal to perform synchronous detection. In order to make the conditions of this synchronous detector independent of input changes, the configuration is such that high-speed AGC using the detected output is applied to the AM intermediate frequency amplifier.

こうして一定条件のもとて同期検波された出力を低域フ
ィルタを通すことによってAF復調出力を得ている。
An AF demodulated output is obtained by passing the synchronously detected output under certain conditions through a low-pass filter.

こうして低いスレッシホールドレベルと深い変調度に対
する安定した受信を確保したAM検波器を提供するもの
である。
In this way, an AM detector is provided which ensures stable reception with a low threshold level and deep modulation depth.

(実施例の説明) 第2図は本発明の実施例を示すものである。第1図と同
一構成箇所には同一番号が付しである。
(Description of Embodiment) FIG. 2 shows an embodiment of the present invention. Components that are the same as those in FIG. 1 are given the same numbers.

1′は高速AGO電圧で増幅度が変化するIF増幅器、
2は乗算器、3,5はコンデンサ、4は抵抗で3.4.
5で構成する低域フィルタは従来例と同一の動作をする
ものである。
1' is an IF amplifier whose amplification degree changes with high-speed AGO voltage;
2 is a multiplier, 3 and 5 are capacitors, and 4 is a resistor. 3.4.
The low-pass filter constituted by No. 5 operates in the same manner as the conventional example.

第2図において、AM中間周波信号は、IF増幅器1′
で増幅されたのち、一方はコンデンサ9を介してトラン
ジスタ13のベースに入力される。トランジスタ13の
コレタク、ベース間に高抵抗11でバイアスを与えると
共に並列に水晶振動子10が接続され、負荷は抵抗12
とする。この時水晶振動子lOの反共振点を中間周波数
に選定するとトランジスタ13は水晶振動子10の反共
振点が最大帰還抵抗となり最大増幅度を示す選択増幅器
として動作する。こうして水晶振動子10の高いQ特性
をもつ超狭帯域フィルタ増幅器が構成される。こうして
取り出されたAM中間周波信号の搬送波成分が乗算器2
の片方の入力として供給される。
In FIG. 2, the AM intermediate frequency signal is transmitted to the IF amplifier 1'
After being amplified by , one of the signals is input to the base of transistor 13 via capacitor 9 . A bias is applied between the collector and the base of the transistor 13 with a high resistance 11, and a crystal resonator 10 is connected in parallel, and the load is a resistor 12.
shall be. At this time, if the anti-resonance point of the crystal oscillator 10 is selected to be the intermediate frequency, the transistor 13 operates as a selective amplifier that exhibits the maximum amplification since the anti-resonance point of the crystal oscillator 10 becomes the maximum feedback resistance. In this way, an ultra-narrow band filter amplifier having a high Q characteristic of the crystal resonator 10 is constructed. The carrier wave component of the AM intermediate frequency signal thus extracted is transmitted to the multiplier 2.
is supplied as one of the inputs.

このとき、IF増幅器1′の出力のもう一方が、乗算器
2の片方の入力として供給されて、乗算器2において乗
算が実施され、同期検波が行われる。
At this time, the other output of the IF amplifier 1' is supplied as one input of the multiplier 2, multiplication is performed in the multiplier 2, and synchronous detection is performed.

この出力は一つはトランジスタ15のベースに接続され
る。トランジスタ15のベース、コレクタ間に高抵抗1
6でバイアスがかけられると同時に、AM中間周波信号
に変調されているAF倍信号通過させるコンデンサ18
が並列に接続されている。この時の負荷は抵抗17であ
る。こうするとAF倍信号コンデンサ18によって短絡
されトランジスタ15は増幅作用をもっていない。この
時DC成分は増幅されるすなわち搬送波の強度に比例す
るDC成分のみを取り出して増幅してこれをAGC制御
信号としてIF増幅器1′に帰還することによってAM
IF信号を一定の出力レベルで得ることが出来る。
One of these outputs is connected to the base of transistor 15. High resistance 1 between the base and collector of transistor 15
A capacitor 18 which is biased at 6 and simultaneously passes the AF multiplied signal which is modulated into an AM intermediate frequency signal.
are connected in parallel. The load at this time is the resistor 17. In this case, the AF multiplier signal capacitor 18 short-circuits the transistor 15, and the transistor 15 has no amplification effect. At this time, the DC component is amplified, that is, only the DC component proportional to the carrier wave intensity is taken out, amplified, and fed back to the IF amplifier 1' as an AGC control signal.
An IF signal can be obtained at a constant output level.

こうして乗算器2で行われる同期検波は一定のレベルで
行われるので、この出力はコンデンサ3゜5と抵抗4に
よって構成される低域フィルタを通すことによってAF
復調出力を得ている。このように構成することによって
安定な同期検波を実現することが可能になったのである
In this way, the synchronous detection performed by multiplier 2 is performed at a constant level, so this output is passed through a low-pass filter consisting of a capacitor 3.5 and a resistor 4, so that the AF
Obtaining demodulated output. This configuration makes it possible to realize stable synchronous detection.

(発明の効果) 以上のように本発明は、超狭帯域フィルタ増幅器を使用
することによって搬送波のみを抽出して。
(Effects of the Invention) As described above, the present invention extracts only the carrier wave by using an ultra-narrow band filter amplifier.

安定した同期検波出力を得ると同時に、AGC回路によ
って常に安定した条件で同期検波を行うことが出来るよ
うになった。特にPLL方式と違って同期外れによるノ
イズの発生が起らないし、AMの高変調時にもその影響
を受けて出力が歪むこともない安定した復調出力を得る
ことが可能となったのである。
At the same time as obtaining stable synchronous detection output, the AGC circuit makes it possible to always perform synchronous detection under stable conditions. In particular, unlike the PLL system, there is no noise generation due to loss of synchronization, and it has become possible to obtain a stable demodulated output without distorting the output even during high AM modulation.

特に周波数シンセサイザ方式による同調点の安定受信機
においてその安定した同期検波器方式として能力を大い
に発揮することが出来る。
Particularly, in a frequency synthesizer system with a stable tuning point receiver, its ability as a stable synchronous detector system can be demonstrated to a great extent.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のPLL方式による搬送波検出とそこで得
られる信号と乗算器による同期検波器方式によるAM検
波器の構成図である。第2図は、本発明の実施例におけ
るAM検波器の構成図である。 1.1′ ・・・ IF増幅器、 2・・・乗算器、 
3゜5 ・・・コンデンサ、 4 ・・・抵抗、 6 
・・・位相比較器、 7−LPF、 8−VCO19,
14,18・・・コンデンサ、10・・・水晶振動子、
 4 、11,12,16,17・・・抵抗、13.1
5・・・トランジスタ。 特許出願人 松下電器産業株式会社 第1図 1           PLビ冷 1し一一−+  
−−J
FIG. 1 is a configuration diagram of an AM detector using a synchronous detector method using carrier wave detection using a conventional PLL method and a signal obtained therefrom and a multiplier. FIG. 2 is a configuration diagram of an AM detector in an embodiment of the present invention. 1.1'... IF amplifier, 2... Multiplier,
3゜5... Capacitor, 4... Resistor, 6
...Phase comparator, 7-LPF, 8-VCO19,
14, 18... Capacitor, 10... Crystal resonator,
4, 11, 12, 16, 17...resistance, 13.1
5...Transistor. Patent applicant: Matsushita Electric Industrial Co., Ltd.
--J

Claims (1)

【特許請求の範囲】 検波出力を利用する高速AGC回路と、 その高速AGC回路によって制御されるAM中間周波増
幅器と、 そのAM中間周波増幅器の出力するAM中間周波信号か
ら搬送波のみを選択する超狭帯域フィルタ増幅器と、 その超狭帯域フィルタ増幅器を通して得られた搬送波信
号とAM中間周波増幅器の出力するAM中間周波信号と
を乗算して同期検波する乗算器と、乗算器の同期検波出
力から復調信号を得る低域フィルタと を備えたことを特徴とするAM検波器。
[Claims] A high-speed AGC circuit that utilizes a detection output, an AM intermediate frequency amplifier controlled by the high-speed AGC circuit, and an ultra-narrow amplifier that selects only a carrier wave from an AM intermediate frequency signal output from the AM intermediate frequency amplifier. A bandpass filter amplifier, a multiplier that performs synchronous detection by multiplying the carrier signal obtained through the ultra-narrowband filter amplifier and the AM intermediate frequency signal output from the AM intermediate frequency amplifier, and a demodulated signal from the synchronous detection output of the multiplier. An AM detector characterized in that it is equipped with a low-pass filter that obtains.
JP24877784A 1984-11-27 1984-11-27 Am detector Pending JPS61127210A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24877784A JPS61127210A (en) 1984-11-27 1984-11-27 Am detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24877784A JPS61127210A (en) 1984-11-27 1984-11-27 Am detector

Publications (1)

Publication Number Publication Date
JPS61127210A true JPS61127210A (en) 1986-06-14

Family

ID=17183225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24877784A Pending JPS61127210A (en) 1984-11-27 1984-11-27 Am detector

Country Status (1)

Country Link
JP (1) JPS61127210A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63193603A (en) * 1986-12-19 1988-08-10 リテフ・ゲゼルフャフト・ミット・ベシュレンクタ・ハフトゥング Synchronous demodulator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63193603A (en) * 1986-12-19 1988-08-10 リテフ・ゲゼルフャフト・ミット・ベシュレンクタ・ハフトゥング Synchronous demodulator

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