JPS61127155A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPS61127155A JPS61127155A JP59249247A JP24924784A JPS61127155A JP S61127155 A JPS61127155 A JP S61127155A JP 59249247 A JP59249247 A JP 59249247A JP 24924784 A JP24924784 A JP 24924784A JP S61127155 A JPS61127155 A JP S61127155A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- coating layer
- semiconductor device
- aluminum coating
- glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【発明の詳細な説明】
１１上裟μ月上！
本発明は半導体装置用リードフレームに係り、さらに詳
しくはパフケージ封止部の片面あるいは両面にイオンプ
レーティングにて形成したアルミニウム被覆層を有する
半導体装置用リードフレームに関するものである。[Detailed description of the invention] 11th grade μ month! The present invention relates to a lead frame for a semiconductor device, and more particularly to a lead frame for a semiconductor device having an aluminum coating layer formed by ion plating on one or both sides of a puff cage sealing portion.
従来の技術
現在使用されている半導体集積回路装置のパッケージ法
は、樹脂封止型、ガラス−セラミック封止型、積層セラ
ミック型の３種に分類される。これら、パッケージ法は
、信頼性および価格の点て長短があり、両者を比較考量
し、用途に応じ゛て巧みに使い分けられている。2. Description of the Related Art Currently used packaging methods for semiconductor integrated circuit devices are classified into three types: resin sealing type, glass-ceramic sealing type, and laminated ceramic type. These packaging methods have advantages and disadvantages in terms of reliability and cost, and they are carefully weighed and used depending on the application.
即ち、信頼性についてこれら３つの方法を比較してみる
と、積層セラミック型が最もすぐれており、次いでガラ
ス−セラミック封止型であり、その次が樹脂封止型であ
る。一方、価格の点ではこの逆の順序となる。この中で
ガラス−セラミック封止型は、信頼性、価格両者におい
て丁度中間的な位置を占めており、従って信頼性と低価
格化の両立が強く望まれているパッケージ法である。That is, when these three methods are compared in terms of reliability, the laminated ceramic type is the best, followed by the glass-ceramic sealing type, and then the resin sealing type. On the other hand, in terms of price, the order is reversed. Among these, the glass-ceramic sealing type occupies an intermediate position in terms of both reliability and cost, and is therefore a packaging method that is strongly desired to achieve both reliability and cost reduction.
第２図は、典型的なガラス−セラミック封止型パッケー
ジの分解部品配列斜視図であり、第３図は、第２図に示
したようなガラス−セラミック封止型パッケージに半導
体装置チップ１を配置した状態を示す断面図である。FIG. 2 is a perspective view of an exploded component arrangement of a typical glass-ceramic sealed package, and FIG. 3 shows a semiconductor device chip 1 in the glass-ceramic sealed package as shown in FIG. It is a sectional view showing the arranged state.
このガラス−セラミック封止型パッケージＡは、半導体
チップ１を収納し、そのメタライズ底面でグイポンディ
ングするための凹部２が中央部に形成されたアルミナな
どのセラミックベース３を有している。また、セラミッ
クベース３の上面周辺部には、鉛ガラスなどの低融点ガ
ラス層４が形成されている。This glass-ceramic sealed package A has a ceramic base 3 made of alumina or the like in which a recess 2 is formed in the center for accommodating a semiconductor chip 1 and for bonding with a metallized bottom surface. Furthermore, a low melting point glass layer 4 such as lead glass is formed around the upper surface of the ceramic base 3 .
このようなセラミックベース３の凹部２を囲むように、
リードフレームから裁断されたリード５が載せられ、こ
れらリード５と半導体チップ１とはアルミニウムワイヤ
６の各端でワイヤボンディングされ、電気的に接続状態
とされている。To surround the recess 2 of such a ceramic base 3,
Leads 5 cut from the lead frame are mounted, and these leads 5 and the semiconductor chip 1 are electrically connected by wire bonding at each end of an aluminum wire 6.
さらに、その上にアルミナなどのセラミックキャップ７
が載せられ、チップ１が気密々封されることになる。こ
のセラミックキャップ７には、半導体チップ１およびワ
イヤ６の部分を囲む凹部８が下側に形成されており、さ
らに、下面周囲には鉛ガラスなどの低融点ガラス層９が
形成されている。Furthermore, a ceramic cap 7 such as alumina is placed on top of it.
is mounted, and the chip 1 is hermetically sealed. A recess 8 surrounding the semiconductor chip 1 and the wire 6 is formed on the lower side of the ceramic cap 7, and a low melting point glass layer 9 such as lead glass is formed around the lower surface.
従って、セラミックベース３とセラミックキャップ７と
は低融点ガラス層４と９とでリード５を間に挟むように
重ねられ、次いで加熱されて低融点ガラス層４と９とが
リード５を固定しつつ互いに融着して、セラミックベー
ス３とセラミックキャップ７とを封止する。Therefore, the ceramic base 3 and the ceramic cap 7 are stacked with the low melting point glass layers 4 and 9 with the lead 5 sandwiched between them, and then heated so that the low melting point glass layers 4 and 9 fix the lead 5 while The ceramic base 3 and the ceramic cap 7 are sealed by being fused together.
発明が解決しようとする問題点
ところで、現在の半導体集積回路装置においては、小型
化、多機能化の動向がみられ、上記のガラス−セラミッ
ク封止型パッケージの半導体集積回路においてもその影
響を受けている。Problems to be Solved by the Invention Incidentally, there is a trend toward miniaturization and multifunctionalization in current semiconductor integrated circuit devices, and the above-mentioned glass-ceramic sealed package semiconductor integrated circuits are also affected by this trend. ing.
即ち、多機能化に応じて半導体集積回路チップそのもの
が大きくなり、小型化を指向してパッケージ形態がＤＩ
Ｐ型（２方向外部リード）からＱｕａｄ型（４方向外部
リード）へ移行するとともに、ガラス封止部面積を小さ
くする傾向を示している。In other words, semiconductor integrated circuit chips themselves have become larger as they become more multi-functional, and packages are becoming more compact as they become more compact.
There is a shift from the P type (two-way external leads) to the Quad type (four-directional external leads), and there is a tendency to reduce the area of the glass sealing part.
この傾向と前述の信頼性および価格と照らし合せると、
ガラス封止部面積の減少に伴う気密性の劣化を防止する
とともに、Ｑｕａｄ型への対応を可能とする廉価なリー
ドフレームの開発が強く望まれているのである。本発明
の目的もこの点にある。Comparing this trend with the reliability and price mentioned above,
There is a strong desire to develop an inexpensive lead frame that can prevent the deterioration of airtightness due to a reduction in the area of the glass sealing part and also be compatible with the Quad type. This is also the purpose of the present invention.
問題点を解決するための手段
そこで本発明者らは、ガラス封止部面積が減少してもパ
ッケージの気密性を十分確保でき、且つＱｕａｄ型への
対応が十分に可能である廉価な半導体装置用リードフレ
ームを得るべく検討した結果、パッケージ封止部の片面
あるいは両面にアルミニウム被覆層をイオンプレーティ
ングにて形成せしめることが上記の目的とするリードフ
レームを開発する上で極めて有効であることを見出し、
本発明を完成するに・・至った。Means for Solving the Problems Therefore, the present inventors have developed an inexpensive semiconductor device that can sufficiently ensure the airtightness of the package even if the area of the glass sealing part is reduced, and that is fully compatible with the Quad type. As a result of our study to obtain a lead frame for the above purpose, we found that forming an aluminum coating layer on one or both sides of the package sealing part by ion plating is extremely effective in developing the lead frame for the above purpose. heading,
We have now completed the present invention.
即ち、本発明のリードフレームは半導体装置用リードフ
レームであって、リードフレーム本体と、そのパッケー
ジ封止部の少なくとも片面に設けられたアルミニウム被
覆層とで構成され、該アルミニウム被覆層は厚さが５μ
ｍ以下であり、バイアス電圧１ＫＶ以上、蒸着速度２０
０八／秒以下もしくは５００八／秒以下の条件下でのイ
オンプレーティングにより形成されたものであることを
特徴とする。That is, the lead frame of the present invention is a lead frame for a semiconductor device, and is composed of a lead frame body and an aluminum coating layer provided on at least one side of the package sealing part, and the aluminum coating layer has a thickness of 5μ
m or less, bias voltage 1KV or more, deposition rate 20
It is characterized by being formed by ion plating under conditions of 08/sec or less or 5008/sec or less.
本発明のリードフレームにおいて、リードフレーム本体
は、鉄、鉄−ニッケノペ銅合金などの従来公知の各種材
料から形成することができ、特に制限はない。In the lead frame of the present invention, the lead frame body can be formed from various conventionally known materials such as iron and iron-Nikkenope copper alloy, and is not particularly limited.
また、本発明のリードフレームは各種の半導体装置のパ
ッケージに有利に応用でき、特に低融点ガラス封止型半
導体装置、即ちいわゆるサーディツプ（ＣＥＲ−ＤＩＰ
）ＩＣなどに適用するのに適したものである。In addition, the lead frame of the present invention can be advantageously applied to packages for various semiconductor devices, particularly for low-melting glass-sealed semiconductor devices, ie, so-called CER-DIP.
) It is suitable for application to ICs, etc.
イオンプレーティング法は、蒸着の際の付着強度が高く
、回り込み性が大きいなどの各種興味ある利点を有して
いることから最近注目されている薄膜形成技術であり、
直流法、高周波法、熱陰極法等各種の方法があり、いず
れの方法も本発明のリードフレームにおけるアルミニウ
ム被覆層形成のために利用することができる。The ion plating method is a thin film formation technology that has recently attracted attention because it has various interesting advantages such as high adhesion strength during vapor deposition and large wraparound properties.
There are various methods such as a direct current method, a high frequency method, and a hot cathode method, and any of these methods can be used to form the aluminum coating layer in the lead frame of the present invention.
詐月
本発明は、最近のＩＣ等の多機能化、小型化の動向に伴
う、パッケージ形態の変遷に応じたガラス封止部の面積
減少に十分対応し得るリードフレームを開発することを
意図するものであるが、この目的は上記のようにリード
フレーム本体のガラス封止部の少なくとも片面にアルミ
ニウム被覆層を設けることにより達成される。The present invention is intended to develop a lead frame that can sufficiently cope with the reduction in the area of the glass sealing part in response to changes in package form, which is accompanied by the recent trend of multi-functionalization and miniaturization of ICs, etc. However, this object is achieved by providing an aluminum coating layer on at least one side of the glass sealing portion of the lead frame body as described above.
本願出願人は、超音波ワイヤボンディングに対するリー
ドフレームの適合性、並びにガラス封止部面積の減少に
伴うパッケージ気密性の低下を改善する目的で、物理蒸
着法によりアルミニウム合金（ＣｕＳＭｎおよびＳｉの
少なくとも１種を含有する）膜をワイヤボンディング部
およびガラス封止部に設けたリードフレームを開発し、
既に特願昭５９−６０８５８号として出願しており、ガ
ラス封止部にアルミニウム合金膜を設けることに基きパ
ッケージの気密性、接合力が改善されることを立証して
いる。In order to improve the suitability of a lead frame for ultrasonic wire bonding and the deterioration of package airtightness due to a decrease in the glass sealing area, the applicant has developed an aluminum alloy (at least one of CuSMn and Si) using a physical vapor deposition method. We developed a lead frame with a film (containing seeds) in the wire bonding part and the glass sealing part.
This patent has already been filed as Japanese Patent Application No. 59-60858, and it has been proven that the airtightness and bonding strength of the package can be improved by providing an aluminum alloy film on the glass sealing part.
本発明では更に研究を進めて特定の条件下においてイオ
ンプレーティングによりアルミニウム被覆層を設けるこ
とにより更に一層気密性、接合性において改善され、ひ
いてはパッケージの信頼性の向上を図ることができるこ
とを見出した。In the present invention, we conducted further research and found that by providing an aluminum coating layer by ion plating under specific conditions, it was possible to further improve airtightness and bonding properties, and in turn, improve the reliability of the package. .
該アルミニウム被覆層の厚さは５μｍ以下であることが
重要であり、これはパッケージの封着強度並びに気密性
等を確保する上で臨界的な条件である。It is important that the thickness of the aluminum coating layer is 5 μm or less, which is a critical condition for ensuring the sealing strength and airtightness of the package.
更に、該アルミニウム被覆層は所定の条件下でイオンプ
レーティングすることが最も望ましく、これら条件も臨
界的なものである。Furthermore, it is most desirable to ion plate the aluminum coating layer under predetermined conditions, and these conditions are also critical.
このイオンプレーティング法における上記条件が臨界的
であることを示し、かつ従来汎用されていたロールクラ
ッド法、真空蒸着法と比較して、イオンプレーティング
法の有利さを実証するために以下の表１に示すような条
件下で上記薄膜形成法を実施し、結果を同表に併せて示
した。In order to show that the above conditions in this ion plating method are critical and to demonstrate the advantages of the ion plating method compared to the conventionally widely used roll cladding method and vacuum evaporation method, the following table is presented. The above thin film forming method was carried out under the conditions shown in 1, and the results are also shown in the same table.
表１
上記表の結果から、本発明において採用したイオンプレ
ーティング法、即ち、バイアス電圧が１ＫＶ以上で、ア
ルミニウム被覆層の厚さが５μｍ以下且つ、蒸着速度が
２００八／秒以下若しくは５００八／秒以上の場合、他
の方法、条件より封着強度及び気密性が著しく向上する
こと、またこれら条件が本発明において臨界的であるこ
とが判った。Table 1 From the results in the above table, it can be seen that the ion plating method adopted in the present invention, that is, the bias voltage is 1 KV or more, the thickness of the aluminum coating layer is 5 μm or less, and the deposition rate is 2008/sec or less or 5008/sec or less. It has been found that when the time is longer than 2 seconds, the sealing strength and airtightness are significantly improved compared to other methods and conditions, and that these conditions are critical in the present invention.
表１の結果からはアルミニウム被覆層の厚さは上限であ
る５μｍが規定されるのみであるが、一般にワイヤボン
ディング部にもＡＩ被覆層を設け、ボンディング性の改
善を行っており、これを本発明のイオンプレーティング
法によるガラス封止部のアルミニウム被覆層の形成操作
とは別に実施すると、ＡＩの被覆操作を２重に行わねば
ならない。The results in Table 1 only specify an upper limit of 5 μm for the thickness of the aluminum coating layer, but generally an AI coating layer is also provided at the wire bonding part to improve bonding properties, and this is If performed separately from the operation of forming the aluminum coating layer of the glass sealing part by the ion plating method of the invention, the AI coating operation must be performed twice.
従って、好ましくはこれらのワイヤボンディング部およ
びガラス封止部の被覆を同時に行う。Therefore, preferably the wire bonding portion and the glass sealing portion are coated at the same time.
ワイヤボンディング部にＡＩ被被覆設け、ボンディング
特性を改善するためには該被覆の厚さは最低１．５μｍ
なければならない。従って、ワイヤボンディング部及び
ガラス封止部のアルミニウム被覆を同時に行う場合には
、アルミニウム被覆層の厚さを１．５〜５μｍの範囲に
制限する必要があり、これによってガラス封止性とワイ
ヤボンディング性の改良を同時に行うことができる。尚
、ガラス封止部とワイヤボンディング部の被覆を別々に
実施する場合にはガラス封止部におけるアルミニウム層
の厚さは、当然のことながら、１．５μｍ以下であって
も有効である。The wire bonding area is coated with AI, and the thickness of the coating must be at least 1.5 μm in order to improve the bonding characteristics.
There must be. Therefore, when coating the wire bonding part and the glass sealing part with aluminum at the same time, it is necessary to limit the thickness of the aluminum coating layer to a range of 1.5 to 5 μm, which improves the glass sealing property and the wire bonding property. It is possible to improve sex at the same time. In addition, when the glass sealing part and the wire bonding part are coated separately, it is of course effective even if the thickness of the aluminum layer in the glass sealing part is 1.5 μm or less.
特に、現在広く行われているロールクラッド法では品質
面で問題があるだけでなく、アルミニウム被覆層がスト
ライブ状とならざるを得ず、今後のパッケージ形態であ
るＱｕａｄ型にも追従できないという欠陥がある。In particular, the currently widely used roll cladding method not only has problems in terms of quality, but also has the disadvantage that the aluminum coating layer has to be in the form of stripes, making it impossible to follow the quad-type package format that will be adopted in the future. There is.
尚、上記表１の如き各種薄膜形成法、並びに条件下での
封止性の差異については、現在のところその原因は定か
ではないが、イオンプレーティング法で形成したアルミ
ニウム薄膜が他の方法より得られたものと比べて結晶粒
径が小さく、粒界が多いことによりアルミニウム被覆層
とガラスとの間の拡散が促進されるためであろうと考え
られる。Regarding the differences in sealing performance between various thin film forming methods and conditions as shown in Table 1 above, the cause is currently unknown, but aluminum thin films formed by ion plating are superior to other methods. It is thought that this is because the crystal grain size is smaller than that of the obtained one and there are many grain boundaries, which promotes diffusion between the aluminum coating layer and the glass.
かくして、本発明によれば、該半導体装置用リードフレ
ーム上のガラス封止部に相当する位置にアルミニウム被
覆層を形成するが、これは、アルミニウムを所定の条件
下でイオンプレーティングすることにより実施でき、そ
れによって上述した欠点をことごとく解消した半導体装
置用リードフレームを提供することができるのである。Thus, according to the present invention, an aluminum coating layer is formed at a position corresponding to the glass sealing part on the lead frame for a semiconductor device, but this is carried out by ion plating aluminum under predetermined conditions. As a result, it is possible to provide a lead frame for a semiconductor device that eliminates all of the above-mentioned drawbacks.
以下、本発明を第１図を参照しつつ更に詳細に説明する
。第１図は本発明によるリードフレームを使用した半導
体集積回路装置のパッケージを断面で示した図である。Hereinafter, the present invention will be explained in more detail with reference to FIG. FIG. 1 is a cross-sectional view of a package of a semiconductor integrated circuit device using a lead frame according to the present invention.
同図において、第２図および第３図と同一部分について
は、同一番号を付してその説明を省略する。In this figure, parts that are the same as those in FIGS. 2 and 3 are given the same numbers and their explanations will be omitted.
即ち、本発明ではリードフレーム１１のガラス封止部１
２に相当する部分に、バイアス電圧１ＫＶ以上、蒸着速
度２０ＯＡ ／秒以下もしくは５００八／秒以上の条件
下で、イオンプレーティングにて馳被覆層１３を厚さ１
．５〜５μｍで形成したものである。That is, in the present invention, the glass sealing portion 1 of the lead frame 11
2, a coating layer 13 with a thickness of 1 is applied by ion plating under the conditions of a bias voltage of 1 KV or more and a deposition rate of 20 OA/sec or less or 500 OA/sec or more.
．． It is formed to have a thickness of 5 to 5 μm.
第１図においては、このアルミニウム被覆層１３をパッ
ケージ封止部の片面にのみ設けた場合を示したが、この
被覆層は勿論両面に形成されていてもよい。Although FIG. 1 shows the case where this aluminum coating layer 13 is provided only on one side of the package sealing part, this coating layer may of course be formed on both sides.
実施例 以下、本発明を実施例により更に具体的に説明する。Example EXAMPLES Hereinafter, the present invention will be explained in more detail with reference to Examples.
板厚が０．２５ｍｍである４２％Ｎｉ−Ｆｅ合金からな
るす−ドフレーム基材に高周波イオンプレーティング法
により、初期真空度を５ Ｘ １Ｏ−６Ｔｏｒｒ、アル
ゴンガス導入後のガス圧を５ Ｘ １０−’Ｔｏｒｒと
し、高周波出力２００Ｗにてアルゴンガスを励起し、５
分間のイオンボンバードを施した後そのまま、バイアス
電圧を１．５ＫＶ、蒸着速度１５０八／秒の条件にて、
アルミニウム被覆層を３μｍ厚に形成した。A wood frame base material made of 42% Ni-Fe alloy with a plate thickness of 0.25 mm was coated by high-frequency ion plating at an initial vacuum level of 5 x 10-6 Torr and a gas pressure of 5 x after introducing argon gas. 10-' Torr, excited argon gas with a high frequency output of 200 W, and
After performing ion bombardment for 1 minute, the bias voltage was 1.5 KV and the deposition rate was 1508/sec.
An aluminum coating layer was formed to a thickness of 3 μm.
一方、同一基材に５ Ｘｌ０−６Ｔｏｒｒ、蒸着速度１
５０八／秒の条件で真空蒸着法にて、同じ厚さのアルミ
ニウム被覆層を形成したリードフレームと、ロールクラ
ッド法による６μｍ厚のアルミニウム被覆層を形成した
リードフレームを用意した。On the other hand, on the same substrate, 5 Xl0-6 Torr, deposition rate 1
A lead frame was prepared in which an aluminum coating layer of the same thickness was formed using a vacuum evaporation method under conditions of 508/sec, and a lead frame was prepared in which an aluminum coating layer was formed with a thickness of 6 μm using a roll cladding method.
これら３つのリードフレームを用いてアルミナ基材、Ｐ
ｂＯＢ２Ｏ３系低融点ガラスにより封止を行ない熱衝撃
サイクル試験後Ｈｅ１Ｊ−クチストを行なった結果、ロ
ールクラッド法、真空蒸着法によりアルミニウム被覆層
を形成したリードフレームについてはリークが認められ
たが、本発明に従ってイオンプレーティングによりアル
ミニウム被覆層を形成したリードフレームについては、
リ−りは全くＳ忍められなかった。Using these three lead frames, alumina base material, P
As a result of sealing with bOB2O3-based low melting point glass and conducting He1J-cutist after a thermal shock cycle test, leakage was observed for the lead frame in which an aluminum coating layer was formed by the roll clad method or the vacuum evaporation method, but the present invention For lead frames with aluminum coating layer formed by ion plating according to
Lily couldn't stand S at all.
発明の効果
以上から明らかなように、半導体装置用リードフレーム
において、そのガラス封止部に対応する部分に、本発明
に従って上記所定のイオンプレーティング条件下で片面
あるいは両面にアルミニウム被覆層を形成せしめること
により、封止信頼性を著しく向上させることができ、且
つ今後のパッケージ形態の動向として注目されるＱｕａ
ｄ型にも十分追従が可能な半導体装置用リードフレーム
を提供することができるのである。Effects of the Invention As is clear from the above, in a lead frame for a semiconductor device, an aluminum coating layer is formed on one or both sides of the portion corresponding to the glass sealing portion under the above-mentioned predetermined ion plating conditions according to the present invention. As a result, sealing reliability can be significantly improved, and Qua
Therefore, it is possible to provide a lead frame for a semiconductor device that can sufficiently follow the D-type.
第１図は本発明によるリードフレームを使用したガラス
−セラミック封止型パ゛ツケージの断面図であり、第２
図は従来のガラス−セラミック封止型パッケージの分解
部品配列斜視図であり、第３図は第２図のパッケージの
断面図である。
（主な参照番号）
１ 半導体チップ、 ２ 凹部、
３ セラミックベース、
４．９ 低融点ガラス層、 ５ リード、６ アルミニ
ウムワイヤ、
７ セラミックキャップ、 ８ 凹部、１１ リー
ドフレーム、 １２ ガラス封止部、１３ アルミ
ニウム被覆層、
１４ ワイヤボンディング部
特許出願人 住友電気工業株式会社
新技術開発事業団
村山 洋−FIG. 1 is a sectional view of a glass-ceramic sealed package using a lead frame according to the present invention, and FIG.
The figure is a perspective view of an exploded component arrangement of a conventional glass-ceramic sealed package, and FIG. 3 is a sectional view of the package of FIG. 2. (Main reference numbers) 1 semiconductor chip, 2 recess, 3 ceramic base, 4.9 low melting point glass layer, 5 lead, 6 aluminum wire, 7 ceramic cap, 8 recess, 11 lead frame, 12 glass sealing part, 13 Aluminum coating layer, 14 Wire bonding department Patent applicant Hiroshi Murayama, New Technology Development Corporation, Sumitomo Electric Industries, Ltd.
Claims (4)
少なくとも片面に設けられたアルミニウム被覆層とを具
備し、該アルミニウム被覆層は厚さが５μｍ以下であり
、バイアス電圧１ＫＶ以上、蒸着速度２００Å／秒以下
もしくは５００Å／秒以上なる条件下でのイオンプレー
ティングによって形成されたものであることを特徴とす
る半導体装置用リードフレーム。(1) It comprises a lead frame main body and an aluminum coating layer provided on at least one side of the package sealing part, the aluminum coating layer has a thickness of 5 μm or less, a bias voltage of 1 KV or more, and a deposition rate of 200 Å/2. 1. A lead frame for a semiconductor device, characterized in that it is formed by ion plating under conditions of less than a second or more than 500 Å/second.
徴とする特許請求の範囲第１項記載の半導体装置用リー
ドフレーム。(2) The lead frame for a semiconductor device according to claim 1, wherein the semiconductor device is of a low melting point glass sealed type.
アルミニウム被覆層を設けたことを特徴とする特許請求
の範囲第１項または第２項に記載の半導体装置用リード
フレーム。(3) The lead frame for a semiconductor device according to claim 1 or 2, wherein an aluminum coating layer is also provided on a wire bonding portion of the lead frame.
ｍの範囲内にあることを特徴とする特許請求の範囲第３
項記載の半導体装置用リードフレーム。(4) The thickness of the aluminum coating layer is 1.5 to 5.0μ
Claim 3 characterized in that it is within the range of m.
A lead frame for a semiconductor device as described in .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59249247A JPS61127155A (en) | 1984-11-26 | 1984-11-26 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59249247A JPS61127155A (en) | 1984-11-26 | 1984-11-26 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61127155A true JPS61127155A (en) | 1986-06-14 |
Family
ID=17190112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59249247A Pending JPS61127155A (en) | 1984-11-26 | 1984-11-26 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61127155A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0275122A2 (en) * | 1987-01-16 | 1988-07-20 | Sumitomo Electric Industries Limited | Chip package transmissive to ultraviolet light |
-
1984
- 1984-11-26 JP JP59249247A patent/JPS61127155A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0275122A2 (en) * | 1987-01-16 | 1988-07-20 | Sumitomo Electric Industries Limited | Chip package transmissive to ultraviolet light |
| US5063435A (en) * | 1987-01-16 | 1991-11-05 | Sumitomo Electric Industries, Ltd. | Semiconductor device |
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