JPS617645A - Metal material for semiconductor device - Google Patents

Metal material for semiconductor device

Info

Publication number
JPS617645A
JPS617645A JP12827884A JP12827884A JPS617645A JP S617645 A JPS617645 A JP S617645A JP 12827884 A JP12827884 A JP 12827884A JP 12827884 A JP12827884 A JP 12827884A JP S617645 A JPS617645 A JP S617645A
Authority
JP
Japan
Prior art keywords
glass
sealing
metal material
metal layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12827884A
Other languages
Japanese (ja)
Inventor
Yoshihiko Doi
良彦 土井
Akira Otsuka
昭 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP12827884A priority Critical patent/JPS617645A/en
Publication of JPS617645A publication Critical patent/JPS617645A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable to obtain a state of film junction by a method wherein the surfaces of the sealing parts consisting of a metal material and glass are respectively formed with an amorphous metal layer. CONSTITUTION:The lead parts 38 of lead frames are placed on a low-melting point glass layer 36 encircling the recessed part 32 of a ceramic base 30. An amorphous metal layer 42 is formed on the surface of at least one side of glass sealing parts 40, which are located on the layer 36. Moreover, a recessed part 48 is formed in a ceramic cap 46, which is superposed on the base 30, corresponding to the recessed part 32 of the base 30, and a semiconductor chip 34 and Al wires 44 are housed in the space, which is defined by the recessed parts 32 and 48. The cap 46 is superposed on the base 30 in such a way as to hold the lead parts 38 between the cap 46 and the base 30 and a sealing treatment is performed. An amorphous metal layer provided on the surface of a metal material as mentioned above is larger in activity, as compared to a crystalline metal layer, and is easy to generate diffusion on a junction face with sealing glass. As a result, a highly reliable junction is obtained at the respective junction face and a highly reliable sealing can be realized.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置のリードフレームなどに使用でき
る金属材料に関するものであり、更に詳しく述べるなら
ば、半導体装置のパッケージ組立実装工程においてパッ
ケージの封止信頼性を飛躍的に向上することができる半
導体装置用金属材料に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a metal material that can be used for lead frames of semiconductor devices. The present invention relates to a metal material for semiconductor devices that can dramatically improve reliability.

従来の技術 現在使用されている半導体集積回路装置のパッケージ法
は、大別すると、樹脂封止型、ガラス−セラミック封止
型、積層セラミック型に分類される。これらパッケージ
法は、信頼性および価格の点で長短があり、両者を比較
考量して用途に応じて巧に使い分けられている。即ち、
信頼性は、王者の方法の比較では、積層セラミック型が
最も優れ、次いでガラス−セラミック封止型であり、そ
の次が樹脂封止型である。一方、価格の面ではこの逆で
ある。この中でガラス−セラミック封止型が、信頼性、
価格において丁度中間的な位置に存在し、信頼性と低価
格化の両立が強く望まれているパッケージである。
BACKGROUND OF THE INVENTION The packaging methods for semiconductor integrated circuit devices currently in use can be broadly classified into resin sealing type, glass-ceramic sealing type, and laminated ceramic type. These packaging methods have advantages and disadvantages in terms of reliability and cost, and they are carefully weighed and used depending on the application. That is,
In terms of reliability, when comparing the best methods, the laminated ceramic type is the best, followed by the glass-ceramic sealing type, and then the resin sealing type. On the other hand, in terms of price, the opposite is true. Among these, the glass-ceramic sealed type is highly reliable and
It is a package that is in the middle of the price range and is highly desired for its combination of reliability and low cost.

第2図は、そのガラス−セラミック封止型パッケージの
分解部品配列斜視図である。但し、半導体装置及びアル
ミニウムワイヤなど一部は省略して示しである。
FIG. 2 is a perspective view of the exploded parts arrangement of the glass-ceramic sealed package. However, some parts such as semiconductor devices and aluminum wires are omitted from illustration.

このガラス−セラミック封止型パッケージは、半導体チ
ップを納めてメタライズ底面にグイボンディングする凹
部12が中央に形成されたアルぜすのようなセラミック
ベース14を有している。そのセラミックベース14の
上面周囲には、鉛ガラスのような低融点ガラス層16が
形成されている。
This glass-ceramic sealed package has a ceramic base 14, such as an aluminum alloy, with a recess 12 formed in the center in which a semiconductor chip is housed and bonded to the metallized bottom surface. A low melting point glass layer 16 such as lead glass is formed around the upper surface of the ceramic base 14 .

そのようなセラミックベース14の凹部12を囲むよう
に、リードフレームから裁断されるリード18が載せら
れ、それらリード18と半導体チップとにアルミニウム
ワイヤの各端がワイヤボンディングされている。更に、
その上に、アルミナのようなセラミックキャップ20が
載せられている。そのセラミックキャップ20は、半導
体チップとアルミニウムワイヤの部分を囲む凹部が下側
に形成され、更に、下面周囲に鉛ガラスのような低融点
ガラス層22が形成されている。
Leads 18 cut from a lead frame are placed so as to surround the recess 12 of the ceramic base 14, and each end of an aluminum wire is wire-bonded to the leads 18 and the semiconductor chip. Furthermore,
A ceramic cap 20 such as alumina is placed thereon. The ceramic cap 20 has a recess formed on the lower side surrounding the semiconductor chip and the aluminum wire, and further has a low melting point glass layer 22 such as lead glass formed around the lower surface.

従って、セラミックベース14とセラミックキャップ2
0とが、低融点ガラス層16と22でリード18を間に
挟むように重ねられて、加熱されて低融点ガラス層16
と22がリード18を固定しつつ互いに融着して、セラ
ミックベース14とセラミックキャップ22とを封止す
る。
Therefore, the ceramic base 14 and the ceramic cap 2
0 are stacked with the low melting point glass layers 16 and 22 with the lead 18 in between, and heated to form the low melting point glass layer 16.
and 22 are fused to each other while fixing the lead 18, thereby sealing the ceramic base 14 and the ceramic cap 22.

一方、現在の半導体集積回路装置の動向は、小型化、多
機能化が叫ばれ、上記のガラス−セラミック封止型パッ
ケージの半導体集積回路においてもその波を受けている
。このことは、多機能化に応じて半導体集積回路チップ
そのものが大きくなり、外部端子接続用リード数が増え
ることを意味し、また、小型化に対応して、DIP型(
2方向外部リード)からQuad型(4方向外部リード
)への移行や外部端子接続用リード数の増大に伴うパッ
ケージのガラス封止部面積の減少等の傾向がある。
On the other hand, current trends in semiconductor integrated circuit devices call for miniaturization and multifunctionalization, and the above-mentioned glass-ceramic sealed package semiconductor integrated circuits are also affected by this trend. This means that as the semiconductor integrated circuit chip becomes more multifunctional, the size of the semiconductor integrated circuit chip itself increases, and the number of leads for connecting external terminals increases.
There are trends such as a shift from a 2-way external lead) to a Quad type (4-way external lead) and a decrease in the area of the glass-sealed part of the package due to an increase in the number of external terminal connection leads.

しかしながら、このようにガラス封止部面積が減少する
と、ガラス同志によって与えられるセラミックベースと
セラミックキャップとの接合力が低下する。その接合力
の低下を、ガラスとリードフレームとの接合力によって
補うことができれば、問題ないが、現在使用されている
リードと低融点ガラスとの接合力は低融点ガラス同志の
接合力に比べて相当低い。そのために、外部端子リード
即ち第2図の例におけるリード18の数が増大すれば、
ベースとキャップとの接合面においてリードを間に挟み
込んでいない部分の面積が減少するため、全体としての
接合力即ち気密性が低下する。
However, when the area of the glass sealing portion decreases in this way, the bonding force between the ceramic base and the ceramic cap provided by the glass particles decreases. There would be no problem if this decrease in bonding strength could be compensated for by the bonding force between the glass and the lead frame, but the bonding force between the currently used leads and low-melting glass is weaker than the bonding force between low-melting glasses. Quite low. Therefore, if the number of external terminal leads, that is, the leads 18 in the example of FIG. 2 increases,
Since the area of the bonded surface between the base and the cap where the lead is not sandwiched between them is reduced, the overall bonding force or airtightness is reduced.

更に、現在のリードフレームとガラスとの接合では、半
導体装置の組立工程や使用時における熱サイクルによっ
て、接着性か更に低下し、リークに至る問題もある。
Furthermore, in the current bonding between lead frames and glass, there is a problem in that the adhesiveness further deteriorates due to thermal cycles during the assembly process and use of the semiconductor device, leading to leakage.

発明が解決しようとする問題点 以上述べたように、従来使用されているリードフレーム
では、ガラスとの接着力が低いために、リードの数が増
大するに伴いパッケージの封止信頼性が十分でなくなる
傾向にある。
Problems to be Solved by the Invention As mentioned above, conventionally used lead frames have low adhesion to glass, so as the number of leads increases, the sealing reliability of the package is not sufficient. It tends to disappear.

そこで、本発明は、ガラスとの接着力が高く且つ信頼性
があり、リードフレームとして使用することが可能な金
属材料を提供せんとするものである。
Therefore, the present invention aims to provide a metal material that has high adhesion to glass, is reliable, and can be used as a lead frame.

更に詳述するならば、本発明は、半導体装置パッケージ
におけるガラス封止部面積が減少しても、パッケージの
無密性に十分な信頼性を与えることができるり、−ドフ
レームをつくることを可能とする金属材料を提供せんと
するものである。
More specifically, even if the area of the glass sealing part in a semiconductor device package is reduced, the present invention can provide sufficient reliability to the hermeticity of the package, and can make it possible to create a closed frame. The aim is to provide a metal material that makes it possible.

問題点を解決するための手段 そこで、本件出願の発明者らは、金属材料とガラスとの
封止信頼性について、種々検討した結果、次のような事
実を確認した。
Means for Solving the Problems The inventors of the present application conducted various studies on the sealing reliability between metal materials and glass, and as a result, confirmed the following fact.

(1)ガラス封止時、金属材料とガラスとの接合性より
も、金属材料の表面を非晶質・化したときのその金属材
料の非晶質化面とガラスとの接合性の方が飛躍的に上昇
する。
(1) When sealing glass, the bonding ability between the amorphous surface of the metal material and the glass when the surface of the metal material is made amorphous is better than the bonding ability between the metal material and the glass. rise dramatically.

(2)金属材料表面を非晶質化する場合だけでなく、金
属材料表面に非晶質金属被膜を付着した場合も、同様の
ガラス接合性の改善効果が得られる。
(2) A similar effect of improving glass bonding properties can be obtained not only when the surface of the metal material is made amorphous, but also when an amorphous metal film is attached to the surface of the metal material.

(3)  これらの非晶質金属層の厚みは、少なくとも
、0.05μm以上あれば、ガラス封止性の向上に効果
がある。
(3) If the thickness of these amorphous metal layers is at least 0.05 μm or more, it is effective in improving glass sealing properties.

これらの確認できた事実に基き、9本発明者らは、ガラ
ス−セラミック封止型の半導体集積回路装置の信頼性の
向上をねらって、種々検討した結果、本発明に至った。
Based on these confirmed facts, the present inventors conducted various studies aimed at improving the reliability of glass-ceramic sealed semiconductor integrated circuit devices, and as a result, they arrived at the present invention.

すなわち、本発明によるならば、ガラスとの封止部の表
面に非晶質金属層を設けたことを特徴とする半導体装置
用金属材料が提供される。
That is, according to the present invention, there is provided a metal material for a semiconductor device characterized in that an amorphous metal layer is provided on the surface of the sealing portion with glass.

昨月 このように金属材料のガラスとの少なくとも封止部表面
を非晶質金属層とすることによりガラスとの封止性が向
上する。その理由は、次の如くである。
By making at least the surface of the sealing portion of the metal material with glass an amorphous metal layer as described last month, the sealing performance with glass is improved. The reason is as follows.

一般に、ガラス封止性を支配する重要な因子としては、
ガラスの金属材料に対するぬれ性の良否が挙げられ、ぬ
れ性が良好な場合には、接合界面部に拡散層が生じ強固
な接合状態が得られることが知られている。
In general, the important factors governing glass sealability are:
This depends on the wettability of glass to the metal material, and it is known that when the wettability is good, a diffusion layer is formed at the bonding interface and a strong bonded state is obtained.

ところで、低融点ガラス封止パッケージでは、半導体素
子に対する熱の影響を小さくするために、500℃以下
の低温でガラス−リードフレーム間の接合が行われるの
で、かかる拡散層は、形成されないのが一般的であった
By the way, in low melting point glass sealed packages, the glass and lead frame are bonded at a low temperature of 500°C or less in order to reduce the effect of heat on the semiconductor element, so such a diffusion layer is generally not formed. It was a target.

そこで、封止部の減少をカバーして高い封止信頼性を得
るためには、ガラス−リードフレーム間の拡散接合が生
じやすい様にすることが必要である。
Therefore, in order to compensate for the decrease in the sealing portion and obtain high sealing reliability, it is necessary to facilitate diffusion bonding between the glass and the lead frame.

本発明において、金属材料表面に設けた非晶質金属層は
、結晶質金属層に比して、活性度が著しく大きく、封止
ガラスとの接合界面での拡散が生じやすく、それだけ、
信頼性の高い接合が得られ、従来の金属とガラスとの封
止性に比較して極めて高い信頼性のある封止を実現でき
るものと考えられる。
In the present invention, the amorphous metal layer provided on the surface of the metal material has significantly higher activity than the crystalline metal layer, and is more likely to diffuse at the bonding interface with the sealing glass.
It is believed that a highly reliable bond can be obtained and that extremely reliable sealing can be achieved compared to conventional sealing properties between metal and glass.

なお、このように金属材料のガラス封止部表面に非晶質
の金属層を設ける方法としては、湿式メッキ、PVD法
、又はCVD法などのコーティング法によって金属材料
表面に非晶質金属層を被覆する方法を使用してもよいし
、金属材料の表面層を、イオンボンバード、電子線ボン
バード、或いはレーザービーム照射などにより非晶質化
する方法を使用してもよい。
In addition, as a method of providing an amorphous metal layer on the surface of the glass sealing part of a metal material in this way, an amorphous metal layer is formed on the surface of the metal material by a coating method such as wet plating, PVD method, or CVD method. A coating method may be used, or a method of making the surface layer of the metal material amorphous by ion bombardment, electron beam bombardment, laser beam irradiation, or the like may be used.

又、非晶質表面層の厚みは、本発明の効果の面から、0
,05μm以上で充分である。一方、非晶質層を必要以
上に厚くすることは、非晶質金属層形成コストが上るの
みで、実用的ではない。そこで、接合信頼性の効果と非
晶質金属層形成コストとの両立を考えるならば、最も有
効な範囲は、0.05〜10μmである。
In addition, from the viewpoint of the effects of the present invention, the thickness of the amorphous surface layer is 0.
, 05 μm or more is sufficient. On the other hand, making the amorphous layer thicker than necessary only increases the cost of forming the amorphous metal layer, which is not practical. Therefore, when considering both the effect of bonding reliability and the cost of forming an amorphous metal layer, the most effective range is 0.05 to 10 μm.

なお、本発明による金属材料をリードフレームとして使
用する場合、非晶質表面層は、リードフレームの少なく
ともガラス封止される部位に形成されることが必要であ
るが、他の部位にまで形成されたとしても、差しつかえ
ない。
Note that when the metal material according to the present invention is used as a lead frame, the amorphous surface layer must be formed at least on the portion of the lead frame that is sealed with glass, but it may not be formed on other portions. Even if it were, it wouldn't be a problem.

また、本発明による金属材料をリードフレームに使用す
る場合、リードフレームの形に打ち抜いた後にガラス封
止部表面に非晶質金属層を設けてもよいが、リードフレ
ームの形に打ち抜く前のベースメタルの必要部分の表面
に非晶質金属層を設けておき、その後、リードフレーム
の形に打ち抜くようにする方が実際的であろう。
Furthermore, when the metal material according to the present invention is used for a lead frame, an amorphous metal layer may be provided on the surface of the glass sealing part after punching into the shape of the lead frame, but It may be more practical to provide an amorphous metal layer on the surface of the required portion of the metal and then punch it into the shape of a lead frame.

更に、本発明による金属材料をリードフレームに使用す
る場合、DIP型、Quad型の両パッケージに適用可
能なことは、言うまでもない。
Furthermore, when the metal material according to the present invention is used for a lead frame, it goes without saying that it is applicable to both DIP type and Quad type packages.

実施例 次に、本発明を実施例によって説明する。Example Next, the present invention will be explained by examples.

第1図は、本発明による金属材料をリードフレームとし
て利用した場合を図解する半導体装置の誇張拡大断面図
である。
FIG. 1 is an exaggerated enlarged sectional view of a semiconductor device illustrating a case where a metal material according to the present invention is used as a lead frame.

第1図に示す半導体装置は、DIP型ガラス・セラミッ
ク封止パッケージを採用したものであり、セラミックベ
ース30の凹部32にグイボンディングされた半導体チ
ップ34を有している。そのセラミックベース30の凹
部32を囲む周辺部には、低融点ガラス層36が形成さ
れている。
The semiconductor device shown in FIG. 1 employs a DIP type glass-ceramic sealed package, and has a semiconductor chip 34 that is firmly bonded to a recess 32 of a ceramic base 30. A low melting point glass layer 36 is formed in the peripheral area surrounding the recess 32 of the ceramic base 30 .

そのようなセラミックベース30の凹部32を囲む低融
点ガラス層36の上に、リードフレームのリード部38
が載せられている。そして、そのリードフレームのリー
ド部38の低融点ガラス層36の上に位置するガラス封
止部40の少なくとも一方の面、例えば、上面に非晶質
金属層42が形成されている。
Lead portions 38 of the lead frame are placed on a low melting point glass layer 36 surrounding such a recess 32 of the ceramic base 30.
is listed. An amorphous metal layer 42 is formed on at least one surface, for example, the top surface, of the glass sealing section 40 located on the low melting point glass layer 36 of the lead section 38 of the lead frame.

しかし、封止性を高めるために、リード部38のガラス
封止部40の両面に非晶質金属層を設けてもよい。
However, in order to improve sealing performance, amorphous metal layers may be provided on both sides of the glass sealing part 40 of the lead part 38.

また、リードフレームのリード部38と半導体チップ3
4とに、アルミニウムワイヤ44の各端がワイヤボンデ
ィングされている。
In addition, the lead portion 38 of the lead frame and the semiconductor chip 3
4 and each end of an aluminum wire 44 is wire bonded.

更に、セラミックベース30に重られるセラミックキャ
ップ46は、セラミックベース30の凹部32に対応し
てその凹部32より大きな凹部48が形成され、凹部3
2と48とによって画定される空間に半導体チップ34
とアルミニウムワイヤ44とが収容されるようになされ
ている。
Further, the ceramic cap 46 which is placed on the ceramic base 30 has a recess 48 which corresponds to the recess 32 of the ceramic base 30 and is larger than the recess 32 .
The semiconductor chip 34 is placed in the space defined by 2 and 48.
and an aluminum wire 44 are housed therein.

そして、セラミックキャップ46の凹部48を囲む周辺
部にも、低融点ガラス層50が形成されている。
A low melting point glass layer 50 is also formed in the peripheral area surrounding the recess 48 of the ceramic cap 46 .

かくして、リードフレームのリード部38を挟むように
してセラミックベース30にセラミックキャップ38が
重られて、例えば、約400℃〜500℃の温度で封止
処理される。
In this way, the ceramic cap 38 is placed on the ceramic base 30 so as to sandwich the lead portion 38 of the lead frame, and the ceramic cap 38 is sealed at a temperature of about 400° C. to 500° C., for example.

上述した構成において、リードフレームの素材として4
2%Ni−Fe合金を使用し、その基板上へ種々の材料
を被覆させ、ガラス封止性について検討したところ、次
の第1表の結果を得た。
In the above configuration, 4 is used as the lead frame material.
Using a 2% Ni--Fe alloy, various materials were coated on the substrate and the glass sealability was investigated, and the results shown in Table 1 below were obtained.

第1表 なお、上記第1表のデータ作成の際使用したガラス封止
性評価法は、次の如くである。
Table 1 The glass sealability evaluation method used to create the data in Table 1 above is as follows.

ガラス封止は、一般に用いられている低融点封止ガラス
を用いて封止温度450℃で行った後、−65℃〜+1
50℃のヒートサイクルを100回経た後、Heリーク
ディテクターでファインリークの有無を測定した。なお
、使用したDIP型ガラス・セラミック封止パッケージ
の最小リークパス(封止長さ)は0.7mmである。
Glass sealing was performed at a sealing temperature of 450°C using commonly used low melting point sealing glass, and then at -65°C to +1
After 100 heat cycles at 50° C., the presence or absence of fine leakage was measured using a He leak detector. Note that the minimum leak path (sealing length) of the DIP type glass-ceramic sealing package used was 0.7 mm.

以上の表から、表面に非晶質金属層を設けていない例1
に比べ、表面に非晶質金属層を設けた例2〜8及び10
が、リークテストの結果が良好であることがわかろう。
From the above table, example 1 where no amorphous metal layer is provided on the surface
Examples 2 to 8 and 10 in which an amorphous metal layer was provided on the surface compared to
However, you can see that the leak test results are good.

なお、表面に非晶質金属層を設けていないが金属アルミ
ニウム被膜を設けた例9が、例2と同様に、リークテス
トの結果が△であると表示されているが、それは○、△
、×の3段階評価によるためで、実際は、例2の方が例
9より優れていた。
Note that Example 9, in which an amorphous metal layer was not provided on the surface but a metallic aluminum coating was provided, is displayed as having a leak test result of △, similar to Example 2, but it is not ○ or △.
This was based on a three-level evaluation of , ×, and in reality, Example 2 was better than Example 9.

以上の結果から明らかなように、本発明によりリードフ
レームの表面に形成された非晶質金属層を介して行なう
ガラス封止は、従来のリードフレーム(表面が結晶金属
となっている)に比較して、封止の信頼性を大幅に向上
させ、且つ、半導体素子の大型化やパッケージの小型化
の動向に十分対応できることが実証された。
As is clear from the above results, the glass sealing performed through the amorphous metal layer formed on the surface of the lead frame according to the present invention is better than that of conventional lead frames (where the surface is made of crystalline metal). As a result, it has been demonstrated that the sealing reliability can be significantly improved, and that it can sufficiently respond to the trends of larger semiconductor devices and smaller packages.

以上、本発明による金属材料を、リードフレームに適用
した場合について説明したが、ガラスとの封止信頼性が
必要な金属材料ならば、リードフレームに限らず、半導
体装置用のどのような金属材料にも適用できることは明
らかであろう。
In the above, the case where the metal material according to the present invention is applied to a lead frame has been described. However, as long as the metal material requires sealing reliability with glass, it can be used not only for lead frames but also for semiconductor devices. It is clear that it can also be applied.

発明の詳細 な説明したように、本発明による金属材料はガラスとの
封止信頼性を著しく向上することができる。従って、リ
ードフレーム等に使用する場合、リードの数が増大して
も、パッケージの封止の信頼性を十分確保することがで
き、半導体素子の大型化やパッケージの小型化の動向に
十分対応できる。
As described in detail, the metal material according to the present invention can significantly improve sealing reliability with glass. Therefore, when used in lead frames, etc., even if the number of leads increases, the reliability of package sealing can be ensured sufficiently, and it can fully respond to the trend of larger semiconductor devices and smaller packages. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明による金属材料を用いたリードフレー
ムを使用した半導体装置パッケージの断面図、そして、
第2図は、ガラス−セラミック封止型パッケージの分解
部品配列斜視図である。 〔主な参照番号〕 14・・セラミックベース、16・・低融点ガラス層、
18・・リードフレームから裁断されたリード、20・
・セラミックキャップ、 22・・低融点ガラス層、30・・セラミックベース、
32・・セラミックベース30の凹部、34・・半導体
チップ、 36・・低融点ガラス層、38・・リードフ
レームのリード部、 40・・リード部38のガ°ラス封止部、42・・非晶
質金属層、 44・・アルミニウムワイヤ、 46・・セラミックキャップ、 48・・セラミックキャップ38の凹部、50・・低融
点ガラス層
FIG. 1 is a sectional view of a semiconductor device package using a lead frame made of a metal material according to the present invention, and
FIG. 2 is a perspective view of the exploded parts arrangement of the glass-ceramic sealed package. [Main reference numbers] 14...Ceramic base, 16...Low melting point glass layer,
18...Lead cut from lead frame, 20...
・Ceramic cap, 22..Low melting point glass layer, 30..Ceramic base,
32... Concavity of ceramic base 30, 34... Semiconductor chip, 36... Low melting point glass layer, 38... Lead part of lead frame, 40... Glass sealing part of lead part 38, 42... Non-containing part. Crystalline metal layer, 44... Aluminum wire, 46... Ceramic cap, 48... Concave portion of ceramic cap 38, 50... Low melting point glass layer

Claims (5)

【特許請求の範囲】[Claims] (1)ガラスとの封止部の表面に非晶質金属層を設けた
ことを特徴とする半導体装置用金属材料。
(1) A metal material for a semiconductor device, characterized in that an amorphous metal layer is provided on the surface of a portion sealed with glass.
(2)前記非晶質金属層は、金属材料の表面を非晶質化
することによって形成されていることを特徴とする特許
請求の範囲第1項記載の金属材料。
(2) The metal material according to claim 1, wherein the amorphous metal layer is formed by making the surface of the metal material amorphous.
(3)前記非晶質金属層は、金属材料の表面をイオンボ
ンバード、電子線ボンバード、或いはレーザービーム照
射することによって形成されていることを特徴とする特
許請求の範囲第2項記載の金属材料。
(3) The metal material according to claim 2, wherein the amorphous metal layer is formed by irradiating the surface of the metal material with ion bombardment, electron beam bombardment, or laser beam irradiation. .
(4)前記非晶質金属層は、金属材料の表面に非晶質化
金属層を被覆することによって形成されていることを特
徴とする特許請求の範囲第1項記載の金属材料。
(4) The metal material according to claim 1, wherein the amorphous metal layer is formed by coating the surface of the metal material with an amorphous metal layer.
(5)前記非晶質金属層は、金属材料の表面に、湿式メ
ッキ、PVD法、或いはCVD法によって、非晶質化金
属層を被覆することによって形成されていることを特徴
とする特許請求の範囲第4項記載の金属材料。
(5) A patent claim characterized in that the amorphous metal layer is formed by coating the surface of a metal material with an amorphous metal layer by wet plating, PVD, or CVD. The metal material according to item 4.
JP12827884A 1984-06-21 1984-06-21 Metal material for semiconductor device Pending JPS617645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12827884A JPS617645A (en) 1984-06-21 1984-06-21 Metal material for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12827884A JPS617645A (en) 1984-06-21 1984-06-21 Metal material for semiconductor device

Publications (1)

Publication Number Publication Date
JPS617645A true JPS617645A (en) 1986-01-14

Family

ID=14980869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12827884A Pending JPS617645A (en) 1984-06-21 1984-06-21 Metal material for semiconductor device

Country Status (1)

Country Link
JP (1) JPS617645A (en)

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