JPS61126687A - Dynamic type ram - Google Patents

Abstract

PURPOSE:To make power consumption lower at the time of a refreshing action by referring to an internal action signal formed based upon the external control signal, and prohibiting an action of a column-type circuit at the time of the refreshing action. CONSTITUTION:When a chip selecting signal inverting CS of the external signal is H and a refreshing control signal inverting RESH is L, an automatic refreshing condition is obtained, and a low address, which is outputted by an automatic refreshing circuit RESH and successively stepped, is selected by a multiplexer MPX. On the other hand, in accordance with these signal inverting CS and inverting RESH, a timing generating circuit TG generates a data selecting timing signal phix, and stops the occurrence of phiy. Through the low decoder R-DCR1 in which the signal phix is supplied, a word line is successively selected and refreshed and a column type circuit circuit without a signal phiy and regardless of the refreshing action, for example, the action such as a main amplifier MA is prohibited, and the power consumption can be lower at the time of a refreshing action.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a dynamic RAM (random access memory). , by detecting changes in the address signal and forming a series of timing signals necessary for the operation of internal circuits.
Now it can be treated the same as AM! I image dynamic type R
It relates to technology that is effective for use in AM.

[Background technology]

The applicant of the present application has developed a pseudo-static RAM that first detects changes in address signals and forms various timing signals necessary for the operation of internal circuits. That is, it uses a dynamic memory cell composed of a capacitor that stores information in the form of charge and a MOSFET for address selection, and its peripheral circuitry is composed of a static 0M03 circuit to detect changes in the address signal. Based on this, various timing signals necessary for the operation of internal circuits are formed, so that it can be treated from the outside in the same way as a static type RAM.

However, in a dynamic memory cell formed on a semiconductor substrate, the charge accumulated in the capacitor decreases over time due to leakage current or the like. Therefore, in order to always store accurate information in a memory cell, the information stored in a memory cell must be read out before it is lost, amplified, and then used again in the same memory cell. It is necessary to perform a write operation, a so-called refresh operation.For example, an automatic refresher method for memory cells in a 64-bit dynamic RAM is described in "Electronic Technology 1, Vol. 123, N.
The automatic refresh circuit shown in pp. 30-33 of J.O. 3 is known. In other words, dynamic RAM
The auto-refresher is equipped with an external terminal for refresher control, and by applying a refresh control signal RESH of a predetermined level to this external terminal, multiple memory cells in the dynamic RAM are automatically refreshed. and a self-refresh function that operates a built-in timer circuit by keeping the refresh signal RESH at a predetermined level and performs the refresh operation at regular intervals.

When the above-mentioned imageless automatic refresh circuit is used as an internally synchronized dynamic RAM (similar to I!!-like dynamic RAM) as described above, a series of timing signals are generated even during a refresh operation, and a refresh operation is performed. Even circuits that are not directly related to the current state are operated, resulting in unnecessary current consumption.

[Purpose of the invention]

An object of the present invention is to provide a dynamic RAM that reduces power consumption during refresh operations.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, during automatic refresh operation using the built-in automatic refresher circuit, generation of column-related timing signals is prohibited, thereby inhibiting the operation of circuits that are not directly related to the refresh operation, thereby reducing power consumption. be.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a dynamic RAM according to the present invention. Each circuit element in the same figure is
The well-known OMO3 (complementary MO5) integrated circuit fabrication technique is formed on a single semiconductor substrate, such as single crystal silicon.

In the following explanation, unless otherwise specified, MOSFET
ET (insulated gate field effect transistor) is an N-channel MOS FET. In addition, in the same figure,
MOS F E with a straight line added between source and drain
T is of P channel type.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MO
SFET consists of a source region, a drain region formed on the surface of such a semiconductor substrate, and polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. It consists of a gate electrode. P Channel M OS F B 'I
' is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the base gate of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOS FET, ie, the N-type well region, is coupled to the power supply terminal Vcc of FIG.

In FIG. 1, the substrate back bias voltage generation circuit vb
b-c are power supply terminals Vc forming external terminals of the integrated circuit;
In response to a positive power supply voltage, such as +5V, applied between 'c and a reference potential terminal or ground terminal, a negative voltage vbb is generated to be supplied to the semiconductor substrate. This applies a back bias voltage to the substrate gate of the N-channel MOS FET, and its source.

Since the parasitic capacitance value between the drain and the substrate is reduced,
The circuit can operate at high speed.

In the memory array M-ARY, a pair of rows is shown as a representative, a pair of complementary data lines arranged in parallel, and a plurality of memory arrays D each including a MO3FET Qm for address selection and a capacitor Cs for information storage are shown. The input/output nodes of the memory cells are distributed and coupled with a predetermined regularity as shown in the figure.

The precharge circuit PCI is MO3 shown as a representative.
Complementary data line like FETQ5.

It is composed of a switch MOS FET provided between D and D.

The sense amplifier SA is a P-channel MO3FETQ? shown as a representative. , Q9 and N-channel MO3FET
Q6. It is composed of a CMOS latch circuit consisting of Q8,
The pair of input/output nodes are coupled to the complementary data line, D. The latch circuit may include, but is not particularly limited to, a P-channel MO3FETQ in parallel form.
I 2. Power supply voltage Vcc is supplied through Ql 3,
N-channel MO3FET QI O, Ql in parallel form
The ground voltage Vss of the circuit is supplied through 1. These power switches Mo 3 F ETQ 10. Q
11 and MO5FETQ12. Q13 is commonly used for latch circuits provided in other similar rows within the same memory mat. In other words, the same memory,
O5FE between P channels in latch circuit in mat
The sources of the T and N channel MO5FETs are commonly connected.

A complementary timing pulse φpal r φpal that activates the sense amplifier SA is applied to the gates of the MO3FETQI O, Ql 2 in the operation cycle,
MO3FETQI 1. At the gate of Ql 3, the timing pulse φpal*lags behind φpal,
Complementary timing pulses φpa2 and φpa2 are applied. By doing this, the sense amplifier S
The operation of A can be divided into two stages. timing pulse φp
a1. When φpal is generated, that is, in the first stage, MO5F with relatively small conductance
Due to the current limiting effect of ETQI O and Q12, the minute read voltage applied between the pair of data lines from the memory cell is amplified without undergoing any undesired level fluctuations. After the difference in complementary data line potential is increased by the amplification operation in the sense amplifier SA, when the timing pulse φpa2.7''pa2 is generated, that is, the second
When entering the stage, MO with relatively large conductance
3FETQI 1. Ql 3 is turned on.

The amplification operation of the sense amplifier SA is performed by MO3FETQ11,
This is made faster by turning on Q13. By performing the amplification operation of the sense amplifier SA in two stages in this way, it is possible to read data at high speed while preventing undesired level changes in the complementary data line.

Although not particularly limited, the row decoder R-DCR is configured by a combination of two divided row decoders R-DCR1 and R-DCR2.

In the figure, one circuit of the second row decoder R-DCR2 (four word lines) is shown as a representative, for example, an N-channel MO3 that receives address signals 72 to T6.
FETQ32 to Q36 and P-channel MOSFETQ
NAN by 0M03 circuit composed of 37 to Q41
The four word line selection signals mentioned above are formed by a D (NAND) circuit.

The output of this NAND circuit is the CMOS
V i Te inverted and cut MO3FETQ28~Q3
1 through the transmission gate MO3F as a switch circuit
It is transmitted to the gate of ETQ24~0.27.

The first row decoder R-DCR1 uses a 2-bit complementary address (No. 8 aO,
4 types of word line selection timing signal φx00 are generated from the word line selection timing signal φX through a switch circuit consisting of a transmission gate (transmission gate) MOSFET and a cut MO3FET selected by the decode signal formed by aO, al, and al. to φxll are formed. These word line selection timing signals φx00 to φxll
is transmitted to each word line via the transmission gate and the MO3FETs Q24 to Q27. Row decoder R-DC
By dividing the row decoder into two like RI and R-DCR2, the pinch (interval) of the row decoder R-DCR2 can be matched with the pitch of the word lines. As a result, no wasted space is created on the semiconductor substrate. MO5FETQ20~Q2 is connected between each word line and ground potential.
3 is provided, and by applying the output of the NAND circuit to its gate, the word line is fixed at the ground potential when not selected. Although not particularly limited, the word line has a far end (the end opposite to the decoder side).
MO5FETs QI to Q4 are provided for reset, and these MO3FEs receive a reset pulse φpH.
By turning on TQI-Q4, the selected word line is reset to the ground level from both ends thereof. On the right, the remaining 2 bits of address signal a7. a8 is used as a mat switching signal for selecting a plurality of similar memory arrays.

Row address buffer X-ADB is connected to external terminal AO-A.
In response to the address signal supplied from 8, the internal address signal aO is in phase with the address signal supplied from the external terminal.
An address signal TO~a8 (hereinafter, these are collectively expressed as 10~Saturday/Sunday) having a phase opposite to ~a8 is formed and supplied to the row decoder R-OCR via a multiplexer MPX, which will be described later.

Column switch C-5W is M shown as a representative.
O3FETQ42. Like Q43, the complementary data line D is selectively coupled to the common complementary data line CD, CD. A selection signal from a column decoder C-DCR is supplied to the gates of these MO5FETs Q42 and Q43.

The column decoder C-0CR is controlled by the column selection timing signal φy and receives address signals a9 to a in opposite phase to the internal address signals a9 to a14 supplied from the column address buffer Y-ADB.
Column switch C-5 by decoding 14
Forms a selection signal to be supplied to W.

Column address buffer Y-ADB is connected to external terminals A9~
In response to the address signal supplied from A14, internal address signals a9 to a14 having the same phase as the address signal supplied from the external terminal and address signals a9 to a14 having the opposite phase (hereinafter, these are collectively referred to as i9 to step 14) ) is formed and supplied to the column decoder C-0CR.

Between the common complementary data lines CD and CD, there is a precharge MO3FETQ that constitutes a precharge circuit similar to the above.
44 are provided. These common complementary data lines CD, C
D is coupled to a pair of input/output nodes of a main amplifier MA having a circuit configuration similar to that of the sense amplifier SA.

For read operation, data output buffer D.

B is brought into operation by the timing signal φr, and amplifies the output signal of the main amplifier MA and sends it out from the external terminal I10. In addition, in the case of a write operation, the data output buffer DOB is activated by the timing signal φrss.
The output of is placed in a high impedance state. In the case of a write operation, the data input buffer DIB is activated by the timing signal φrw and transmits a complementary write signal according to the write signal supplied from the external terminal I10 to the common complementary data lines CD, CD. As a result, writing to the selected memory cell is performed. Note that in the case of a read operation, the output of the data input buffer sofa DIH is brought into a high impedance state by the timing signal φrl-.

The various timing signals described above are formed by the following circuit blocks.

Although not particularly limited, what is shown by the circuit symbol ATD is address signals aO to a8 (or 0 to 8) and an address signal +l! This is an address signal change detection circuit that receives signals 9 to a14 (or 79 to 14) and detects a change in the rising or falling edge thereof. The address signal change detection circuit ATD includes, but is not particularly limited to, an exclusive OR circuit that receives each of the address signals 80 to a14 and their delayed signals, and an OR circuit that receives the output signals of these exclusive OR circuits. It is composed of That is,
An exclusive circuit is provided for each address signal to receive an address signal and a delayed signal of that address signal.

In this case, a total of 15 exclusive OR circuits are provided, and the output signals of these 15 exclusive OR circuits are input to the OR circuit. When any one of the address signals aO to a14 changes, this address signal change detection circuit ATD forms an address signal change detection pulse φ synchronized with the change timing.

The circuit symbol TG is a timing generation circuit, which forms the main timing signals etc. shown as the representative above. That is, this timing generation circuit TG
receives the address signal change detection pulse φ, the enable signal WE (enable signal WE), the chip selection signal C8, and the refresh signal RESH supplied from an external terminal, and forms the above-mentioned series of timing pulses.

The circuit symbol REF is an automatic refresher circuit and a refresher address counter. Contains timers etc. This automatic refresh circuit REF is activated by setting refresh i-i+RESH from an external terminal to a low level. That is, when the chip selection signal C8 is at a high level, the refresh signal R
When ESH is set to low level, the automatic refresh circuit RE
F is connected to multiplexer M by control signal φrot.
P
Refresh operation C by selecting one word line
In addition, if the refresh signal RESH is kept at a low level, a timer is activated and the refresh address counter is incremented at regular intervals, during which time a continuous refresh operation (self-refresh) is performed. In this embodiment, although not particularly limited, in order to check the operation of the address counter, etc., a function is added to write into the memory cell using addressing by the refresh operation. That is, as described later, the write enable signal WE is set to the power supply voltage V in synchronization with the refresh operation.
When the write control signal is at a level higher than cc, writing is performed to the memory cell at the address specified by the address counter.

FIG. 2 shows a circuit diagram of an embodiment of the circuit for forming the data line selection timing signal φy in the timing generation circuit TG.

When the timing ordering circuit TG receives the output pulse φ of the address signal change detection circuit ATD, it outputs a word line precharge pulse φ, a word line selection timing signal φX, a word line selection timing signal φX,
Sense amplifier operation timing signal φpa (φpal
+φpa2), etc. In this case, a NAND gate circuit G1 is used as a circuit that delays the operation timing signal φpa of the sense amplifier by an inverter circuit IV2 to form a data line selection timing signal φy, and a NAND gate circuit G2 forms a control signal thereof. is added. That is, the control signal φref and the refresh write control signal φwref are supplied to the input of the Nant gate circuit G2. The output of this Nant gate circuit G2 is used as a control signal for the Nant gate circuit G1 which forms the data line selection timing signal φy.

The operation of this embodiment circuit will now be described with reference to the timing diagram shown in FIG.

When the chip selection signal C8 is set to high level, this RA
M is made chip non-selected. At this time, when the refresh control signal RESH is set to a low level for a certain period of time, the auto-refresh operation described above is executed. In synchronization with the low level of the refresh control signal RESH, when a write enable signal WE with a level higher than the power supply voltage Vcc is supplied as shown by the solid line in the figure, the refresh write control signal φ-ref is synchronized with this. is set to low level. In such a refresh write operation, the output of the Nant gate circuit G2 is set to a high level (logic "1"), so the data line selection timing signal φy is formed as in a normal write or read operation. . Although not shown, column system timing signals such as main amplifier MA operation timing signal φma, data input buffer sofa DIB, and data output buffer DOB are selectively operated by delaying the data line selection timing signal φy. Writing and reading can be performed to the memory cell at the address specified by the timing refresh address counter. Such a refresh operation function is mainly used for the following purposes. In the automatic refresh circuit REF, it is extremely important that the built-in refresh address counter operates normally. In order to confirm the operation of the above refresh address counter, the stored information in the memory cell is set to logic "O" in advance, and by writing using the above automatic refresh, the memory information is set to logic "O".
By rewriting to 1'' and confirming this rewriting by reading it, the operation of the refresh address counter can be indirectly confirmed.

In the refresh operation, the write enable signal WE goes to a high level (Vcc) as shown by the dotted line in the figure.
). As a result, the refresh write control signal φ-ref is set to high level. Therefore, in the same auto-refresh operation as described above, each time the control signal φref goes high, the Nant gate circuit G
1 is closed, the data line selection timing signal φy
occurrence is stopped. As a result, the operation of column-related circuits, for example, the operation of the main amplifier MA, etc., is prohibited. This makes it possible to inhibit the column selection operation and the amplification operation of the main amplifier during the normal refresh operation.

Note that in the self-refresh operation performed by keeping the refresh control signal RESH at a low level, the control signal φref is kept at a high level during that time, so that the operation of the column-related circuit can be similarly inhibited.

In addition, if the above refresh writing function is not provided,
An inverted signal of the control signal φref may be formed to close the t-contact Nant gate circuit G1 at a low level during the refresh operation.

〔effect〕

<1) By referring to an internal operation control signal formed based on an external control signal, generation of a column-related timing signal during a refresh operation is prohibited, thereby preventing column-related circuits that are not directly related to the refresh operation. By prohibiting the operation, power consumption can be reduced.

(2) Since self-refresh operation is mainly used during battery bank-up operation, battery life can be extended by reducing E2 power consumption.)
Effects can be obtained.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the Examples described in F, and it is understood that various changes can be made without departing from the gist thereof. Needless to say. For example, the read reference voltage of the memory cell may be formed using a dummy cell.

In addition, a circuit that prohibits the operation of internal circuits that are not directly related to the refresh operation is a circuit that selectively prohibits the generation of a gate circuit similar to the above for each timing generation circuit supplied to each circuit. It may be.

[Application field]

The present invention incorporates an automatic refresh circuit and can be widely used in internally synchronized dynamic RAMs.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a partial embodiment of the timing generation circuit, and FIG. 3 is a timing diagram for explaining its operation. be. M-ARY...Memory array, PCI...Precharge circuit, SA...Sense amplifier, C-SW...Column switch, R-OCR...Row address decoder, C-DC
R: Column address decoder, MA: Main amplifier, ATD: Address signal change detection circuit, TG: Timing generation circuit, REF: Automatic refresh circuit, D
OB...data output buffer, DIB...data manual buffer, MPX...multiplexer, G1. G2...Nant gate circuit

Claims (1)

[Claims] 1. An automatic refresh circuit that performs an automatic refresh operation based on a control signal supplied from an external terminal, and a series of processes necessary for the operation of the internal circuit based on the change detection output of the address signal and the external control signal. It is characterized by comprising a timing generation circuit that generates a timing signal and includes a circuit that stops the operation of a main amplifier that amplifies at least a signal on the common complementary data line during a refresh operation state performed by the automatic refresh circuit. Dynamic RAM. 2. A patent characterized in that the dynamic RAM has a function of performing a write operation to a memory cell designated by an address signal generated by an automatic refresh circuit using a combination of a refresh control signal and a write enable signal. Dynamic RAM according to claim 1.