JPS61125259A - Receiving device - Google Patents

Abstract

PURPOSE:To obtain a receiving device with simple circuit which is able to receive the transmitted data accurately and is stable against frequency variation and noise by making the system to receive a pulse signal that expresses the binary data by the variation of pulse spacing. CONSTITUTION:The demodulation signal (a) of a demodulating circuit 5 is constituted by the synchronizing signal of comparatively long pulse spacing and the 8-bit data that follows the synchronizing signal and expresses the binary data with its varied pulse spacing. And, the synchronizing signal of which pulse spacing is longer than that of the data pulse by n-times of it, is detected. Based on the pulse spacing of this synchronizing signal, a space which is longer than 1/n(m>n) of this pulse spacing is made '1' (or '0'), one that is shorter than the 1/n length is made '0' (or '1'), by which signal the system performs its decision, and obtains a binary data of specified number of bits.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a receiving device.

[Prior art]

For example, in conventional radio-controlled toys, one of the formats of control data transmitted to a receiving device is a pulse position modulation method.

The control data using this pulse position modulation method is
A synchronization signal expressed by two pulse signals with a predetermined pulse interval, and following this synchronization signal, when controlling three channels, for example, the a pulse of the first channel is expressed with a predetermined pulse interval between each. , then a second channel B pulse, and then a third channel C pulse.

Then, depending on the operating position of the operating lever of the transmitter, the above a.
The position of each pulse of b and Q changes linearly, whereas the receiving device changes the rotation speed, direction of rotation, etc. of the motor, which is set in a one-to-one relationship with the position of each pulse of albXC. receive control data to control the
The toy is driven.

[Problems with conventional technology]

However, with the conventional method described above, data is expressed according to the position of the pulse, so as the number of channels increases, the circuit becomes extremely complex, and malfunctions occur due to frequency fluctuations and noise on the transmitting side. There are some problems that can easily occur.

[Purpose of the invention]

This invention is a simple circuit, resistant to frequency fluctuations and noise,
An object of the present invention is to provide a receiving device that can accurately receive transmitted data.

[Key points of the invention]

It receives a pulse signal that expresses binary data 1'', ...o, etc. by the length of the pulse interval, and detects a synchronization signal with a pulse interval m (m is a positive number) times longer than the pulse interval of the data pulse. , based on the pulse interval of this synchronization signal, those longer than 1/n (n is a positive number, m>n) of this pulse interval are designated as "1" (or "o"), and those shorter than 1/n are designated as "1" (or "o"). It is determined as '0'' (or 1'') and binary data of a predetermined number of bits is obtained.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to a radio-controlled toy will be described with reference to the drawings.

FIG. 1 shows the circuit configuration of the receiving device. In the figure, 1 is resistance,
It is a one-shot circuit with a capacitor connected, and when the receiver's power switch is turned on, a single signal R is generated.
2, and is reset by a carry signal R3, which will be described later. Then, the single-shot signal R2 resets the SRR flip-flop 2. This flip-flop 2 is set by a signal READY, which will be described later, and its set output signal becomes a signal R1.

On the other hand, 3 is an antenna, which is transmitted from the transmitter at a frequency of, for example, 27.
The control data carried by the 145 (MHz) signal is received and sent to the demodulation circuit 5 via the high frequency amplifier 4.
It is demodulated and becomes signal a. Further, this demodulation circuit 5 receives a 26.69 (MHz) signal from the local oscillator 6 and performs a demodulation operation using a superheterodyne method.

Here, FIG. 2 shows an example of the signal waveform of the signal a. This signal a first consists of a synchronization signal consisting of a relatively long pulse interval of a synchronization pulse signal, and following this synchronization signal, and depending on the length of the pulse interval, 11 bits of binary data.
``'', a data signal (8-bit data) consisting of eight pulse intervals expressing "0".The period of the synchronization signal is, for example, 30 (msec).
c), data "1" is a pulse interval of 10 (msec) that is larger than 1/4 of the period of this synchronization signal, and data "0" is a pulse interval of 5 (msθC) that is smaller than 1/4. The data pulse signal is generated.The pulse width of each pulse signal is Q, 5 (meeo),
The data period varies depending on the content of the hunt roll data, but is approximately 100 [m118Q).

Returning to FIG. 1, 7 is a timing generation circuit, which converts the 30 (KHz) signal from the local oscillator 6 into the signal a.
When the first pulse signal of
z) clock CL3.

Further, the signal a is applied to the input terminal S of 8 sets of SR type rough flip-flops, and is also applied as an input signal to a shift register 9 having a capacitance of 5 bits.

This shift register 9 is an ant gate whose gate is controlled by the set output signal of the flip-flop 8.
10, and each bit output is driven by the AND gate 1.
1, and its output becomes the clock OLI. This 5-bit shift register 9 has a frequency of 15 (KHz)
This is provided to distinguish whether it is a noise or a normal pulse signal by sampling the pulse width ("1" section) of the pulse signal of the signal a five times. If the pulse signal is normal, one clock CL1 is generated.

The clock OLI, along with a carry signal R3 to be described later, resets the block 70 and block 8 via the OR gate 12, and is applied to the one-shot circuit 13 to generate a one-shot signal. This one-shot signal is given to an 8-bit counter 14 and an 8-bit latch 15, respectively.
When the one-shot signal rises, the count value of the counter 14 is latched in the latch 15, and then when the one-shot signal falls, the counter 14 is reset.

The counter 14 is provided to count up the pulse interval of the signal a by counting up the counter 14 by the four-wheel drive OL3.
are both applied as clear signals via the OR gate 16.

The data latched in the latch 15 is transferred to A of the comparator circuit 17.
The input terminal and the register 18 are respectively provided. The data taken into the register 18 is further applied to the B input terminal of the comparator circuit 17 via the gate 19, and is also applied to the register 2o where it is reduced to 1/4 the size of the data and then sent to the register 20. It is further applied to the B input terminal of the comparator circuit 17 via the gate 21.

Here, the register 18 holds data representing the pulse interval of the synchronizing signal of the signal a, and the register 20 holds data representing 1/4 of the pulse interval of the synchronizing signal, which is a reference for distinguishing between data 1" and "Q". The specific circuit is shown in FIG. 3.

That is, as shown in FIG. 3, the upper six bits of the output data of the register 18 are given to the lower six bits of the register 20, and the upper two bits of the register 20 are always given 0'' data (ground level). There is.

The comparison circuit 17 compares each data of the A and B input terminals and
)B, a signal g of 1n is generated, and is supplied to L8B of the 8-bit shift register 23 via the AND gate 22 as the data content from the signal a. Since the shift register 23 is shifted to the right by the clock OLI, the 8-bit data according to the signal a that is sequentially input to L8B is shifted to the upper side, and the data is supplied to the latch 24. Then, this latch 24 latches the 8-bit data in response to a signal READY that is output when 8-bit data is input to the latch 24, and sends it to a motor drive circuit (1 not shown) etc. for rotation control etc. used.

Further, in the figure, 25 is a one-shot circuit, and an AND output of an AND gate 26 which inputs the signal R1 and a signal S to be described later.
and signal g is given via OR gate 27,
Generates a single signal. Then, at the rising edge of the one-shot signal, the register 18 latches the output data of the latch 15. Note that this register 18 is cleared by inputting the signal R2.

Further, the one-shot signal from the one-shot circuit 25 is applied to the one-shot circuit 29 via the inverter 28, and one-shot signal is further outputted from the one-shot circuit 29, causing the register 20 to latch the data.

Further, numeral 30 in the figure is a 9-ary counter, which is counted up by the clock C0LI and counts each pulse signal of the signal a. Then, when the count value is "0", the signal C is output as 1", and when it is between "1" and "8", the signal C is output as 1", and furthermore, "8" → "O" is reset. The reset signal a (READY) is output as 1''.

The signal R1 and the signal R1 passed through the inverter 32 are both applied to the OR gate 31 and supplied to the gate 19 as the control signal θ. Further, the signal C and the signal R1 are applied to an AND gate 33, and the output thereof is applied to the gate 21 as a control signal. Furthermore, signal C is signal R1
It is also applied to the AND gate 22.

Further, the 9-ary counter 30 receives the output of an AND gate 34 which inputs both the signal g and the signal R1 via an inverter 35 as a reset signal.

[Operation of the embodiment]

Next, the operation of the above embodiment will be explained. When the operating lever on the transmitter side is operated, a high frequency signal for providing a synchronizing signal and 8-bit data, as shown in FIG. 2, for example, is transmitted and received by the antenna 3. The synchronization signal and 8-bit data of the signal a are 100 (m
Occurs continuously at intervals of about 100.

Furthermore, when the receiving device is powered on, the one-shot circuit 1 first generates a single signal R2, which clears the counter 14 and the register 18. At the same time, the 7-rip 70-rub 2 is reset and the signal R2 is generated. R1 becomes 0''. Other circuits in FIG. 1 are also initialized.

Next, when the first synchronization pulse signal "1", which constitutes the first synchronization signal of the signal a in FIG. 2, is output from the demodulation circuit 5,
Lip flop 8 is set, and shift register 9
is supplied with data "1" to its LSB, and furthermore, the timing generation circuit 7 generates clocks CL2 and C by inputting the signal a.
Start outputting L3 respectively. Therefore, the clock OL2 shifts the shift register 9 through the analog gate 10 which is opened by the set output of the flip-flop 8. Since the synchronizing pulse signal is a signal with a pulse width that is more sufficient than that of noise, when the clock CL2 is output five times, "1" is written to all bits of the shift register 9, and the clock OLI is set to 1 from the AND gate 11. The one-shot signal is generated from the one-shot circuit 13, and the flip-flop o 77' 8 tt is reset.

Therefore, the latch 15 is set to the count value "0" of the counter 14.
is latched and applied to the A input terminal of comparison circuit 17 and register 18, and then counter 14 is cleared. In this case, the gate 19 is opened and the gate 21 is closed because the signal R1 is "0" and the signal R1 is "0", and the gate 21 is closed. , starts counting the clock OL3.

Next, when the second synchronizing pulse signal forming the above-mentioned first synchronizing signal in FIG. 2 is output as signal a, the flip-flop 8 is set again. Therefore, in the same manner as described above, when clock OL2 outputs five clocks, one clock O
LI is generated, the flip 70 knob 8 is reset, and the one shot signal is output from the one shot circuit 13, and the latch 15 starts the counter 1 in synchronization with the rise of this one shot signal.
The current count value of 4 (that is, data representing the pulse interval of the first synchronizing signal) is latched, and then the counter 14 is cleared in synchronization with the fall of the one-shot signal. The count value latched by the latch 15 is then applied to the input terminal of the comparison circuit 17, and the counter 14 starts the next counting operation.

Since data "0" is input from the gate 19 to the B input terminal of the comparator circuit 17 at this time, the comparison result is A>
B, and the signal g is output as '1''. Therefore, one shot signal is generated from the one-shot circuit 25, and the count value representing the pulse interval of the above-mentioned first synchronization signal is taken into the register 18. It is applied to the B input terminal of the comparison circuit 17 through the gate 19 in the middle, and the data of the count value 174 is taken into the register 20.

-4, the 9-decimal counter 30 has the above second clock CL.
1 is applied, but the output of the signal g of '1' and the current signal R
Since 1 is MO'', the 9-ary counter 30 is reset again and its count value remains rOJ.

Next, when the first data pulse signal representing data "1" of the 8-bit data following the first synchronization signal shown in FIG. 2 is generated as signal a, the clock OLI is generated in the same manner as described above, and therefore One shot circuit 13
A single signal is generated. Therefore, a count value representing the pulse interval of data "1" is latched in the latch 15 and applied to the A input terminal of the comparison circuit 17 and the register 18. The comparator circuit 17 compares the count value for the pulse interval of the data "1" at the A input terminal and the B
The signal g is '0' in this case. No one-shot signal is generated from the shot circuit 25, so the register 18 does not take in the count value of data "1", and its contents remain unchanged as the current value of the synchronizing signal.

Also, since the signal g is 0'' this time, the reset signal is O
”, the 9-digit counter 30 is not reset, and the clock OLI is counted, and the count value changes from “0” to “1”.
” will be +1. Therefore, from then on, the signal S becomes "0" and only the signal C becomes "1", but the state in which the gate 19 is open and the gate 21 is closed does not change because the signal R1 (Won).

Next, data “0”, lI+ of the 8-bit data in FIG.
, "O", 0", 1", "1", and "1" respectively. It is exactly the same as when outputting, so the signal g is ``0'' each time.
At the same time, the 9-decimal counter 30 is incremented by 1, changing from "]" to "8". Then, since the 9-ary counter 30 is reset to "0" when it reaches 8, the signal ek (READY) is output as R1.

As a result, flip-flop 2 is set and the signal 'R
1 becomes "1" thereafter, and accordingly, no reset signal is outputted thereafter regardless of the signal g.

With the above, the reception operation for the first synchronization signal and 8-bit data is completed, but during this time, the AND gate 22 is closed because the signal R1 is R0'', and therefore only invalid data is input to the shift register 23. Of course, this invalid data is also latched in the latch 24, but since it is the first time, the motor only performs the initial setting operation.

Then, when the second synchronization signal is output, the comparator circuit 1
In step 7, a comparison is made with the count value for the synchronization signal first taken into the register 18, but since both count values are generally approximately equal, the register 18 continues to hold the first count value. Further, during this comparison operation of the synchronizing signals, since the signal is "1", no data is input to the shift register 23.

Next, when a data pulse signal indicating the first 1'' of 8-bit data is output in response to the second synchronization signal,
At that time, the 9-ary counter 30 counts the clock CL1 and the count value becomes "1", and the signal C therefore becomes R1", and at the same time, although the signal R1 is 1", the AND gate 33 outputs '1'. When the signal is output, the gate 21 is opened, and R0'' is output from the OR gate, and the gate 19 is closed. Therefore, at this time, the comparison circuit 17
The B input terminal of
data '°1', '0', which is obtained by reducing the count value of
A count value serving as a reference for determining " is inputted. A count value corresponding to a pulse interval corresponding to binary data 1" is inputted to the A input terminal of the comparator circuit 17.

Therefore, the comparison result at this time is A)B, and the signal g is output as "1" to the AND gate 22 which is being opened.
The data is taken in as data "1" to the LSB of the shift register 23 via.

Next, when a data pulse signal of ``0'', which is the second data of the 8-bit data in response to the second synchronization signal, is generated, the 9-ary counter 30 is incremented by 1 and becomes ``2'', and the signal C is It continues to be output as "R1". Therefore, in the comparator circuit 17, the data to the A input terminal "
Count value for OI+ and above 1/ to B input terminal
A comparison is made with the reduced data of 4, and in this case it becomes A(B, and the signal g is output as 60". Therefore, this data "0" is taken into the LSB of the shift register 23. , the previous data "1" is shifted to the second bit.

Below, the data from the 3rd bit to the 8th bit "I I+, t
Exactly the same operation is performed for "oll, No", "1", "1", and R1", and during this time, the 9-ary counter 30 is incremented by 1, and each of the above data is sequentially fetched into the shift register 23. be included.

When all the data are taken in, the signal READY becomes R1'', so the 8-bit data in the shift register 23 is latched by the latch 24, and sent to the motor drive circuit to execute the corresponding control.

The reception operation for the third synchronization signal and its 8-bit data after power-on is exactly the same as the second synchronization signal described above. Even if the pulse interval of the synchronization signal fluctuates on the way, based on the magnitude relationship between the current fluctuating synchronization signal of the comparison circuit 17 and each pulse interval of the previous synchronization signal,
The signal g is generated as "1" or 0, and if it is 1 m, the pulse interval has become a little larger, so the new one is taken into the register 18, and the register 20 outputs 174. The data is reduced to ``1'', O
Since it is used to determine n, even if there is a frequency fluctuation of signal a, it can be dealt with immediately.

Furthermore, if the power is turned off and signal a disappears,
When counter 14 generates carry signal R3, all circuits are reset.

In the above-described embodiments, the present invention is applied to a receiving device for a radio-controlled toy, but the present invention is of course not limited to this, and may be applied to a receiving device for other equipment.

〔Effect of the invention〕

As explained above, the present invention receives a pulse signal expressing binary data "1" and "0" by the length of the pulse interval, and the pulse interval of the data pulse is m(
m is a positive number) A synchronization signal with a pulse interval that is twice as long is detected, and based on the pulse interval of this synchronization signal, one of this pulse interval is
/ n (n is a positive number, m>n) longer than 1" (or "On"), shorter than 1 / n as 0" (or 11"), and binary data of a predetermined number of bits is Since the receiving device is designed to obtain the same data, the circuit does not become complicated even if the number of data bits increases, and it also has the advantage of being less susceptible to frequency fluctuations and noise of the modulated wave on the transmitting side.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a receiving device according to an embodiment of the present invention, FIG. 2 is a waveform diagram of demodulated control data,
FIG. 3 is a connection diagram of the shift registers 18 and 20. 1.13.25.29...One-shot circuit,
2.8... Flip-flop, 5... Demodulation circuit, 6... Local oscillator, 7... Timing generation circuit, 9.23... Shift register, 14.30... Counter, 15.24...
...Latch, 18.20 ...Register, 17
...Comparison circuit, 19.21...Gate.

Claims (1)

[Claims] demodulating means for receiving a synchronizing signal consisting of a synchronizing pulse signal train having a predetermined pulse interval and a data signal consisting of a data pulse signal train representing data following the synchronizing signal and demodulating the signal; and an output of the demodulating means. a detection means for detecting the pulse interval of the synchronization signal and each pulse interval of data following the synchronization signal; and a detection means for detecting the pulse interval of the synchronization signal detected by the detection means; Among each pulse interval of the data, those larger than 1/n (n is a positive number) of the pulse interval of the synchronizing signal are set as "1" (or "0") of binary data.
), and determining means that determines a value smaller than 1/n as "0" (or "1").