JPS61125068A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve mounting density, by using unused or used semiconductor elements, which are provided in a semiconductor device and unused region other than wirings, forming a smoothing capacitor for stabilizing a power source voltage, thereby reducing an area required for providing the smoothing capacitor. CONSTITUTION:A smoothing capacitor is formed by using extra semiconductor elements in a basic cell 8A. At this time, a junction capacity between an embedded layer 34 and a semiconductor substrate 5, a junction capacity between an epitaxial layer 35 and bases 11C and 14C and a junction capacity between emitters 11B and 14B and the bases 11C and 14C are used. The base regions 11C and 14C are electrically connected to a conducting layer 22 at a Vee potential through a connecting hole 19 by a conducting layer 18. Collector regions 11A and 14A and the emitter regions 11B and 14B are electrically connected to a conducting layer 23 at a Vcc potential through a connecting hole 21 by a conducting layer 20. The conducting layers 22 and 23 are the second conducting layers.

Description

[Detailed Description of the Invention] [Technical Field] The present invention is! 14 conductor device, in particular:
The present invention relates to a technique that is effective when applied to reduce noise superimposed on power supply wiring.

[Background technology] 4A conductor! In an electronic device configured by providing a plurality of R circuit devices (rc) on a mounting board, noise generated due to the electrical operation of the IC is superimposed on the power supply wiring, causing the potential of the power supply wiring to fluctuate. If the potential of the power supply wiring fluctuates, the characteristics such as the output and threshold voltage of the transistor will become unstable.
This causes malfunctions in logic circuits, etc.

Therefore, in the electronic device, a smoothing capacitor is provided between the ICs in order to reduce the noise of the electric wiring.

The inventor of the present invention has discovered a problem in that as the packaging density of ICs increases, it becomes necessary to reduce the distance between ICs, making it difficult to provide a smoothing capacitor on a mounting board.

Note that a technique for configuring a smoothing capacitor for reducing noise in power supply wiring by providing multiple metal layers in a mounting board is described, for example, in the specification and drawings of Japanese Patent Application No. 59-81765. There is.

[Object of the Invention] An object of the present invention is to provide a technique that can satisfactorily reduce noise superimposed on power supply wiring.

Another object of the present invention is to provide a technique that can improve the packaging density by forming a smoothing capacitor in the circuit board (c) to reduce potential fluctuations in the power supply wiring.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief outline of one typical invention disclosed in this application is as follows.

By configuring a smoothing capacitor for power supply voltage stabilization using an unused semiconductor element provided in a semiconductor device or an unused area other than used semiconductor elements and wiring, the area required for providing the smoothing capacitor can be reduced. This improves the packaging density.

Hereinafter, the configuration of the present invention will be explained along with examples.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiment ■] In Embodiment I, transistors for configuring logic such as NAND gates and NOR gates are arranged in advance in a row, and the transistors are later assembled into a master slice type IC to configure logic according to customer requirements. This is an application of the invention.

1 to 7 are diagrams for explaining embodiment (2) of the present invention, in which FIG. 1 is a perspective view of an electronic device configured by mounting a plurality of ICs on a mounting board, and FIG. The figure is a plan view showing the outline of the configuration of a master slice type chip, FIG. 3 is a plan view of the main part of the cell array in FIG. 2, and FIG. 4 is a plan view showing the basic cell arrangement in FIG. FIG. 5 is an equivalent circuit diagram of a logic circuit, FIG. 5 is a layout diagram of a semiconductor element provided in a basic cell, FIG. 6 is a sectional view taken along the Vl-VI cutting line in FIG. 3, and FIG. It is a sectional view taken along the section line ■-■ in the figure.

Note that in FIGS. 1 and 3, the interlayer insulating film is not shown in order to make the structure easier to see.

In FIGS. 1 to 7, ■ is a mounting board, on which a plurality of electrodes 2 are provided around one periphery, and a plurality of I
C3 are electrically connected to each other by wiring 4 to form an electronic device.

5 is a semiconductor substrate made of P-type single crystal silicon;
The bonding pad 6, input/output circuit 7, and cell row 8 are the second
The layout is as shown in the figure. cell column 8
is a NAND gate, N.

Basic cells 8A each having a plurality of semiconductor elements for configuring a logic circuit such as an R gate are arranged in a column.

The basic cell 8A, as shown in FIGS. 3 and 5,
Resistance elements 9, 12, 13, 16 consisting of semiconductor regions, and npn type bipolar transistors 10, 11, 14, 1
5. In the transistor, the region with the symbol A attached to each number is the collector region, the region with the symbol B is the emitter region, and the region with the symbol C is the base region. The transistor 11 is made up of two transistors, and has a collector region 11A formed of two transistors.

The basic cell 8A in the upper part of FIG.
．． 12.13.16 and transistor 10.11.1
4.15 are connected by the first conductive layer 17 to form a NOR circuit as shown in FIG. Resistance element 9, 12.13°16 and transistor io, ii
, 14.15 and the conductive layer 17 are indicated by X marks.

The input terminals are the four conductive layers 17A and 17B shown in FIG. 3, and the output terminal is the conductive layer 17C.

The basic cell 8A in the center of FIG. 3 is redundant for configuring the logic circuit required by the customer. Therefore, if it was originally 1, it would remain unused.

One of the features of the present invention is that a smoothing capacitor is constructed by actively using the semiconductor element of the redundant basic cell 8A.

The smoothing capacitor is, for example, a transistor 11.14.
base area iic, 14C, collector area 11A, 1
4A, and the junction capacitance when each of the emitter regions 11B and 14B is reverse biased. Specifically, the junction capacitance between the buried layer 34 and the semiconductor substrate 5, the junction capacitance between the epitaxial layer 35 and the base IIG, 14G, and the junction capacitance between the emitter IIB, 14B and the base IIG, 14
The junction capacitance between C and C is used.

The base region IIC, 14G is connected to a Vee potential (for example, -3°0 [V] through the contact hole 19 by the conductive layer 18
) is electrically connected to the conductive layer 22 of ). Collector area IL
A, 14A and emitter regions IIB, 14B are electrically connected to a conductive layer 23 at Vcc potential (for example, 0 [V]) through a contact hole 21 by a conductive layer 20. The conductive layers 22 and 23 are the second conductive layers.

In this way, since a smoothing capacitor can be configured within a chip, semiconductor elements that constitute one circuit, especially transistor io
, 11.14.15, a smoothing capacitor can be provided in the vicinity of . Therefore, the wiring length between the smoothing capacitor and the semiconductor component is reduced, and the wiring resistance is reduced. For these reasons, noise superimposed on the power supply wiring such as the conductive layers 22 and 23 can be well absorbed by the smoothing capacitor.

Therefore, noise that unnecessarily flows into the semiconductor element can be reduced, and malfunction of the transistor due to noise can be prevented.

In this embodiment, resistive elements 9, 12, 13, 16 and transistors 10, 15 are not used as components of the smoothing capacitor. However, as above, these resistive elements 9
．． By electrically reverse biasing transistors 12, 13, 16 and 15, 10, a smoothing capacitor can be formed.

Resistance element 9.12.13.16 and transistor 10
．． By using 15 as a component of the smoothing capacitor, the capacitance value of the smoothing capacitor can be increased.

The resistive element 9.12.13.16 is connected to the conductive layer 23 at Vcc potential if it consists of an n-type semiconductor region, and to the conductive layer 22 at Vee potential if it consists of a p-type semiconductor region. The transistor l0515 has a collector region 10A.
, 15Δ and the emitter regions 10B, 15B as the conductive layer 2
Connect to 3.

Connect the base head 1dtoc, tsc to the conductive layer 22.

The conductive M24 shown in FIG.
, 0[V], the conductive layer 25 has a vbb potential (e.g. -r,
t [V]), conductive M26 is at Vcs potential (for example -1
, 8 [V]) signal line. Conductive layer 24.25.2
6 is a second conductive layer.

27 to 31 are third conductive layers, the conductive layer 27 is at Vcc potential, the conductive layer 28 is at Vtt potential, and the conductive layer 29 is at Vtt potential.
ee potential, the conductive layer 30 is a power supply wiring for supplying a Vbb potential, and the conductive layer 31 is a power supply wiring for supplying a Vcs potential.

Note that the amount of current flowing through the conductive layer M2B, 30.31 is smaller than that of the conductive layer 27 that supplies the Vcc potential and the conductive layer 29 that supplies the Vee potential.

From this, the smoothing capacitor is not connected to the conductive layers 28, 30, and 31 because the potential fluctuation caused by IC operation is small.

A field insulating film 32 is provided on the upper surface of the semiconductor substrate 5, and together with the p+ type channel stopper region 33, electrically isolates the semiconductor elements.

6 and 7, 36 is an insulating film provided on the field insulating film 32, and is mainly used in the emitter region 1.
It is used as a mask for introducing impurities when forming 0B, IIB, 14B, and 15B. 37 and 38 are interlayer insulating films, respectively.

Note that FIGS. 6 and 7 show the third conductive layers 27 to 3.
1 and a protective film are not shown.

Further, in ICs using bipolar transistors, an aluminum layer is usually used as a conductive layer. The aluminum layer easily diffuses into the silicon, forming the emitter region 10.
B, IIB, 14B, 15B and base region 10C:, I
There is a risk of destroying the bond with IG and 14C115G.

Although this is not provided in this embodiment, the emitter region 1
This can be prevented by interposing, for example, a polycrystalline silicon layer between 0B, IIB, 14B, and 15B and the conductive layer 17.20 connected thereto.

In the mask slicing IC manufacturing method, the collector region 10A of the transistor is prepared in advance before the customer requests.
, IIA, 14A, 15A, base region 10G, IIC
:, 14G, 15G, emitter region 10B, IIB, 1
4B, 15B, and only the collector regions 10A, 11A, 14A, 15A and the base regions 10C1IIG, 140.15G are formed in advance, and the emitter regions 10B, IIB, 14B, 15B are formed in advance by the customer. There is a method in which it is formed after a request is received. In the latter method, an emitter region 10B is provided in the basic cell 8A that does not constitute logic.
IIB, 14B, and 15B are never provided. Therefore, emitter regions 10B, lIB, 14B, 15B
The junction capacitance between the base region lOc, iic, 14C:, 15G cannot be used as a smoothing capacitor. However, emitter regions 10B, IIB, 14B, 1
5B and the base regions 10C, IIG, 14c, 15G are the junction capacitances of the base regions 10C, IIG, 14G, 15
C, and collector regions 10A and 11A.

Junction capacitance with L4A, 15A and collector area 10A
, IIA, 14A, 15A or the junction capacitance between the buried M34 and the semiconductor substrate 1, so there is no influence.

As can be seen from the above description, according to the present embodiment (2), by providing a smoothing capacitor using an unused semiconductor element in a master slice type chip, a smoothing capacitor can be provided on the mounting board 1. area can be made unnecessary. Therefore, since the area required to provide the smoothing capacitor is reduced, the EC3 on the mounting board l
The packaging density can be improved.

[Example ■] In Example ■, a smoothing capacitor was constructed using an unused basic cell (not numbered) for configuring the input/output circuit 7 shown in FIG. It is composed of

8 to 1I are diagrams for explaining the embodiment (2), and FIG. 8 is a layout diagram of a semiconductor element provided in a basic cell for configuring the input/output circuit 7, The figure is a plan view for explaining the smoothing capacitor configured in the basic cell, FIG. 1O is a cross-sectional view taken along the line XX in FIG. 9, and FIG. It is a sectional view taken along the xr cutting line.

First, a layerer 1- of semiconductor elements for configuring an input/output circuit will be explained using FIG.

In Figure 9, Q! , Q2, Qs, Q4 are bipolar transistors, with n-type collector regions 39, pM
Base region 40. It consists of an n+ type emitter region 41. On the surface of the collector area vA39, a conductive layer 147 is formed.
To reduce connection resistance.

An n+ type semiconductor region 39A is provided. Collector area 3
9. On the upper surface of each of the base region 4 ( ) and the emitter region 41 , an extraction electrode 42 made of a metal 1 that is difficult to diffuse into the semiconductor substrate 5 , such as tungsten or polycrystalline silicon, is provided.

The lead electrode 42 is formed by diffusing aluminum used as wiring into the semiconductor substrate 5, for example, in the emitter region 4.
This is provided to prevent electrical insulation between the base region 40 and the base region 40 from being destroyed.

R+, R2, and R3 are resistance elements consisting of p-type medium 4-body regions, and are used as load resistances.

Resistance elements R1, R2, and R3 are formed in the same process as that for forming base region 40. Extracting electrodes 42 are also provided on predetermined upper surfaces of the resistive elements R1, R2, and R3.

43, 44, 45, and 46 are the second conductive layers, respectively, and the conductive layer 43 has a Vcc potential (for example, 0 [V]).
, the conductive layer 44 has a Vee potential (for example, -3.0 [V]),
The conductive layer 45 has a Vcs potential (for example, -1.8 [V]),
The conductive layer 46 is a power supply wiring for supplying a vbb potential (for example, −1.1 [V]).

The transistor Q1. Q2, Q3, Q4 and resistance elements R1, R2, R3 constitute an input/output circuit, but a detailed description of the circuit example will be omitted.

Next, an example of a smoothing capacitor configured in the basic cell will be explained using FIGS. 9 to 11.

Note that in FIG. 9, the layout of the semiconductor elements has already been explained in FIG. 8, so the semiconductor elements are not labeled with reference numerals in order to make the configuration easier to see.

In the mask slicing type IC, semiconductor elements are initially formed in each cell for the single circuit 7, and the circuit is constructed by a wiring process after a customer's request is received. However,
The number of cells and elements is sufficient to meet any customer requirements. Therefore, some basic cells are unused although they are equipped with semiconductor elements. The feature of this embodiment is that the smoothing capacitor is constructed using this unused basic cell.

In FIGS. 9 to 11, reference numeral 47 denotes a first electrical layer, which is provided over substantially the entire area within the basic cell.

If the adjacent basic cell is also unused, the conductive layer 47
Two basic cells are provided consecutively in the same pattern as shown in the figure.

The conductive layer 47 is a P-type semiconductor region, that is, the base region 40
And in order to reverse bias the resistance elements R1, R2, and R3, they are connected to the conductive layer 44. The conductive layer 44 and the conductive layer 47 are connected through the connection hole 48 . Furthermore, the base region 40 and the resistance element R
The connection portions between 1, R2, and R3 and the conductive layer 47 are indicated by X marks and are not numbered.

By reverse biasing the base region 40 and the resistive elements R+, R2, and R3, the epitaxial HI 35
Junction capacitance can be obtained between

Further, as can be seen from FIG. 9, the proportion of the conductive layer 43 on the cell is larger than that of the other conductive layers 44.45°46. From this, Zetsu 81! Conductor 1 with A37 as dielectric
1! Layer 43 and conductive layer 47 can form a capacitor.

In this way, the conductive layer 4 at the V e potential of the first IrJg
The most distinctive feature of this embodiment is that 7 is the central electrode, and the semiconductor region and the second layer conductive layer 43 at Vcc potential form a parallel capacitor.

49, 51, and 53 are the leads '1' of the first layer mouth, respectively! It is a layer. The conductive layer 49 is located in the collector region 3 of the transistor Q+.
9 and emitter region 41 to conductive layer 43A, conductive layer 51 connects collector region 39 of 1-transistor Q3, Q4 and emitter 9Jf region 41 to conductive FIJ 43B, and conductive layer 51 connects conductor 1! Layer 53 connects collector region 39 and emitter region 41 of I-transistor Q2 to conductive layer 43B. The conductive layer 49 is conductive through the connection hole 50.
43A, the conductive layer 51 is connected to the conductive layer 43B through the connection hole 52, and the conductive layer ff153 is connected to the conductive layer 43B through the connection hole 54.

Note that the respective connections between the conductive layers 49, 51, 53, the collector region 39, and the emitter region 41 are indicated by X marks.
No code is given.

The collector region 39 and emitter region 41 are as follows.

By reverse biasing them, similar to Embodiment I, the opening with the cutting I inset R34 or the base area 4
0 and constitutes a smoothing capacitor.

As can be seen from the above explanation, according to Example H, the first conductive layer and the second conductive layer are placed in the unused area other than the used semiconductor elements and wiring in the cell constituting the input/output circuit. By forming a smoothing capacitor with the conductive layer,
It is possible to eliminate the need for a smoothing capacitor to be provided on the mounting board. Therefore, the mounting density of ICs on the mounting board can be improved.

By constructing the first smoothing capacitor using an unused semiconductor element, constructing the second smoothing capacitor by constructing the first conductive layer and the second conductive layer, and connecting them in parallel. , the capacitance value of the smoothing capacitor can be increased.

[Effects] According to the new technology disclosed in the present application, the following effects can be obtained.

(1). Since the smoothing capacitor made of a junction capacitor is constructed by reverse biasing the unused semiconductor elements in the chip, the smoothing capacitor can be provided near the semiconductor elements, especially the transistors.

(2). By configuring a smoothing capacitor with the first conductive layer and the second conductive layer in an unused area other than the used semiconductor elements and wiring in the cell that constitutes the input/output circuit, it is possible to It is possible to eliminate the need for a smoothing capacitor to be provided.

(3). According to (1) and (2) above, the wiring length between the smoothing capacitor and the semiconductor element can be reduced, so the wiring resistance between them is reduced, and noise can be well absorbed by the smoothing capacitor. can.

(4) According to (3) above, the noise superimposed on the tt power supply wiring can be absorbed in the vicinity of the semiconductor element, so that the noise flowing into the semiconductor element can be reduced.

(5). By (4) above, it is possible to improve the reliability of the IC.

B (6) (- According to (1) and (2) above, it is possible to eliminate the need for a smoothing capacitor to be provided on the mounting board.

(7) According to (6) above, it is possible to improve the mounting density of ICs on the mounting board.

(8) Construct a first smoothing capacitor using an unused semiconductor element, configure a second smoothing capacitor with a first conductive layer and a second conductive layer, and connect them in parallel. By connecting them, the capacitance value of the smoothing capacitor can be increased.

As above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

For example, one aspect of the present invention provides an I
It can be applied not only to ICs but also to IC1s that are superior to MISFETs, such as gate arrays. If the semiconductor region for configuring the MISFET is n-type, this semiconductor region is connected to a power supply wiring with a higher potential than the semiconductor substrate, and if it is p-type, it is connected to the same potential as the semiconductor substrate or lower potential than the semiconductor substrate. Connect to the power supply wiring.

[Brief explanation of drawings]

1 to 7 are diagrams for explaining Embodiment 1 of the present invention. FIG. 1 is a perspective view of an electronic device configured by mounting a plurality of ICs on a mounting board. FIG. 2 is a plan view schematically showing the configuration of a master slice type chip, and FIG. 3 is a plan view of the main part of the cell array in FIG. 2. 4 is an equivalent circuit diagram of the logic circuit configured in the basic cell in FIG. 3, FIG. 5 is a layout diagram of a semiconductor element provided in the basic cell, and FIG. 6 is a Vl diagram in FIG. 7 is a sectional view taken along the -Vl cutting line; FIG. 7 is a sectional view taken along the ■-■ cutting line in FIG. 3; FIG. 8 to FIG. FIG. 8 is a layout of semiconductor elements provided in a basic cell for configuring an input/output circuit, FIG. 9 is a plan view for explaining a smoothing capacitor configured in the basic cell, and FIG. 10 is a sectional view taken along the line XX in FIG. 9, and FIG. 11 is a sectional view taken along the line xr-xt in FIG. 9. 1... Mounting board, 2... Electrode, 3... IC14.
... Wiring, 5... Semiconductor substrate, 6... Bonding PC, 7... Input/output circuit, 8.8A... Cell row, 9
．． 12.13, IG, R+, R2, R3...Load resistance, 17.18°20.22.23.24.25.26
．． 27.28.29.30.31.42.43.43Δ
, 43B, 44.45.4G, 47.49.51.53
...Conductive layer, 19.21.4B, 50.54... Connection hole, 32... Field insulating film, 33... Channel stopper region, 34... Buried layer, 35... Epitaxial layer , 36.37.38...Insulating film. Figure 2 Figure 3 Figure 8 Figure 9

Claims (1)

[Claims] 1. A master slice type semiconductor device equipped with a power supply voltage stabilizing capacitor, in which an area other than unused semiconductor elements or used semiconductor elements and wiring provided in the semiconductor device is used to A semiconductor device comprising a smoothing capacitor for stabilizing power supply voltage. 2. The smoothing capacitor is configured by applying a power supply to the unused semiconductor elements in the cell column, which is constructed by arranging a plurality of semiconductor elements in the column direction to constitute logic circuits such as NAND gates and NOR gates, so as to provide a reverse bias. 2. The semiconductor device according to claim 1, wherein the semiconductor device is configured by a junction capacitance between a semiconductor substrate and a semiconductor element by connecting wiring. 3. The semiconductor device according to claim 1 or 2, wherein the semiconductor element is a bipolar transistor. 4. The smoothing capacitor includes a first conductive layer connected to a first potential in an unused area between semiconductor elements of an input/output circuit that is not used in a peripheral circuit of a semiconductor device;
2. The semiconductor device according to claim 1, further comprising a second conductive layer provided on the conductive layer via an insulating film and connected to a second potential. 5. The semiconductor device according to claim 4, wherein the second conductive layer is a power supply wiring extending over an input/output circuit.