JPH0595049A - Semiconductor device and its mounting method - Google Patents

Abstract

PURPOSE:To reduce the impedance and the inductance of wiring and the heat resistance of a semiconductor device, and elevate the degree of freedom in pattern layout by connecting the rear wiring corresponding to the kind of the potential applied to the kind of the electrode of a semiconductor element with a corresponding electrode through a via hole. CONSTITUTION:A desired electric circuit is constituted by providing semiconductor elements 261-263 in optional proper layout on the surface side of a board 24. On the other hand, on the rear of the board 24, plural kinds of rear wirings 321-322 corresponding to the kinds of the potential applied to the electrodes of the semiconductor elements 261-263 are provided. Moreover, via holes 301, 302, and 303 piercing the board 24 are provided, and through these, the corresponding electrodes of the semiconductor elements 261-263 and rear wirings 321-322 are connected directly through these. Hereby, the impedance and the inductance of the wiring can be reduced, and the heat resistance of the semiconductor device can be reduced, and the degree of freedom in the pattern layout on the surface side of a board can be elevated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its mounting method.

[0002]

2. Description of the Related Art Conventionally, a wire bonding technique has been widely known as the most general technique for mounting a semiconductor integrated circuit in a package. Here, FET (Fi
A semiconductor integrated circuit using an eldEffect Transistor, such as DCFL (Direct Cou)
Considering the case where the wire bonding technology is used for mounting the pled FET logic circuit, in this case, the FET, the wiring, and the bonding pad are provided on the front side of the substrate, and the wiring is arranged from the FET to the bonding pad in the peripheral portion of the substrate. The bonding pads on the periphery and the bonding pads of the package are connected via bonding wires. Therefore, since the wiring is arranged from the FET to the bonding pad in the peripheral portion of the substrate, there arise problems that the pattern layout on the front side of the substrate is restricted, multilayer wiring is required, and the wiring becomes redundant. Especially in power devices and microwave band devices using FETs, it is desired to reduce the grounding inductance, but the wiring becomes redundant and the inductance of the wiring increases or the inductance of the bonding wire increases. There is a problem that the ground inductance cannot always be reduced sufficiently. Therefore, as a conventional technique for solving these problems, for example, Document 1: IEEE TRNSACTIONS ONE
LECTRON DEVICES (AY-A-Transactions on Electron Devices),
VOL. ED-25, NO. 10, pp. 1218-1
221 and 1978, a method in which circuit elements on the front and back of the substrate are connected via a via hole penetrating the substrate and a method by a flip chip method have been proposed.

FIG. 8 is a sectional view schematically showing the structure of a semiconductor device used in the former conventional mounting technique. The semiconductor device shown in the figure includes a substrate 10 and an FE provided on the front side of the substrate 10.
T121 to 124, via holes 141 to 143 penetrating the substrate 10, and backside wiring 1 provided on the backside of the substrate 10.
6 and 6.

Each of the FETs 121 to 124 has an active layer formed on the substrate 10 (not shown). FET 121 has source, gate and drain electrodes 181, 182 and 1
83 is provided. The FET 122 comprises source, gate and drain electrodes 185, 184 and 183. FET1
Reference numeral 23 designates source, gate and drain electrodes 185, 186.
And 187. FET 124 includes source, gate and drain electrodes 189, 188 and 187. These FETs 121 to 124 form a DCFL circuit, and here, the source electrodes 181, 185 and 1 of these FETs are used.
89 is connected to a common ground potential. Therefore, via holes 141, 142 and 143 are provided in the substrate portions corresponding to the source electrodes 181, 185 and 189 so as to penetrate the substrate 10. Then, the backside wiring 1 is formed on the entire back surface of the substrate 10 and in the via holes 141 to 143.
6 is provided, and the back side wiring 16 and the source electrodes 181, 185 and 189 are connected to each other through the via holes 141, 142 and 143.

In this semiconductor device, the source electrode 181,
185 and 189 are grounded by using the via holes 141 to 143 and the back side wiring 16, and therefore wirings for grounding these source electrodes need not be provided on the front side of the substrate 10, so that the degree of freedom in designing the pattern layout on the front side of the substrate is reduced. There is an advantage that it can increase. Further, as compared with the case of grounding only the front side wiring without using the via hole, the back side wiring 16
The wiring length can be shortened, and since wire bonding is not required, the inductance and impedance of the back wiring 16 can be reduced.

FIG. 9 is a sectional view schematically showing the structure of a semiconductor device used in the latter conventional mounting technique by the flip chip method. The components corresponding to the above-mentioned conventional components are denoted by the same reference numerals, and detailed description of the same points as the above-described conventional components will be omitted.

The semiconductor device shown in FIG.
121 to 124 and bumps 201 to 203, and these bumps 201, 202 and 203 are provided on the source electrodes 181, 185 and 189, respectively. When mounting this semiconductor device in a package, the bumps 201 to 203 are connected to the grounding wiring of the package while the semiconductor device is face down. In this semiconductor device,
The electrodes 181, 185 and 189 of the FET are connected to the bump 20.
Since it is grounded by directly connecting to the package via 1, 202 and 203, there is an advantage that the degree of freedom in designing the pattern layout on the front side of the substrate can be increased. Further, since the wiring length for grounding can be shortened, the inductance and impedance of the grounding wiring can be reduced.

[0008]

However, in the case of the former semiconductor device, since the back side wiring is provided on the entire back surface of the substrate and the back side wiring is used only as the ground wiring, only one kind of wiring can be reduced on the front side of the substrate. Therefore, there is a problem in that the degree of freedom in designing the pattern layout on the front side of the substrate cannot always be sufficiently increased.
Further, in order to improve the electrical characteristics of a semiconductor device, particularly a power device or a microwave band device such as a DCFL circuit, not only the inductance and impedance of the ground wiring are reduced but also other types such as the inductance of the power voltage wiring and It is desired to reduce the impedance as well. However, in the former semiconductor device, since only one type of backside wiring is provided on the entire back surface of the substrate, there is a problem in that it is not possible to reduce the inductance and impedance of a plurality of types of wiring.

In the latter semiconductor device, the electrodes of the front side semiconductor element are directly electrically connected to the package by a face-down method, whereby the wiring length can be shortened and the inductance and impedance of a plurality of types of wiring can be reduced. It is technically not always easy to form bumps used for electrical connection between the element electrodes and the package, and since the bumps are located between the substrate and the package after mounting on the package, the bumps between the semiconductor element electrodes and the package are not formed. There was a problem that it was difficult to check the connection failure between the two. Further, in the latter semiconductor device, the semiconductor device is mounted face down, so that there is a problem that the heat dissipation of the semiconductor device cannot be performed sufficiently.

An object of the present application is to solve the above-mentioned conventional problems and to provide a semiconductor device and a mounting method thereof in which desired lengths of plural kinds of wirings can be shortened.

[0011]

To achieve this object, a semiconductor device according to the first invention of the present application is a semiconductor substrate, a semiconductor element provided on the front side of the semiconductor substrate, and a via penetrating the semiconductor substrate. A hole and a back side wiring provided on the back side of the semiconductor substrate and connected to the electrode of the semiconductor element through a via hole, and a plurality of types of back side wiring corresponding to the type of potential applied to the electrode of the semiconductor element are provided. It is characterized in that the wiring is connected to an electrode of a semiconductor element to which a potential of a type corresponding to the back wiring is applied.

According to the semiconductor device mounting method of the second invention, the semiconductor device of the first invention is mounted in a package having a lead wiring, and the back wiring of the semiconductor device and the lead wiring of the package corresponding to the back wiring are provided. When connecting
A first terminal portion extending in a predetermined direction is provided on the back wiring, a second terminal portion extending along the extending direction of the first terminal portion is provided on the lead wiring, and the first terminal portion and the second terminal portion are provided. Is moved along these extending directions and rubbed against each other, and the first terminal portion and the second terminal portion are connected by a eutectic method.

[0013]

According to the first invention, two or more kinds of back side wirings corresponding to the kinds of potentials applied to the electrodes of the semiconductor element are provided,
Since the plural kinds of back side wirings are connected to the electrodes of the corresponding semiconductor element through the via holes, for example, the impedance and the inductance of the plural kinds of wirings are reduced, or the thermal resistance of the semiconductor device is further effectively reduced. Alternatively, the degree of freedom in pattern layout on the front side of the substrate can be more effectively increased.

According to the second invention, the first terminal portion and the second terminal portion respectively extend in the same direction. Therefore, even if the semiconductor device of the first invention is provided with a plurality of back side wirings and the package is also provided with a plurality of lead wirings, the corresponding first terminal portion and second terminal portion to be connected are in contact with each other. so,
By moving these terminal portions along these extending directions and rubbing them together, it is possible to collectively connect a plurality of back side wirings and a plurality of lead wirings corresponding to each other in the same step.

[0015]

Embodiments of the first and second inventions will be described below with reference to the drawings. The drawings are only schematic representations so that the invention can be understood, and are therefore not intended to limit the invention to the illustrated examples.

FIG. 1 and FIG. 2 are a cutaway perspective view and a cross-sectional view schematically showing the construction of the essential part of the first embodiment of the invention, and FIG. 2 is a cross-section taken along the line II--II of FIG. Show.

As shown in these figures, the semiconductor device 22 of this embodiment includes a semiconductor substrate 24 and semiconductor elements 261 to 261.
263, via holes 301 to 303, and back side wiring 32
1, 322.

The semiconductor substrate 24 is, for example, semi-insulating GaAs.
It is a substrate, and the semiconductor elements 261 to
263 is provided. The semiconductor elements 261-263 are, for example, F
ET, and these semiconductor elements 261-263 are 26
1, 262 and 263 are arranged in a line in this order. The semiconductor element 261 has a source electrode 341 and a gate electrode 342.
And the drain electrode 343, the semiconductor element 262 includes a source electrode 345, a gate electrode 344, and a drain electrode 3.
43, and the semiconductor element 263 has a source electrode 34.
5, a gate electrode 346 and a drain electrode 347. The drain electrode 343 is a common electrode for the semiconductor elements 261 and 262, and the source electrode 345 is the semiconductor element 26.
2, 263 is a common electrode. Each semiconductor device includes an active layer (not shown), the source and drain electrodes form an ohmic junction with the active layer, and the gate electrode forms a Schottky junction with the active layer.

On the front side of the substrate 24, front side wirings and semiconductor elements are provided in any suitable pattern layout (semiconductor elements or electric circuit elements other than the semiconductor elements 261 to 263 described above are provided in some cases. A desired electric circuit is configured, and in this embodiment, for example, a front side wiring 28 on the front side of the substrate 24, a front side wiring (not shown) different from the wiring 28, and semiconductor elements 261 to 263 are provided, The semiconductor elements 261 to 2 corresponding to these front side wirings, respectively.
The electrodes and the electrodes 63 are connected to each other to form an electric circuit, for example, a DCFL circuit. And the source electrode 3
41 and 345, ground potential and drain electrodes 343 and 3
A power supply voltage is applied to 47.

On the back side of the substrate 24, semiconductor elements 261 to
A plurality of types of back side wirings 321 and 322 corresponding to the type of potential applied to the electrode of H.263 are provided. In this embodiment, the back wirings 321 and 322 are of two types, that is, a power supply voltage and a ground potential, and the back wiring 321 is an electrode for ground potential and the back wiring 322 is an electrode for power supply voltage. The back wiring 321 is connected to electrodes of a semiconductor element to which a potential corresponding to the wiring is applied, that is, source electrodes 341 and 345 to which a ground potential is applied in this embodiment. Further, the back wiring 322 is connected to the back wiring 322. An electrode of a semiconductor element to which a potential of a type corresponding to the wiring is applied, in this embodiment, drain electrodes 343 and 347 to which a power supply voltage is applied are connected.

Therefore, via holes 301 and 302 penetrating the substrate 24 are provided at positions corresponding to the source electrodes 341 and 345, respectively.
The back side wiring 321 is also provided inside 2 and the source electrode 34 is directly provided through the via holes 301 and 302.
1, 345 and the back side wiring 321 for ground potential are connected. In addition, the substrate 24 is placed at a position corresponding to the drain electrode 343.
A via hole 303 penetrating therethrough is provided, and a backside wiring 322 is also provided inside the hole 303, and the drain electrode 323 and the backside wiring 322 for power supply voltage are directly connected via the via hole 303. Also, the drain electrode 347 is connected to the back side wiring 3 for the power supply voltage through the via hole.
Although it may be directly connected to the gate electrode 22 depending on the arrangement position, in this example, the front side wiring 28 is connected to the gate electrode 3
The drain electrodes 347 to 343 are provided so as not to make electrical contact with the electrodes 46 and 344, and the drain electrodes 347 and 343 are connected by the front side wiring 28, and the front side wiring 28, the drain electrode 343, and the via hole 303.
The drain electrode 347 and the back side wiring 322 for the power supply voltage are indirectly connected via the. For example, when the drain electrode 347 and the backside wiring 321 for ground potential do not overlap with each other in plan view, the drain electrode 347 is directly connected to the backside wiring 322 for power supply voltage through a via hole. When the drain electrode 347 and the backside wiring 321 for ground potential overlap each other in plan view, the drain electrode 347 is indirectly connected to the backside wiring 322 for power supply voltage by using the front side wiring. do it.

FIG. 3 is a bottom view schematically showing the structure of the essential part of the first embodiment of the present invention, showing the respective positions of the via holes 301 to 303 and the back side wirings 321 to 322. As shown in the figure, in this embodiment, the back side wirings 321 and 32 are
The back side wiring 32 has an overall shape of 2 in a stripe shape extending in a predetermined direction (direction indicated by an arrow P in the drawing).
The whole 1 and the whole 322 are used as a first terminal portion connected to a lead wire of a mounting package of a semiconductor device, which will be described later. The back side wirings 321 and 322 are not solidly provided on the entire back side of the substrate 24, but are provided on a part thereof, and the back side wirings 321 and 322 are arranged in parallel so as to be sufficiently separated to be electrically separated. And the back wiring 321
The via holes 301 and 302 are provided in the area where the via wirings are provided, and the via hole 303 is provided in the area where the backside wiring 322 is provided.

Next, an embodiment of the second invention will be described.
This embodiment is an example of implementing the embodiment of the first invention described above.

FIG. 4 is a diagram showing an example of the structure of a mounting package of a semiconductor device used for implementing the second invention, showing the main part of the mounting package, particularly the terminal part structure of the lead-out wiring connected to the back side wiring of the semiconductor device. It is a notch perspective view which shows schematically. The package 35 shown in FIG.
And lead wires 381 and 382.

The package 35 is a lead wiring of a type corresponding to the type of the back side wiring, in this example, the lead wiring 3 for ground potential.
81 and a lead wire 382 for the power supply voltage. The lead wiring 381 is a second terminal portion 381a connected to the first terminal portion of the back side wiring 321 for ground potential, and the lead wiring 382 is a second terminal portion connected to the first terminal portion of the back side wiring 322 for power supply voltage. 382a. Although not shown, a lead terminal connected to an external electric circuit such as ground or a power supply voltage or other circuit is provided in the peripheral portion of the package body 36, and the lead wires 381 and 382 are provided on the side opposite to the second terminal portion. The parts are drawn from the second terminal portions 381a and 382a to lead terminals connected to the ground and the power supply voltage, respectively. At least the second terminal portions 381a and 382a of the lead wirings 381 and 382 each have a striped shape extending in the predetermined direction P similarly to the first terminal portion, and the second terminal portions 381a and 382a are arranged in parallel. To do.

FIG. 5 is a diagram provided for explaining the embodiment of the second invention, and is a perspective cutaway view showing a state in which the first terminal portion of the back side wiring is placed on the second terminal portion of the lead wiring. .. Reference numerals A and B in the figure denote via holes 301 and 302, respectively.
A portion of the back side wiring 321 disposed inside is shown, and a symbol C shows a portion of the back side wiring 322 arranged inside the via hole 303.

As shown in the figure, in mounting the semiconductor device 22 on the package 35 in this embodiment, first, the first terminal portions of the back side wirings 321 and 322 and the lead wirings 381 and 382 corresponding to these are formed. Two-terminal portion 381a,
382a and the corresponding first and second terminal portions are brought into contact with each other.

Since the first terminal portions of the back side wirings 321 and 322 and the second terminal portions 381a and 382a are connected by the eutectic method using, for example, Au and Sn, in this embodiment, at least the back side wirings 321 and 322 are connected. For example, one terminal has a two-layer structure including an Au thin film and a Sn thin film sequentially provided from the substrate 24 side, and is formed of a material suitable for the eutectic method.
The Au thin film and the Sn thin film are formed, for example, by the selective plating method.
It is selectively formed at a predetermined position. Along with this, the lead wire 3
81, 382 at least second terminal portions 381a, 382
a is an Au thin film, for example, and is formed from a material suitable for the eutectic method.

Next, the first terminal portions of the back wirings 321 and 322 and the second terminal portions 381 of the lead wirings 381 and 382.
a and 382a are pressed against each other and brought into contact with each other,
The first and second terminal portions are moved along the extending direction P and rubbed together to connect the first and second terminal portions by the eutectic method. At this time, these first and second terminal portions are rubbed together while being heated to, for example, about 300 ° C., as is usually done by the eutectic method. Further, as is usually done by the eutectic method, the first and second terminal portions are reciprocally moved to rub these terminal portions together, so that the adhesion and parallelism between the back side wiring and the lead-out wiring are practically sufficient. I shall. The rubbing of the first and second terminal portions causes a eutectic reaction of Au and Sn to connect the corresponding first and second terminal portions. Through the connected first and second terminal portions, the semiconductor device 2
2 is fixed to the package 35.

In this embodiment, in order to prevent a short circuit when connecting the first and second terminal portions by the eutectic method, the first and second terminal portions are extended in a predetermined direction P, and in this direction P The first and second terminal portions were moved to connect these terminal portions.

In order to prevent a short circuit, the distance between the back wirings 321 and 322 adjacent to each other and the lead wiring 3 adjacent to each other
The separation distance between 81 and 382 is determined so as not to cause a short circuit while taking into account the alignment accuracy of the first and second terminal portions and the spread of the wiring pattern due to rubbing. In order to prevent a short circuit, it is preferable that the distance between them be 100 μm or more.

In this example, since the first and second terminal portions are stripe-shaped, they have a larger area than the bumps in the flip chip method, and therefore the first and second terminal portions can be easily formed and connected. Also, the alignment accuracy at the time of connecting the second terminal portion can be relaxed as compared with the flip chip method. Further, the back side wiring of the semiconductor device has a concave portion at a position corresponding to the via hole, but since this concave portion is sufficiently small compared to the contact area of the first and second terminal portions, even if this concave portion is present. There is no problem in ensuring the parallelism of the first and second terminal portions. Further, since the semiconductor device is mounted face up on the package, the heat dissipation of the semiconductor device is also good. Also, since plural kinds of back side wirings are respectively connected to the electrodes of the corresponding semiconductor element through via holes or, in some cases, via holes and front side wirings, plural kinds of wirings are used for ground potential and power supply voltage. Impedance and inductance of wiring can be reduced, or thermal resistance of the semiconductor device can be reduced more effectively, or the degree of freedom of pattern layout on the front side of the substrate can be increased more effectively. In an electric circuit such as a DCFL circuit,
By reducing the impedance of the power supply voltage wiring, it is possible to reduce variations in the magnitude of the power supply voltage applied to each semiconductor element forming the electric circuit.

FIG. 6 is a diagram showing another example of the structure of the mounting package used for implementing the second invention, and schematically shows the structure of the main part of the mounting package, particularly the lead-out wiring connected to the back side wiring of the semiconductor device. It is a notch perspective view.

The mounting package shown in FIG. 4 is suitable for a semiconductor device having a relatively small device scale.
The mounting package shown in FIG. 6 is suitable for a case where the semiconductor device has a relatively large device scale and a high degree of integration and it is necessary to disperse the via holes of the semiconductor device over a wide range.

The package 40 shown in FIG. 6 includes a package body 36 and lead wires 421 and 422. The package 40 is provided with a lead wiring of a type corresponding to the type of the back wiring, in this embodiment, a lead wiring 421 for ground potential and a back wiring 422 for power supply voltage. The lead wire 421 is composed of striped or rectangular second terminal portions 421a to 421c and a common connection portion 421d for commonly connecting these terminal portions. Similarly, the lead wiring 422 is a striped or rectangular second terminal. The parts 422a to 422c and a common connection part 422d that connects these terminal parts in common. The second terminal portions 421a to 421c for ground potential and the second terminal portions 422a to 422c for power supply voltage are provided so as to extend along the constant direction P, and one side of these second terminal portions is provided. These second terminal portions are arranged in parallel so as to be pointed to each other.
Then, the other end portions of the ground potential second terminal portions 421a to 421c are connected to the common connection portion 421d, and these second terminal portions are connected to the ground potential lead terminal (not shown) through the common connection portion 421d. To do. Also, the other end of the second terminal portions 422a to 422c for power supply voltage is connected to the common connection portion 422d, and these second terminal portions are connected to the common connection portion 42.
It is connected to a lead terminal (not shown) for a power supply voltage via 2d.

As described above, by providing a plurality of types of lead wirings and a plurality of types of back side wirings respectively dispersed at arbitrary and suitable positions, it is possible to increase the degree of freedom of the positions where the via holes of the semiconductor device are provided.

In this example, in order to prevent the occurrence of a short circuit when each second terminal portion is connected to the corresponding first terminal portion by the eutectic method, for example, the separation distance L between the adjacent second terminal portions is set.
1 is 100 μm or more, and the first and second terminal portions are 300
The distance L2 between the common connection part for ground potential and the second terminal part for power supply voltage, the common connection part for power supply voltage, and the second connection part for ground potential are set so that they are moved and rubbed to each other in the moving range of μm. The distance L3 between the terminal portions is 400 μm which is larger than the moving range of the first and second terminal portions, respectively.
It should be m. The width W of the second terminal portion depends on the layout of the semiconductor element of the semiconductor device and the size and shape of the via hole, but is set to, for example, 300 μm or more so that the current of the second terminal portion can be set to a desired small value. Take a large cross-sectional area in the direction orthogonal to the flowing direction.
The length L4 of each second terminal portion is preferably longer than the length L5 (see FIG. 2) of each backside wiring of the semiconductor device to ensure the reliability of the connection between the first and second terminal portions. L5 = 2
If it is 000 μm, L4 may be set to a length L4 = 2500 μm, which is longer than L5 by several hundred μm.

FIG. 7 is a diagram showing another example of the structure of the mounting package used for carrying out the second invention, and schematically shows the main part of the mounting package, particularly the structure of the lead-out wiring connected to the back side wiring of the semiconductor device. It is a notch perspective view.

The package 46 shown in FIG. 7 is a package 46 suitable for a semiconductor device having a relatively large scale, and includes a package body 36 and lead wires 461 and 462.
463. In this example, there are three types of backside wiring of the semiconductor device, and the package 44 has three types of lead wiring 4
61 to 463. The lead wiring 461 includes stripe-shaped second terminal portions 461a to 461e and a common connection portion 461f that commonly connects these second terminal portions.
2 includes stripe-shaped second terminal portions 462a to 462b and a common connection portion 462c that commonly connects these second terminal portions, and the lead wire 463 has a striped second terminal portion 463.
a to 463b and a common connection portion 463c that commonly connects these second terminal portions. These three types of lead wires 461 to
Each second terminal portion of 463 is provided so as to extend along the constant direction P, and one side of each of these second terminal portions is provided so as to point to each other, and these second terminal portions are arranged in parallel. Then, the other end of each of the second terminal portions of the lead wiring 461 is connected to the common connection portion 461f, and the potential corresponding to the type of the lead wiring 461 is connected to each of the second terminal portions via the common connection portion 461f. It is connected to an applied lead terminal (not shown). Similarly, the second terminal portions of the lead wires 462 and 463 are connected to the lead terminals (not shown) to which a potential corresponding to the type of the lead wires 462 and 463 is applied, via the common connection portions 462c and 463c.

Also in this example, a plurality of types of lead wires 461 to 4 are provided.
By providing the 63 and a plurality of types of back side wirings in a dispersed manner at arbitrary and suitable positions, it is possible to increase the degree of freedom of the position where the via hole of the semiconductor device is provided.

These inventions are not limited to the above-mentioned embodiments, and therefore, the structure, shape, arrangement position, arrangement number, numerical condition, forming material and the like of each component can be changed arbitrarily and suitably. ..

For example, front side wirings and / or electrodes of semiconductor elements are provided in multiple layers on the front side of the semiconductor substrate, and via holes are provided from the back side of the substrate to the front side wirings of each layer and / or the electrodes of semiconductor elements. Alternatively, the electrode of the semiconductor element may be connected to the back wiring via the via hole. The type of backside wiring may include types other than ground potential and power supply voltage. In addition, the semiconductor element is FE
An element having any suitable structure other than T can be used.

[0043]

As is apparent from the above description, according to the first invention, two or more kinds of back side wirings corresponding to the types of potentials applied to the electrodes of the semiconductor element are provided, and a plurality of kinds of back side wirings are provided. Since each is connected to the corresponding electrode of the semiconductor element through a via hole, for example, impedance and inductance of a plurality of types of wiring can be reduced, or the thermal resistance of the semiconductor device can be further effectively reduced, or the front surface of the substrate can be reduced. The degree of freedom of the pattern layout can be increased more effectively. ..

In the practice of the first invention, a plurality of types of wirings for which impedance and / or inductance are desired to be reduced are mainly arranged as back side wirings, and these plurality of types of back side wirings are connected to electrodes of corresponding semiconductor elements through via holes. Is preferably connected to. By doing so, it is possible to reduce the impedance and / or the inductance with respect to a plurality of types of wiring, and as a result, it is possible to further improve the circuit characteristics of the electric circuit, particularly the high frequency electric circuit.

According to the second invention, the first terminal portion and the second terminal portion respectively extend in the same direction. Therefore, even if the semiconductor device of the first invention is provided with a plurality of back side wirings and the plurality of lead wirings is provided in the mounting package of this device, the corresponding first terminal portion and second terminal portion to be connected are brought into contact with each other. With a simple method of moving these terminal portions along these extending directions and rubbing them in the above state, it is possible to collectively connect the plurality of wirings in the same step. Therefore, the semiconductor device can be mounted easily and quickly.

Further, even when a plurality of back side wirings and a plurality of lead-out wirings are provided, the first terminal portion and the second terminal portion of these wirings are provided so as to extend in the same direction, and these wirings are provided in the extending direction. By moving and rubbing the first terminal portion and the second terminal portion together, a short circuit between adjacent terminal portions can be eliminated.

[Brief description of drawings]

FIG. 1 is a cutaway perspective view schematically showing a main part configuration of an embodiment of a first invention.

FIG. 2 is a cross-sectional view schematically showing a main part configuration of an embodiment of the first invention.

FIG. 3 is a bottom view schematically showing a main part configuration of an embodiment of the first invention.

FIG. 4 is a cutaway perspective view of a main part schematically showing an example of the configuration of a package used for implementing the second invention.

FIG. 5 is a cutaway perspective view of an essential part for explaining an embodiment of the second invention.

FIG. 6 is a main part plan view schematically showing an example of the configuration of a package used for implementing the second invention.

FIG. 7 is a main part plan view schematically showing an example of the configuration of a package used for implementing the second invention.

FIG. 8 is a sectional view schematically showing an example of a configuration of a semiconductor device used in a conventional mounting technique.

FIG. 9 is a sectional view schematically showing another example of the configuration of the semiconductor device used in the conventional mounting technique.

[Explanation of symbols]

22: Semiconductor device 24: Semiconductor substrate 261 to 263: Semiconductor element 28: Front side wiring 301 to 303: Via hole 321 to 322: Back side wiring 341 to 347: Electrode 35, 40, 46: Mounting package 421 to 422, 461 to 463 : Lead wiring 421a to 421c, 422a to 422c, 461a to
461e, 462a to 462b, 463a to 463b:
Second terminal part

Claims (3)

[Claims] 1. A semiconductor substrate, a semiconductor element provided on the front side of the semiconductor substrate, a via hole penetrating the semiconductor substrate, and a back side wiring provided on the back side of the semiconductor substrate and connected to an electrode of the semiconductor element through the via hole. In a semiconductor device comprising: a semiconductor element to which a plurality of types of back side wirings corresponding to the types of potentials applied to the electrodes of the semiconductor element are provided, and the back side wirings are applied with a potential of the type corresponding to the back side wirings. A semiconductor device, characterized in that it is connected to the electrode of. 2. The semiconductor device according to claim 1, wherein the back side wiring includes at least two kinds of back side wirings for a power supply voltage and a ground potential. 3. The semiconductor device according to claim 1 is mounted in a package having a lead wiring, and when connecting the back side wiring of the semiconductor device and the lead wiring of the package corresponding to the back side wiring, it extends in a predetermined direction. The first terminal portion is provided on the back side wiring, the second terminal portion extending along the extending direction of the first terminal portion is provided on the lead wiring, and the first terminal portion and the second terminal portion are extended from these. A method for mounting a semiconductor device, comprising: moving the semiconductor device along a direction in which the first terminal portion and the second terminal portion are connected by a eutectic method.