JPS61123313A - Analog-digital converting circuit - Google Patents

Abstract

PURPOSE:To improve the linearity of an output digital signal by feeding back a DC level of a video signal inputted to two A/D converting circuits via a differential amplifier to which a reference voltage is applied. CONSTITUTION:Video signals (b, a) different in polarity and DC component from each other are fed to A/D converters 14, 15 from two amplifier circuits 13, 12. The DC level difference between the converters 14, 15 is biased by connecting an effective range of the converter 14 and the effective range of the converter 15 accurately. In adding input signals to the converters 14, 15, since the polarity of the video signals (a, b) is inverted, only the DC component is left. The difference between the DC component and the reference voltage of a reference voltage source 18 is amplified, fed back to the amplifier circuit 13 to stabilize the DC level of the input signal to the A/D converter 14. Digital data from the converters 14, 15 are composed by an operation circuit 16 and a digital data having 1 bit more than the quantized bit number of the converters 14, 15 is outputted.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is an A/
The present invention relates to D conversion circuits, and particularly to human/D converters for television signals.

(Prior art) Conventionally, in analog-to-digital conversion of television signals, the conversion speed is high and the number of output bits is high, which is expensive. I was getting output.This kind of conventional A
A block diagram and waveform diagram of an example of the /D conversion circuit are shown in FIGS. 3 and 4 (a).

(shown in bl) The next video signal supplied to the input terminal 1 is sent to the A/D converter 4 via the inverting amplifier circuits 2 and 3.
, 5. The output digital data of the A/D converters 4 and 5 are combined by an arithmetic circuit 6 and sent to an output terminal 7.
Send output digital data to. A/D converter 4
A reference voltage from a reference voltage source 8 is supplied to A and 5.
A clock is supplied to the /D converters 4 and 5 and the arithmetic circuit 6 from a clock pulse input terminal. The A/D converters 4 and 5 each divide between the ground potential and the reference voltage, and in the case of 8 bits, O to 255 for the input analog voltage.
The data is output to the calculation circuit 6. DC level adjuster 9
adjusts the DC level of the input signal of the A/D converter 4.5 to obtain the input signals a I , b / (see Fig. 3) of the two A/D converters as shown in Fig. 4 1al and (bl). This is provided to maintain the DC level by 2V.

(Problem to be Solved by the Invention) In the conventional A/D conversion circuit described above, the difference in the DC component between the signals a' and b' of the outputs of the inverting amplifier circuits 2 and 3 is such that the output data can be converted linearly. The K to be changed needs to be within an error of several mV, but it has the disadvantage that it tends to fluctuate due to fluctuations in ambient temperature, power supply voltage, etc.

The present invention provides an A
/D conversion circuit.

(Means for solving the disadvantages) The A/D conversion circuit of the present invention includes first and second amplifier circuits that input an analog signal and output the DC levels at different levels; and first and second A/D converters receiving outputs from each of the second amplifier circuits;
A signal obtained by mixing the outputs of the first and second amplifier circuits and a reference voltage that sets the full scale of the first and second OA/D converters are mixed with the analog signal in the first amplifier circuit. It is configured to include a differential amplifier circuit that outputs a DC component, and an arithmetic circuit that synthesizes and outputs digital signals from the first and second A/D converters.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an A/D conversion circuit according to the present invention. The video signal supplied to the input terminal 11 is input to the inverting amplifier circuit 12. After passing through the non-inverting amplifier circuit 13, the human/
The data is sent to D converters 14 and 15, A/D converted, and output digital data is sent from the arithmetic circuit 16 to the output terminal 17.

The A/D converters 14 and 15 receive A from the reference voltage source 18.
/ Reference voltage (-2V) that sets the full scale of D conversion
) is supplied. The signals from the inverting amplifier circuit 14 and the non-inverting amplifier circuit 13 are added together and supplied to the + side input of the differential amplifier circuit 21, and the reference voltage from the reference voltage source 18 is supplied to one side input of the differential amplifier circuit 21. is supplied, and after amplifying the difference between the two inputs and attenuating the high-frequency components, it is added to the DC voltage from the DC level adjuster 19 and supplied to one side of the input of the non-inverting amplifier circuit 13. . DC level adjuster 19
is used as a coarse adjustment.

The valid input range of A/D converter 14.15 is 0 to -2
v, the waveforms of the input signals a and b of the A/D converter 15°14 will be the waveforms shown in the second figure 1, (bl. Generally, the pedestal of the video signal shown in the second figure ta) is clamped to a constant voltage. The arithmetic circuit 16 inverts the signal from the A/D converter 15, adds it to the signal from the A/D converter 14, and outputs the result to the output terminal 17. In addition, in the A/D converters 14 and 15, when the input signal a exceeds the range of 0 to -2v, the output data becomes OO...0, 11...
Limited to 1.

In addition, A/D converters 14 and 15, and an arithmetic circuit 16
is supplied with a clock from a clock pulse input terminal 20. In addition, since the output signal of the differential amplifier circuit 21 is used to compensate for slow direct current fluctuations (like the video signal), the output signal of the differential amplifier circuit 21 is a signal with the high frequency attenuated. .

Amplification circuits that handle high-band signals such as Eirin signals tend to be accompanied by DC drift, but in this embodiment, the DC component is compensated for by the differential amplifier circuit 21 for low frequencies. In the differential amplifier circuit 21 for low frequencies, one with less DC drift can be easily obtained.

The two A/D converters 14 and 15 are connected to two amplifier circuits 13 for inputting video signals having different polarities and DC components.
．． It is supplied from 12 and used. A/D converter 14,
15 DC level difference between A/D converter 1
4 and the effective range of the A/D converter 15. each A
/D converter 14, 1.5 input signals are added to form video signal a.

Since the polarity of b is reversed, there is only a DC component.

The difference between this DC component and the reference voltage from the reference voltage source 18 is amplified and fed back to the amplifier circuit 13 to stabilize the DC level of the input signal to the A/D converter 14. The digital data from the two A/D converters 14 and 1.5 are combined in the arithmetic circuit 16 and output to each A/D converter.
Digital data with one bit more than the number of quantization bits of the D converters 14 and 15 is output.

(Effects of the Invention) The A/D conversion circuit of the present invention has the effect of improving the linearity of the output digital signal by providing feedback as described above.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention.
, tb+ are waveform diagrams of signals a and b shown in Figure 1, Figure 3 is a block diagram of a conventional A/D conversion circuit, and Figure 4 is a block diagram of a conventional A/D conversion circuit.
Figures fat and (bl are the signals a' shown in Figure 3, respectively)
. It is a waveform diagram of b'. 1.11...Input terminal, 2,3.12...
...Inverting amplifier circuit, 13...Non-inverting amplifier circuit,
4, 5.14゜15... A/D converter, 6.16... Arithmetic circuit, 7.17...
・Output terminal, 8.18...Reference voltage source, 9.1
9...DC level adjuster, 10,20...
...Clock pulse input terminal. Agent Patent Attorney Susumu Uchihara ゛2'111' ITfJ (KU) (#/) Figure 2 (^) (b) Age 4-
times

Claims (1)

[Claims] First and second amplifier circuits that input analog signals and output them at different DC levels, and first and second A/D converters that receive outputs from the first and second amplifier circuits, respectively. and a signal obtained by mixing the outputs of the first and second amplifier circuits, and a reference voltage that sets the full scale of the first and second A/D converters, and the first amplifier circuit receives the analog signal. a differential amplifier circuit that outputs a DC component to be mixed with the first and second A;
An A/D conversion circuit comprising: an arithmetic circuit that synthesizes and outputs digital signals from an A/D converter.