JP2534069B2 - Variable output amplitude type binary transversal filter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a filter circuit that directly limits a band of a digital wireless communication device to a baseband signal, and controls a transmission output of the wireless communication device. It is related to the method.

(Prior Art) Conventionally, in a binary transversal type filter as shown in FIG. 3, the output amplitude cannot be controlled by the circuit inside the filter, and the variable gain type amplifier circuit is connected in cascade to the output. Or, an attenuator was added. Below is the third
A case where the variable gain type amplifier circuit shown in the figure is provided will be described.

A binary signal is input from the input terminal 1 and applied to the time expansion circuit 3. The time expansion circuit 3 is composed of a delay circuit array in which the same delay circuit group as the delay circuit 2 is connected in cascade, and the delay time of each delay circuit is a time quantization interval of time expansion (hereinafter referred to as a sampling frequency). , It depends on the target attenuation characteristics of the binary transversal filter. Normally, a sufficiently small sampling interval is selected for the input binary signal. However, especially when aiming for precise roll-off type Nyquist shaping, at a rate that is an integer multiple of the bit rate of the input binary signal. Perform sampling. In this case,
The delay circuit 2 is often composed of a flip-flop type delay element which operates by an external clock signal.

The output of the time expansion circuit 3 is connected to the input of the buffer circuit group 5, and the time expanded input signal is a binary voltage supply to the input of the next time expansion coefficient conversion circuit 7 in the buffer circuit group 5. It appears at the output of each buffer circuit 4 as a source.

In the time expansion coefficient conversion circuit 7, current control type coefficient conversion is performed for each input with respect to the low impedance input of the following sum circuit 8.

The example shown in FIG. 3 has the simplest structure in which the value itself of each series resistor 6 is proportional to the conversion coefficient string in order to limit the current. The summing circuit 8 synthesizes the currents from the respective outputs corresponding to the converted time expansion coefficient. As described above, the summing circuit 8 of the conventional example is a low impedance current synthesizing circuit, and the voltage follower circuit shown in FIG. 3 that utilizes the inverting input of an operational amplifier or the like is often used.

The output of the summing circuit 8 appears at the output terminal in the form of replacing the current combined value with the voltage amplitude. The amplitude waveform at this point is
The target waveform of this filter is an approximate waveform quantized at the sampling interval described above. Therefore, the output of the summing circuit 8 contains spurious waves that are integral multiples of the sampling frequency, and if these spurious waves are immediately input to a wireless modulator or the like, harmful spurious emission will occur.
In this sense, the output of this filter is connected to the spurious eliminating filter 9 as shown in FIG.

What has been described above is the operation of a general binary transversal filter, but as can be easily understood, it is extremely difficult to control its output amplitude only by the internal circuit of the binary transversal filter.

Therefore, in FIG. 3, in order to control the output amplitude,
An amplitude controlling variable gain amplifying circuit 10 independent of the filter is added so that a required amplitude can be supplied to a modulator such as a radio device.

(Problems to be Solved by the Invention) However, in the case of the conventional configuration shown in FIG.
Since the amplifier circuit and the variable gain amplifier circuit 10 are connected in cascade, it is necessary to pay attention to the stability of the output, especially the offset fluctuation of the output signal. In addition, the circuit scale is large, and even when adjustments are made, operations are complicated, and there are many points to be reviewed from the aspects of reliability and economy.

(Means for Solving Problems) In order to solve the above-mentioned drawbacks of the conventional example, the present invention provides a time expansion circuit including a delay circuit array and a buffer circuit group connected to each expansion output of the time expansion circuit. In the binary transversal filter including a time expansion coefficient conversion circuit connected to each output of the buffer circuit group, a sum circuit for synthesizing the output of the coefficient conversion circuit, and a spurious removal filter, the buffer circuit group is A CMOS circuit having a complementary driver structure,
It is a binary transversal filter provided with an amplitude control circuit for supplying a common variable voltage to the power supply input of each CMOS circuit as amplitude control. An embodiment of the present invention in which the CMOS circuit is configured as a buffer circuit will be described below.

(Example) An example is shown in FIG. A binary signal is input from the input No. 41 and the operation of the time expansion circuit 3 constituted by the delay circuit array is the same as that of the conventional example of FIG. In the present invention, the output of the time expansion circuit 3 is connected to a buffer circuit group 5 having a CMOS structure, and the power supply terminal of the buffer circuit group 5 has a common applied voltage which is independent of the power supply lines of other circuits. An amplitude control circuit 10 'capable of supplying a variable voltage is connected.
The reason why the power supply voltage is controlled to be referred to as an amplitude control circuit here is as follows. That is, in a CMOS structure element such as the buffer circuit 4 ′, as shown in FIG. 2, the gates and drains of the P-channel MOS FET and the N-channel MOS FET are connected in common, and the sources of each are connected to the positive power source and ground. One of the MOS FETs turns on and the other turns off depending on the state of the common gate input. ON MOS FE
The internal resistance of T is about 10 ³ Ω, but it is a MOS FET that turns OFF.
The internal resistance of is considered to be about 10 ¹⁰ Ω. Therefore, its output amplitude has a property of being almost linearly dependent on the power supply voltage applied to the element within an allowable load range. The operation of this circuit 4 is shown in Table 1.

In fact, in a commercially available CMOS gate IC or the like, it is said that there is no problem even if it is considered that the H output is equal to the applied power supply voltage and the L output is equal to the ground level when operated with a single-pole power supply. Due to this property, each output terminal of the buffer circuit group 5 in FIG.
An H-level voltage proportional to the power supply voltage appears, and each buffer circuit functions as a voltage variable binary voltage supply source by the applied voltage. On the other hand, in the sum circuit 8 via the time expansion coefficient conversion circuit 7 after the buffer circuit group 5, as described in the conventional example,
Since the output of each buffer circuit 4'is linearly summed, the output amplitude of the sum circuit 8 is proportional to the output amplitude of the buffer circuit 4 '. The output amplitude of the transversal filter can be controlled. Next, the amplitude control circuit 1 in FIG.
It will be described that the divided voltage output in 0'is connected to the non-inverting input in the summing circuit 8.

In FIG. 1, the buffer circuit 4'having a CMOS structure is assumed to use a normal CMOS gate IC with a single-pole power supply. That is, the binary output voltage of the buffer circuit 4'is zero or H level. Therefore, if the non-inverted input in the summing circuit 8 is dropped to the ground as shown in FIG. 3, the output signal thereof causes an offset on the minus side. Even if this is canceled by using a non-inverting input in the summing circuit 8 by making a reference voltage from a normal power supply system, the amplitude control method that operates only the H level of the buffer circuit output as described above will reduce the amplitude. As a result, the offset changes every time it is changed. Therefore, the reference voltage is created by the buffer circuit power supply voltage that is proportional to the amplitude change. That is, the correlation of output amplitude ∝ output signal offset ∝ buffer circuit power supply voltage was used. As a result, amplitude control can be easily realized without fluctuations in output offset.

(Effects of the Invention) As described above, according to the present invention, the amplitude variable circuit continuously connected to the filter for controlling the output amplitude is not required, and conventionally, the ATT or the gain variable amplifier that operates in a wide band is used. Where a relatively delicate circuit is required, it has been greatly rationalized, and the output amplitude can be changed by a very simple voltage change operation. Also, because of the property of being realized by the variable voltage operation, connection with an external control circuit becomes easy. For example, this is a circuit that applies ALC to the transmission output of a phase-amplitude modulation type wireless device. In addition, in the phase-amplitude modulation type modulation method, even for baseband 2-series input that uses quadrature carrier or multi-valued 2-series input such as 16QAM, the filters of the 2-series circuits are included. If the output amplitude of the buffer circuit is controlled with the same voltage, amplitude control of two series can be realized simultaneously, and the application range is wide.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of a CMOS type buffer circuit used in the present invention, and FIG. 3 is a conventional example. 3 ... Time expansion circuit, 4 '... Complementary buffer circuit, 5 ... Buffer circuit group, 7 ... Time expansion coefficient conversion circuit, 8 ... Sum circuit, 10'
...... Amplitude control circuit.

Claims (2)

(57) [Claims] 1. A time expansion circuit including a delay circuit array, a buffer circuit group connected to each expanded output of the time expansion circuit, a time expansion coefficient conversion circuit connected to each output of the buffer circuit group, and the coefficient. In a binary transversal filter including a sum circuit for synthesizing conversion circuit outputs and a spurious elimination filter, the buffer circuit group has a complementary driver structure.
An output amplitude variable type binary transversal filter comprising a CMOS circuit and an amplitude control circuit for supplying a common variable voltage to the power supply input of each CMOS circuit as amplitude control. 2. A means for dividing the output of the amplitude control circuit by resistance to obtain a reference voltage proportional to the output of the amplitude control circuit and supplying the reference voltage to the summing circuit as a differential input.
2. The output amplitude according to claim 1, wherein the offset generated in the output signal of the summing circuit when the CMOS circuit is operated by a single-pole power source is offset while interlocking with the amplitude control of the buffer circuit group. Variable binary transversal filter.