JPS61122726A - Control circuit of reactive power compensator - Google Patents

Abstract

PURPOSE:To control highly accurately a reactive power compensator by executing the operation of primary delay processing and reset filter processing by an operating means based upon software. CONSTITUTION:The voltage of a power system 1 is detected by a voltage detecting circuit 5 and a signal obtained through a delay circuit 7 having a delay element of which time constant is variable and a signal outputted from the detecting circuit 5 are inputted to a voltage control circuit 9. A thyristor ignition phase control circuit 11 determines the control variable of a thyristor device 3 in accordance with the output of the circuit 9. A current detecting circuit 13 detects the current of the device 3 and determines the time constant of the delay circuit 7. The operation for the primary delay processing of the delay circuit 7 is executed by the operating means based upon the software.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a control circuit for a static type non-active power compensator. There was one shown in Figure 7. In the figure, 1 is a power system, 2 is a reactor, 3 is a thyristor device consisting of an antiparallel circuit of Nyristors, 4 is a capacitor, 5 is a voltage detection circuit, and 6
is a summing point, 7 is a first-order delay circuit, 8 is a summing point, 9 is a voltage control circuit, 10 is a summing point, l'l is a thyristor firing phase control circuit, 12 is a □ current transformer, 13 is a current detection circuit ,1
4 is a summing point, 15 is an integrating circuit, 16 is a negative polarity cardiopulmonary circuit,
17 is reactor 2, thyristor device 3, capacitor 4
This is a static type reactive power compensator consisting of.

Next, the operation will be explained. The reactive power compensator 17 always connects the capacitor 4 to the power system 1 and compensates for the difference between the capacitor 4 and the reactor 2 by connecting it in parallel with the capacitor 4 or by continuously controlling the admittance of the accelerator 2 with the thyristor device 3. The composite reactive power Qo is configured to be continuously adjustable from a phase leading region to a phase lag region.

As a control method for this reactive power compensator 170, the effective value of the voltage of the power system is detected by the voltage detection circuit 5, and the first voltage deviation ΔV! between the detected value and the voltage reference value Vref is determined.
7 First voltage deviation signal Δvl obtained at addition point 6
is input to the addition point 8 and also to the first-order lag circuit 7. At addition point 8, the above-mentioned first voltage deviation Δv
1 and the output of the first-order lag circuit 7 to obtain a second voltage deviation ΔV2. This second voltage deviation Δv2 is input to the voltage control circuit 9 at the next stage. This voltage control circuit 9 is usually composed of a first-order delay element, and is 1+T8
(where T is a time constant and K is a gain constant). The output of the voltage control circuit 9 passes through the addition point 10, and
The signal is input to the thyristor firing phase control circuit 11. The thyristor firing phase control circuit 11 controls the thyristor firing phase corresponding to Qo so that the reactive power compensator 17 can output an appropriate reactive power Qot according to the input signal level.
An operation is performed to give a thyristor firing signal to the thyristor device 3. By using such a control circuit, when the voltage of the power system 1 drops below the voltage reference value vref, the reactive power compensator [17 outputs phase-advanced reactive power as Qo,
It acts to raise the voltage of the power system 1, and conversely, when the voltage of the power system 1 rises above the voltage reference value Vref, the reactive power compensator 17 outputs lagging reactive power as Qo, and the voltage of the power system 1 increases. By acting to lower the voltage, the voltage of the power system 1 can be kept constant, and
In the reactive power compensator, when the power system voltage is steadily lower than vref, when the reactive power compensator 17 is operated to raise the voltage in response, the characteristics of the reactive power compensator 17 are reduced. This means that most of the compensation capacity is used for steady voltage drops, and even if a new voltage change occurs in this state,
There is a problem that it is no longer possible to respond to such changes and make full use of the functions of the reactive power compensator.
A first-order delay circuit 7 is added to the control circuit, and the first voltage deviation Δ
V! For the steady change of Δvl and 1 at addition point 8
The output of the next delay circuit 7 is canceled out so that the control circuit does not respond to steady changes in Δv1. For example, when Δvl changes stepwise, Δv2 follows only the initial change in Δv1, and then gradually converges to zero.

On the other hand, when the voltage of the power system 1 rises, the control circuit controls the output Qo of the reactive power compensator to the lagging side to suppress the voltage rise, but in this case, the capacitor 4
Since it is necessary to flow reactive power Qt which is greater than the phase advanced reactive power Qc of There is a problem in that it is uneconomical because it requires equipment. Therefore, from an economic standpoint, the reactor 2 and thyristor device 3 should have a short-time overload rating, and a relatively small continuous-rated device can handle lagging reactive power several times the continuous rating for a short period of time. It is desirable to control. In a reactive power compensator having such a short-time overload rating, it is necessary to add a constant current control circuit to the control circuit to operate the reactor 2 and thyristor device 3 within an allowable overload.

This constant current control circuit detects the current IR flowing through the thyristor device 3 using the current transformer 12, and the current detection circuit 13
, it is converted into a DC signal corresponding to its effective value.

When IR becomes larger than the current setting value Iref, the deviation signal Δ is calculated at the adding point 14 and input to the integrating circuit 15. The result of integration in the integrating circuit 15 is input to the negative polarity blocking circuit 16. The negative polarity blocking circuit 16 allows the input signal to pass only when the input signal is of positive polarity, and blocks the signal when the input signal is of negative polarity, but this only occurs when the current 11 of the thyristor device 3 is larger than Iref. This is to operate the constant current control circuit. The output of the negative polarity blocking circuit 16 is input to the summing point 10, and as a current feedback signal, as shown in FIG.
1 within Iref to prevent overload of the thyristor device 3.

[Problem that the invention seeks to solve]

The control circuit of a conventional reactive power compensator is configured as described above, so when digital control is performed based on software, processing is performed based on the algorithm of the conventional control circuit, so digital calculation processing is not required. It was difficult to improve accuracy.

That is, the block diagram of the first-order lag calculation in FIG. 7 can be shown as shown in FIG. 9, and the transfer function y in this conventional first-order lag calculation is expressed as follows. By transforming this equation (1), we obtain the general term yn
From equation (1), (1+TS) y = Kx yn-)/n-1 is obtained, and when Sy is replaced with T, it becomes. However, T is a time constant and ΔT is a sampling time.

Therefore, as can be understood from equation (2), conventionally, when performing arithmetic processing of 16-bit data, if the ratio of T: ΔT becomes large, even if T and ΔT are changed, Since there is no change within a bit and the error is treated as a truncation error, the error in the equation as a whole increases, and as a result, it has become difficult to perform high-precision control. Also, in the case of reset filter processing, this was done to eliminate the block diagram as shown in Figure 10. This invention provides a control circuit for a reactive power compensator that realizes all new algorithms for the control circuit and enables highly accurate control of the control circuit.

[Failure to solve the problem]

The control circuit of the reactive power compensator of the present invention includes a voltage detection circuit that detects the voltage of the power system, a delay circuit that inputs the output of the voltage detection circuit and has a delay element with a variable time constant, and an output of the voltage detection circuit. A voltage control circuit composed of a first-order delay circuit that inputs this output through a delay circuit, a thyristor firing phase control circuit that determines the control amount of the thyristor/device according to the output of the voltage control circuit, and a current control circuit of the thyristor device. The current detection circuit detects the current value and determines the time constant of the delay circuit based on this current value, and further includes calculation means for calculating the first-order delay processing of the voltage control circuit and the reset filter processing of the delay circuit. It is something.

[Effect]

In the present invention, the first-order delay processing and reset filter processing in the voltage control circuit are performed by calculation means using shadow calculation processing that does not cause errors, and as a result, highly accurate control of the control circuit is made possible.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, an example in which the present invention is applied to first-order delay processing will be explained.

FIG. 1 shows the calculation means 20, and in FIG.
21 is the first-order lag gain K input from the reset filter.
22.31 is a bit shift processing circuit that performs 16-bit processing, and 23 is an overflow processing circuit that performs all overflow processing. 24
Is it the previous first-order delayed output? - Previous-next-delayed output circuit that temporarily holds and outputs; 25 is a subtractor that subtracts all the previous-next-delayed output from the current-next-delayed output that is input this time; 26 is a subtracter that obtains the current integral input; The previous integral value output circuit 27 holds and outputs the previous integral value, and 27 is an adder that adds the previous integral input from the current integral input.

28 is an integral gain mantissa setting device that multiplies the added value added by the adder 27 by the current integral mantissa, 29 is a previous calculated value output circuit that temporarily holds and outputs the previous first-order lag calculated value, and 30 is an integral This is an adder that adds the previous-next delayed calculation value to the output of the gain mantissa setter 28. Further, the proportional gain exponent setter 21, the bit shift processing circuit 22, the integral gain mantissa setter 28, the adder 30, the previously calculated value output circuit 29, and the bit shift processing circuit 31 are each configured to perform double word processing. The result of this calculation is output from the bit shift processing circuit 31 to the voltage control circuit. Note that each device has a 16-bit processing configuration.

In addition, the block diagram of the first-order delay calculation shown in Fig. 2 is
It can be shown as shown in the figure. The transfer function y in this case is.

y = −x・・・・・・(3)S, and when we transform this to find the general term yn, we get (1
), the term xn-xn-t is sent to the integral gain mantissa setter 28 in FIG. 1, the term xn-xn-t is sent to the previous integral value output circuit 26 in FIG. corresponds to each.

Next, the operation of this embodiment will be explained.

In this embodiment, the -th order delay process is program controlled according to the flowchart shown in FIG.

That is, when the first-order lag processing input expressed in 16 bits is input from the reset filter to the -order lag circuit, -
A determination is made as to whether or not to use the next-order lag calculation, and if it is used, it is multiplied by the first-order lag gain K in the proportional gain index setter 21 of FIG. 1, and the result is displayed in 16 bits. If it is not used, it is returned to the voltage control circuit as it is, and the -next lag calculation is not performed. Next, in the bit shift circuit 22, the multiplication result of the proportional gain exponent setter 21 is converted into word data by bit-shifting by the gain exponent, and if there is a digit error, overflow processing is performed. The subtracter 25 subtracts the 16-bit data and the previous-next delayed output to obtain the current integral input. Furthermore, the adder 27
In , the current integral input and the previous integral input are added,
This added value is multiplied by the current integral mantissa in the integral gain mantissa setter 28, and the previous-next delayed calculation value is added in the adder 30. Finally, this addition result is converted into 16-bit data by the bit shift processing circuit 31, and the integral conservation term (double word) is converted into bits using the current and previous integral gain exponents. The integral conservation term and first-order lag calculation output are calculated using the integral gain.

By the way, when performing the above processing, the proportional gain exponent setter 21 and the bit shift processing circuit 22 perform the following steps.
Since the product of 16 bits is processed using a 16-bit floating point number, no error occurs, and the next subtracter 25 also performs subtraction of 16 bits, so no error occurs in the integral input this time. do not have. Therefore, the integral input is subsequently processed based on equation (4) without error.

In equation (4), since it corresponds to the integral gain mantissa setter 28, no error occurs even if 16-bit display is performed after 16-bit floating point processing.

Similarly, XQ+ x corresponding to the previous integral value output circuit 26
(1-1 and Y corresponding to the previous calculation value output circuit 29
Since 16-bit addition is also performed for n-1, no error occurs. Therefore, no error occurs in the first-order lag processing circuit of this embodiment.

When 16-bit display data is input manually as in this example, the relationship T>ΔT occurs, and as the difference between T and ΔT increases, □ converges to 1. Therefore, as the ratio of T:ΔT increases, the error within 16 bits is treated as a truncation error, and the overall error tends to increase.

As described above, in this embodiment, since the -th order delay processing is performed using the processing concept (algorithm) based on FIG. 5, it is possible to perform highly accurate control without generating processing errors.

Next, another embodiment in which the present invention is applied to filter processing will be described. Note that the same parts as in the previous embodiment are given the same reference numerals, and redundant explanation will be omitted.

In this embodiment, the calculating means 32 is configured as shown in FIG. 4, and subtracts the previous reset filter internal output value from the input data input as voltage deviation to the subtracter 25, and the result of this subtraction is The reset filter output value is output from the output terminal OUT. The previous reset filter internal integration output value is processed in the same way as in the previous embodiment. In addition, the block diagram in this case is shown in Figure 5,
This operation is processed based on the flowchart shown in FIG. 6, and similarly to the above embodiment, the reset filter processing can be controlled with high precision.

〔Effect of the invention〕

As described above, according to the present invention, control is performed based on an algorithm that does not cause errors by means of arithmetic means that process -order delay processing and reset filter processing in two arithmetic forms with the same number of bits. , has the effect of providing high-precision control.

[Brief explanation of drawings]

1 to 3 show an embodiment of the control circuit of the reactive power compensator according to the present invention, FIG. 1 is a schematic configuration diagram of the calculation means that performs the first-order delay processing, and FIG. 2 is the block diagram thereof. 3 is a flowchart showing the first-order delay processing, FIGS. 4 to 46 show other embodiments of the present invention, FIG. The figure is a block diagram, Figure 6 is a flowchart showing the reset filter processing, and Figure 7 is a flowchart showing the reset filter processing.
Figures 1 to 10 show the control circuit of a conventional reactive power compensator, Figure 7 is its circuit diagram, Figure 8 is a characteristic diagram showing current reduction characteristics by a first-order lag circuit, and Figures 9 and 10 are first-order lag circuits. FIG. 3 is a block diagram showing delay processing and reset filter processing, respectively. In the figure, 5 is a voltage detection circuit, 7 is a delay circuit, 9 is a voltage control circuit, 11 is a thyristor firing phase control circuit, 13
is a partial current detection circuit, 17 is a reactive power compensator, 20.32
is the calculation means.

Claims (1)

[Claims] A circuit that maintains the voltage of the power system constant by controlling a reactive power compensator consisting of a series connection of a reactor and a thyristor device connected to the power system and a capacitor connected in parallel to this, the circuit controlling the voltage of the power system at a constant level. a voltage detection circuit that detects the voltage of the grid; a delay circuit that inputs the output of this voltage detection circuit and has a delay element with a variable time constant; and a first-order lag that inputs the output of the voltage detection circuit and this output through the delay circuit. a voltage control circuit configured by a circuit; a thyristor firing phase control circuit that determines the control amount of the thyristor device according to the output of the voltage control circuit; a current detection circuit that determines a time constant of a delay circuit; and a control circuit for a reactive power compensation circuit, comprising a calculation means for calculating first-order delay processing in the voltage control circuit and reset filter processing in the delay circuit. A control circuit for a reactive power compensator, characterized in that: