JPS61121771A - Abnormal output voltage preventing circuit of dc/dc converter - Google Patents
Abnormal output voltage preventing circuit of dc/dc converterInfo
- Publication number
- JPS61121771A JPS61121771A JP23880184A JP23880184A JPS61121771A JP S61121771 A JPS61121771 A JP S61121771A JP 23880184 A JP23880184 A JP 23880184A JP 23880184 A JP23880184 A JP 23880184A JP S61121771 A JPS61121771 A JP S61121771A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- converter
- transistor
- terminal
- abnormal output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はＤＣ−Ｄｏコンバータの出力電圧異常防止回路
拡間し、詳しくは、ＤＣ−ＤＯコ／バータの入力電圧が
低いとき及び高いときにＤＣ−ＤＣコンバータの発振を
止め、入力電圧が正常な電圧のときＫ ＤＣ−ＤＣコン
バータを働かせることによ）、ＤＣ−ＤＣコンバータの
出力電圧が異常な電圧とならないようＫする異常電圧発
生防止回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention expands the output voltage abnormality prevention circuit of a DC-Do converter. This circuit relates to an abnormal voltage generation prevention circuit that prevents the output voltage of the DC-DC converter from becoming an abnormal voltage by stopping the oscillation of the DC converter and operating the DC-DC converter when the input voltage is a normal voltage. It is.
従来の技術
従来、ＤＣ−ＤＣコンバータは電圧の安定化能力はな−
ので、ＤＣ−ＤＣコンバータの前段に電圧の安定化回路
（レギュレータ）を付けるのが普通である。Conventional technology Conventionally, DC-DC converters have no ability to stabilize voltage.
Therefore, it is common to install a voltage stabilizing circuit (regulator) before the DC-DC converter.
ここで、このレギュレータが何らかの原因で故障して、
ＤＣ−ＤＣコンバータに低電圧あるいは高電圧が加えら
れた場合には、ＤＣ−ＤＣコンバータの二次出力には入
力に比例した電圧が出力されてしまう。Here, this regulator malfunctions for some reason,
When a low voltage or a high voltage is applied to the DC-DC converter, a voltage proportional to the input is outputted to the secondary output of the DC-DC converter.
発明が解決しようとする問題点
そして、ＤＣ−ＤＣコンバータに加えられる電圧が、低
電圧である場合には二次負荷が誤動作をするし、また高
電圧である場合にはＤＣ−ＤＣコンバータのパワートラ
ンジスタを破壊したり、二次負荷回路を破壊するという
欠点があった。Problems to be Solved by the Invention If the voltage applied to the DC-DC converter is low, the secondary load will malfunction, and if the voltage applied to the DC-DC converter is high, the power of the DC-DC converter will be affected. It had the disadvantage of destroying transistors and secondary load circuits.
本発明はこれらの欠点を解決するためになされたもので
あり、従って本発明の目的は、ＤＣ−ＤＣコンバータの
入力電圧が適当な電圧となったときにのみＤＣ−ＤＣコ
ンバータを働かせ、ＤＣ−ＤＣコンバータの入力電圧が
低電圧及び高電圧のときにはＤＣ−ＤＣコンバータの発
振を止めることによって、ＤＣ−ＤＣコンバータの出力
に異常な電圧が発生しないようにした新規な出力電圧異
常防止回路を提供することにある。The present invention has been made to solve these drawbacks, and therefore, an object of the present invention is to operate the DC-DC converter only when the input voltage of the DC-DC converter becomes an appropriate voltage, and to convert the DC-DC converter into a suitable voltage. To provide a novel output voltage abnormality prevention circuit that prevents abnormal voltage from occurring at the output of a DC-DC converter by stopping oscillation of the DC-DC converter when the input voltage of the DC converter is low voltage or high voltage. There is a particular thing.
問題点を解決するための手段
上記目的を達成する為に、本発明に係るＤＣ−ＤＣコン
バータの出力電圧異常防止回路は、ＤＣ−ＤＣコンバー
タの発振を制御する第１のトランジスタと、この第１の
トランジスタのベースに接続され低電圧時及び高電圧時
にこの第１のトランジスタを１ＯＦＦ ”するように働
く２本のツェナーダイオード及び第２のトランジスタと
を具備して構成される。Means for Solving the Problems In order to achieve the above object, an output voltage abnormality prevention circuit for a DC-DC converter according to the present invention includes a first transistor for controlling oscillation of the DC-DC converter, and a first transistor for controlling oscillation of the DC-DC converter. The first transistor is connected to the base of the second transistor and has two Zener diodes and a second transistor that turn off the first transistor when the voltage is low and when the voltage is high.
発明の実施例
次に本発明をその好ましい実施例について図面を参照し
ながら具体的に説明する。Embodiments of the Invention Next, preferred embodiments of the present invention will be specifically described with reference to the drawings.
第１図は本発明に係る出力電圧異常防止回路を含むＤＣ
−ＤＣコンバータの全体の構成を示すブロック図である
。図において、参照番号１，２は非安定化覗圧の入力端
子、３は発振器用電圧の入力ｉ子、４ｉｄレギュレータ
、５ばＤＣ−ＤＣコンバータ、６は発振器、７は本発明
に係る出力電圧異常防止回路、８，９は出力端子、１０
は電圧の供給を制御する入力端子、１１は電圧検出用端
子、１２は電圧の供給を制御された出力端子、１３はグ
ランド用端子である。FIG. 1 shows a DC voltage control circuit including an output voltage abnormality prevention circuit according to the present invention.
- It is a block diagram showing the whole structure of a DC converter. In the figure, reference numbers 1 and 2 are input terminals for unregulated peeking pressure, 3 is an oscillator voltage input terminal, 4 is an ID regulator, 5 is a DC-DC converter, 6 is an oscillator, and 7 is an output voltage according to the present invention. Abnormality prevention circuit, 8 and 9 are output terminals, 10
11 is an input terminal for controlling voltage supply, 11 is a voltage detection terminal, 12 is an output terminal whose voltage supply is controlled, and 13 is a ground terminal.
第１図の回路動作を説明すると、レギュレータ付きのＤ
Ｃ−ＤＯコンバータにおいて、何らかの原因でレギュレ
ータ４が故障してＲ２の電圧が通常よりも低くあるいは
高くなったときに、出力電圧異常防止回路７が動作して
発振器６への電圧供給を断つことによ９発振器６が発振
を停止し、ＤＣ−ＤＣコンバータ５が働かなくなり出力
電圧も出力されなくなる。To explain the circuit operation in Figure 1, the D
In the C-DO converter, when the regulator 4 fails for some reason and the voltage of R2 becomes lower or higher than normal, the output voltage abnormality prevention circuit 7 operates to cut off the voltage supply to the oscillator 6. 9. The oscillator 6 stops oscillating, the DC-DC converter 5 stops working, and no output voltage is output.
第２図は本発明に係る出力電圧異常防止回路の第１の実
施例を示す回路構成図であって、Ｑｌ、Ｑ２はトランジ
スタ、Ｄｌはダイオード、Ｄ２． Ｄ３は定電圧ダイオ
ード、Ｒ１，Ｒ２，Ｒ３，Ｒ４は抵抗である。FIG. 2 is a circuit configuration diagram showing a first embodiment of the output voltage abnormality prevention circuit according to the present invention, in which Ql and Q2 are transistors, Dl is a diode, D2. D3 is a constant voltage diode, and R1, R2, R3, and R4 are resistors.
第２図に示した回路の動作説明をするに、電圧検出用端
子１１が定電圧ダイオードＤ３のツェナ電圧とトランジ
スタＱ２のベースエミッタ順方向電圧降下（約０．７Ｖ
）を加えた電圧よりもわずかに高くなると、トランジス
タＱ２は導通状態となり、それによってトランジスタＱ
１も導通状態となる。そうして、端子１０の電圧は端子
１２に供給されることになる。電圧検出用端子１１の電
圧がさらに高くなって定電圧ダイオードＤ２のツ二す電
圧を越えると、トランジスタＱ１のベース電位が高くな
ってトランジスタＱ１は非導通となり、端子１０の電圧
は端子１２に供給されなくなる。To explain the operation of the circuit shown in FIG. 2, the voltage detection terminal 11 is connected to the Zener voltage of the constant voltage diode D3 and the base-emitter forward voltage drop of the transistor Q2 (approximately 0.7 V).
), transistor Q2 becomes conductive, thereby causing transistor Q
1 also becomes conductive. The voltage at terminal 10 will then be supplied to terminal 12. When the voltage at the voltage detection terminal 11 becomes higher and exceeds the voltage across the constant voltage diode D2, the base potential of the transistor Q1 becomes higher, the transistor Q1 becomes non-conductive, and the voltage at the terminal 10 is supplied to the terminal 12. It will no longer be done.
このように、本発明の出力電圧異常防止回路は端子１１
の電圧を検出して端子１０と端子１２０間を０Ｎ１０Ｆ
Ｆ制御することができる。これを第１図の回路に応用す
ればＲ２の電圧の異常を検出してＤＣ−ＤＣコンバータ
５の発振を止め、出力に異常電圧を発生することを防せ
ぐことかできる。In this way, the output voltage abnormality prevention circuit of the present invention has the terminal 11
Detects the voltage of 0N10F between terminal 10 and terminal 120.
F control is possible. If this is applied to the circuit shown in FIG. 1, it is possible to detect an abnormality in the voltage of R2, stop the oscillation of the DC-DC converter 5, and prevent abnormal voltage from being generated at the output.
第３図は本発明の第２の実施例を示す回路構成図であり
、第２図の０Ｎ１０ＦＦ トランジスタＱ１をＰＮＰ型
からＮＰＮ型に置き換えた回路であり、第２図と同様に
、トランジスタＱ３は、定電圧ダイオードＤ４のツェナ
電圧で°ＯＮ”となり、定電圧ダイオードＤ５のツェナ
電圧とトランジスタＱ４のベースエミッタ順方向電圧降
下を加えた電圧で”ＯＦＦ”となる。FIG. 3 is a circuit configuration diagram showing a second embodiment of the present invention, in which the 0N10FF transistor Q1 in FIG. 2 is replaced from the PNP type to the NPN type, and similarly to FIG. 2, the transistor Q3 is , it is turned ON by the Zener voltage of the constant voltage diode D4, and turned OFF by the sum of the Zener voltage of the constant voltage diode D5 and the base-emitter forward voltage drop of the transistor Q4.
発明によって生じる効果
以上説明したように、本発明に係る回路は、ある入力電
圧を検出し、それによって働く回路（ＤｔＥ−ＤＣコン
バータ、定格電圧を越えるとこわれやすい回路、定格電
圧を越えると誤動しやすい回路）の部品故障や誤動作を
防止するという利点がある。Effects produced by the invention As explained above, the circuit according to the present invention detects a certain input voltage and operates according to the input voltage (DtE-DC converter, a circuit that is easily damaged when the rated voltage is exceeded, and a circuit that malfunctions when the rated voltage is exceeded). This has the advantage of preventing component failures and malfunctions in circuits that are prone to damage.
【図面の簡単な説明】
第１図は本発明を含むＤＣ−ＤＣコンバータの全体を示
すブロック図、第２図は本発明による第１の実施例を示
す回路構成図、第３図は本発明による第２の実施例を示
す回路構成図である。
１．２．３・・・入力端子、４・・・レギュレータ、５
、、、 ＤＣ−ＤＣコンバータ、６・・・発振器、７・
・・本発明の回路、８．９・・・出力端子、１０．１２
・・・電圧の０Ｎ１０ＦＦ入出力端子、１１・・・電圧
検出端子、１３・・グランド端子、Ｑｌ、 Ｑ２． Ｑ
３． Ｑ４・・・トランジスタ、Ｄｌ・・・ダイオード
、Ｄ２． Ｄ３． Ｄ４． Ｄ５・・・定電圧ダイオー
ド、Ｒ１，Ｒ２，Ｒ３，Ｒ４，Ｒ５，Ｒ６，Ｒ７゜Ｒ８
・・・抵抗
特許出願人 日本電気株式会社
代 理 人 弁理士 熊谷雄太部
第３図[Brief Description of the Drawings] Fig. 1 is a block diagram showing the entire DC-DC converter including the present invention, Fig. 2 is a circuit configuration diagram showing a first embodiment according to the present invention, and Fig. 3 is a block diagram showing the entire DC-DC converter including the present invention. FIG. 2 is a circuit configuration diagram showing a second embodiment of the invention. 1.2.3...Input terminal, 4...Regulator, 5
,,, DC-DC converter, 6... oscillator, 7.
...Circuit of the present invention, 8.9...Output terminal, 10.12
... Voltage 0N10FF input/output terminal, 11... Voltage detection terminal, 13... Ground terminal, Ql, Q2. Q
3. Q4...transistor, Dl...diode, D2. D3. D4. D5... Constant voltage diode, R1, R2, R3, R4, R5, R6, R7°R8
...Resistance patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai Figure 3
Claims (1)
スタと、この第１のトランジスタのベースに接続され低
電圧時及び高電圧時にこの第１のトランジスタを“ＯＦ
Ｆ”するように働く２本のツェナーダイオード及び第２
のトランジスタとを含むことを特徴とするＤＣ−ＤＣコ
ンバータの出力電圧異常防止回路。A first transistor that controls the oscillation of the DC-DC converter, and a first transistor that is connected to the base of the first transistor and turns the first transistor "OOFF" at low voltage and high voltage.
Two Zener diodes and a second
An output voltage abnormality prevention circuit for a DC-DC converter, comprising a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23880184A JPS61121771A (en) | 1984-11-13 | 1984-11-13 | Abnormal output voltage preventing circuit of dc/dc converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23880184A JPS61121771A (en) | 1984-11-13 | 1984-11-13 | Abnormal output voltage preventing circuit of dc/dc converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61121771A true JPS61121771A (en) | 1986-06-09 |
Family
ID=17035489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23880184A Pending JPS61121771A (en) | 1984-11-13 | 1984-11-13 | Abnormal output voltage preventing circuit of dc/dc converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61121771A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219708A (en) * | 2012-01-23 | 2013-07-24 | 三美电机株式会社 | Battery protecting circuit, battery protecting device, and battery pack |
-
1984
- 1984-11-13 JP JP23880184A patent/JPS61121771A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219708A (en) * | 2012-01-23 | 2013-07-24 | 三美电机株式会社 | Battery protecting circuit, battery protecting device, and battery pack |
| JP2013150521A (en) * | 2012-01-23 | 2013-08-01 | Mitsumi Electric Co Ltd | Battery protection circuit, battery protection device, and battery pack |
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