JPS61121517A - Signal change detecting circuit - Google Patents

Abstract

PURPOSE:To ensure a sharp rise of an output pulse, by adding an electronic switch and a delay signal generating circuit, in a circuit which detects the change of an input signal and produces a 1-shot output pulse. CONSTITUTION:When an address signal Ai changes to H from L, a 1-shot pulse of H having the time width decided by the delay time T is produced at the output phii of an EX-OR circuit 1i. An inverter consisting of an FET Q2 and Q1i is actuated and a 1-shot pulse of L is produced at an output terminal 3 with a small delay. This pulse is supplied to a delay signal generating circuit and a 1-shot pulse delayed by T0approx.=T is applied to the gate of an FET Q4 serv ing as a control terminal of an electronic switch 6. At this time point the FET Q4 conducts and contributes to the rise of the terminal 3. Thus a sharp rise is secured as shown by a solid line (m).

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a circuit for detecting changes in an input signal, including an MO8 type FIT. The present invention relates to an input signal change detection circuit that detects a change in an address input signal of a static memory circuit used and generates a one-shot pulse.

[Conventional technology]

In recent years, in friend memory circuits using MO8 type FET1,
A change in the address input signal is detected, a one-shot pulse is generated, and the decoder circuit, digit circuit, etc. are precharged with this pulse. By precharging and balancing the differential output section, which aims to reduce power consumption, high-speed t-H can also be achieved.

As a conventional example of the above-mentioned human input signal change detection circuit, P type M
The circuit of FIG. 5 using an O8FET and an N-type MO8FET is typical.

This circuit consists of parallel N-type MO8FETs Ql, J~Q
,.

is an inverter that has all P-type MO8FET Q2 as a common load ◎ Below, N-type MO8FET is N-
Abbreviated as MOS and P-MOS.

Each bit signal of address signals Afl is input to EX-OR circuits 10 to 1n directly and via delay elements DQ%DfI, respectively. The delay time is the same and is assumed to be T.

If one of the address signals A Q %A n , for example, Ai, changes, the output button of the EX-OR circuit 1 outputs a shot pulse at time -T, as shown in the time chart of FIG. t- occurs. This output φ1 turns on N-MO8 (Jli), and the negative one-shot pulse shown in the figure is generated at the output terminal 5. This pulse precharges each circuit of the memory used in the MO8FET. The above circuit is a NOR circuit. When all the configurations are completed and the address signals AQ to A0 change, the one-shot pulse force is generated.

By the way, in the circuit shown in Figure 3, P-MO8Q2 and N-
MOS Qlo-Q+U constitutes a ratio circuit, and its switching characteristics are determined by the beta ratio, that is, N-MO8Q+
Transconductance of o-QlH vs. p-MO of load
It is determined by the ratio of transconductance of 8Q2. The characteristic is good when the beta ratio is large, and the output level can be kept low.Therefore, considering the connection with the next stage, the transconductance of N-MO5Q+.~Q+n should be set so that the beta ratio is large. Then, since the number of A is large, the overall chip size becomes large, leading to an increase in power consumption.By reducing the transconductance of P-MO8Q2, the Peter ratio can be increased. As a result, the flow capacity of p-MO8Qlo1 is limited, and the speed at which the pulse at the output terminal 3 changes from "L" to "H" becomes slow as shown in Figure 4. , this is especially noticeable because the load capacity is large. If the change is slow, the start of operation after precharging will be delayed, resulting in the inability to operate at high speed. 6 90 [Problems to be solved by the invention] ] An object of the present invention is to eliminate the above-mentioned drawbacks and to provide an input signal change detection circuit which adjusts to changes in an input signal and generates a short shot pulse.

It is an object of the present invention to provide a circuit that generates a pulse with a steep fall and whose pulse time width is limited to the time required for precharging. However, since the falling edge is usually sufficiently steep, the rising characteristic should be improved.

[Means for solving problems]

The circuit of the present invention connects an electronic switch between the output terminal of a conventional human power signal change detection circuit and a power source, and inputs an output pulse between the control terminal of the electronic switch and the output terminal, A delay signal generation circuit is provided which generates a delay pulse delayed by the one-shot pulse width and makes the electronic switch conductive.

As shown in the conventional example WJ3 diagram, when the load is a P type and the drive element is an N type MO8FE'l', when a P type MO8FET is used as an electronic switch, the output pulse is a one-shot pulse at the gate electrode. A shaping pulse delayed by a certain width is applied. When an N-type MO8FET is used as the electronic switch, a delayed pulse obtained by inverting the output one-shot pulse is applied to the gate '1E pole.

[For production]

In the present invention, the electronic switch starts operating and conducts just at the trailing edge of the one-shot pulse at the output of the input signal change detection circuit, and the current passing through this path charges the capacitance of the output terminal.

This current is added as a rising charging current to the charging current caused by the FIT of the load of the inverter circuit, so that the rising speed becomes faster.

[Example of sacrifice] FIG. 1 shows a circuit diagram of an embodiment of the present invention.

N-MOS Q1o to Gh a form a logic circuit, and P-
MO8Q2 forms an inverter as a load, and each N-M
EX-OR circuit 10 is connected to the gate of O3Gho=Q1a.
To the 0EX-OR circuits 10 to 1a to which the outputs φ0 to φ1 of ~1n are applied, address signals AQ%A are applied directly and through delay elements Do%D (the delay times of which are the same). The configuration of the circuit portion described above is similar to that of the conventional example shown in FIG. 5, and all < fWJ.

In this embodiment, in the above circuit, the output terminal 5 and the terminal V
, P-MO3QJ are connected in series, and a VC delay signal generating circuit 5 is provided between the output terminal 3 and the gate' polarization of P-MO3Q4. The delayed signal generating circuit 5 is a CMOS two-stage circuit as shown, with a capacitor CO added between them, and its output signal is delayed by exactly the time equal to the input pulse tTo from the output terminal 3, and becomes a ratio signal. Here, To is approximately equal to the delay time T of the delay element ~D0.

The newly provided P-MO8Q4 is composed of electronics and a six-metal switch, and is provided to charge the capacitor t of the output terminal 3. The operation will be explained using the time chart shown in FIG. Among the address signals, Ai is from °1L'' to H at two points as shown in the figure.
'1, EX-OR circuit 1) 17) The inverter consisting of OP-MOS Q2 and N-MOS Sushi generates a one-shot pulse of ``H'' with a time width (D) defined by the delay time T in the output φ amount. and output terminal 3 °1),1
) is generated with a slight delay. This one-shot pulse is generated manually by the delay 1g generation circuit 5, and is applied to the gate electrode of P-MO8Q, which is the control terminal of the electronic switch 60. A one-shot pulse is applied. From this point on, P-MO8Q4 becomes conductive and contributes to the rise of the voltage at the output terminal 3. With this determination, in the conventional circuit, the rise indicated by the dotted line ! is as shown by the solid line ゛- It becomes steep. When A1 changes from H6 to 1L'' at 9 points, the voltage rise at the output terminal 3 similarly becomes steep.

Since the relationship between P-MO3Q4 and N-MOS QIe-Q+ is a ratioless circuit, P-MO8
Q4 transconductance ah, N-MO8Q,
Can be selected regardless of O to Q+1. So this P-1i1
) The above-mentioned remarkable effect can be obtained by increasing only the size of 0SQ4 and increasing the flow capacity.

Next, an N-type MOS FET is conveniently used as the electronic switch 6, and a third embodiment of the present invention is shown in FIG.

At this time, since the polarity of the one-shot pulse appearing at the output terminal 3 does not drive N-1i'lO8Q7, the delay signal generation circuit 5 is a -CMO8z slope circuit, which is placed next to the delay circuit to which the intermediate Vc response amount Cak is added. A circuit that connects a CMOS inverter to invert the phase? use

[@Akira's effect] As detailed above, in a conventional input signal change detection circuit, the one-shot pulse output stage is a ratio circuit, so the size of the load MOSFET is limited and the current capacity is limited. Due to the low fco and the slow rise of the shot pulse, the precharge time did not end early, making it impossible to speed up the memory circuit. In the present invention, an electronic switch is separately provided between the output terminal and the power supply, and the electronic switch is turned on at exactly 9 points in time when the one-shot pulse rises, and the tr! jp, the current charges the output terminal capacitor and makes its rise steep. Full use of MOS FET as an electronic switch,
Its size is different from that of the output stage ll1A@MO8b'Er since the entire ratioless circuit is formed, so the current capacity can be increased by increasing its size.

In the circuit of the present invention, the designed one-shot pulse t- is generated only for the period required for precharging the memory circuit, which is advantageous for speeding up and reducing power consumption.

In FIGS. 1 and 5, the gate electrode of the load MO3FET is grounded, but it is also possible to operate it by applying an external control signal, and the effects of the present invention are the same in that case.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an operation time chart of the circuit, and FIG. 3 is a circuit diagram of an embodiment of the present invention. FIG. 4 is a circuit diagram and operation time chart of a conventional circuit, and FIG. 5 is a circuit diagram of another embodiment of the present invention. 10~1 a-EX-OR circuit, Do~D,
-... Delay element, 3 - Output terminal, 5... Delay signal axis main circuit, 6... Electronic switch, QIoS-Qln, Q7 -N MOS
FET, Q2, Q4...P-M
OS FgTAo~An...Address decoding. Applicant: NEC IC Microcomputer System Co., Ltd. Agent: Patent Attorney: Kazuhiro Yen Hara / Figure 1 AoAL An 2nd v! U

Claims (2)

[Claims] (1) In a circuit that detects a change in an input signal and generates a one-shot output pulse, an electronic switch is connected between an output terminal of the circuit and a power supply, and a control terminal of the electronic switch and the output terminal are connected. 1. An input signal change detection circuit comprising: a delay signal generation circuit which inputs an output pulse during the period of time, generates a delayed pulse delayed by approximately a one-shot pulse width, and makes the electronic switch conductive. (2) The electronic switch in item 1 above is a MOS FET,
The fourth claim, wherein the control terminal is a gate electrode.
Input signal change detection circuit described in .