JPS61121361A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61121361A JPS61121361A JP24240684A JP24240684A JPS61121361A JP S61121361 A JPS61121361 A JP S61121361A JP 24240684 A JP24240684 A JP 24240684A JP 24240684 A JP24240684 A JP 24240684A JP S61121361 A JPS61121361 A JP S61121361A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- layer
- base
- conduction type
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000007888 film coating Substances 0.000 abstract 1
- 238000009501 film coating Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910001423 beryllium ion Inorganic materials 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 206010011224 Cough Diseases 0.000 description 1
- 241001236294 Hebe Species 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910001425 magnesium ion Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高速のへテロ接合バイポーラ・トランジスタ
（ｈｅｔｅｒｏｊｕｎｃｔｉｏｎ ｂｉｐｏｌａｒ
ｔｒａｎｓｉｓｔｏｒ：ＨＢＴ）と呼ばれる半導体装
置を製造するのに好適な方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a high speed heterojunction bipolar transistor.
The present invention relates to a method suitable for manufacturing a semiconductor device called a transistor (HBT).
第３図は従来技術で製造されたＨＢＴの要部切断側面図
である。FIG. 3 is a cutaway side view of essential parts of an HBT manufactured by the conventional technique.
図に於いて、ｌは半絶縁性ＧａＡｓ基板、２はｎ＋型Ｇ
ａＡｓコレクタ・コンタクト層、３はｎ型Ｇ ａ Ａ
ｓコレクタ層、４はｐ“型ＧａＡＳベース層、５はｎ型
ＡｌＧａＡｓエミツタ層、６はエミッタ電極、７はベー
ス電極、８はコレクタ電極、９は外部ベース抵抗をそれ
ぞれ示している。In the figure, l is a semi-insulating GaAs substrate, 2 is an n+ type G
aAs collector contact layer, 3 is n-type Ga A
4 is a p" type GaAS base layer, 5 is an n type AlGaAs emitter layer, 6 is an emitter electrode, 7 is a base electrode, 8 is a collector electrode, and 9 is an external base resistance.
本従来例を製造する場合、基板１にコンタクト層２、コ
レクタ層３、ベース層４、エミッタＮ５を連続してエピ
タキシャル成長させ、その後、メサ・エツチングして諸
電極の引き出しゃ電極形成を行っている。When manufacturing this conventional example, a contact layer 2, a collector layer 3, a base layer 4, and an emitter N5 are successively epitaxially grown on a substrate 1, and then mesa etching is performed to extract various electrodes and form electrodes. .
前記構造のＨＢＴに於いては、次に列挙するような問題
がある。The HBT having the above structure has the following problems.
（１） ベース層４の厚さは全面に亙り一様であり、
従って、ベース・エミッタ接合の下側部分もベース電極
７の引き出し部分も同じであるから外部ベース抵抗８の
値が高い。(1) The thickness of the base layer 4 is uniform over the entire surface,
Therefore, since the lower part of the base-emitter junction and the extended part of the base electrode 7 are the same, the value of the external base resistance 8 is high.
（２）ベース層４が面内に拡がっている為、適当なアイ
ソレーションを施したり、或いは、イオン注入を行わな
いと、ベース・コレクタ接合面積が広すぎてコレクタ容
量が大である。(2) Since the base layer 4 extends in-plane, the base-collector junction area will be too large and the collector capacitance will be large unless appropriate isolation or ion implantation is performed.
（３）エミツタ層５が面内に拡がっている為、適当なア
イソレーションを施したり、或いは、イオン注入を行わ
ないと、エミッタ・ベース接合面積が広すぎ且つエミッ
タのフィンガ輻Ｗが広すぎてエミッタ容量が大であると
共にベース抵抗も大きい。(3) Since the emitter layer 5 spreads in-plane, unless proper isolation or ion implantation is performed, the emitter-base junction area and the emitter finger radius W will be too wide. The emitter capacitance is large and the base resistance is also large.
ＨＢＴに関し、ここに挙げたような問題が存在すると、
そのスイッチング・スピードが低下することは云うまで
もない。Regarding HBT, if there are problems such as those listed here,
Needless to say, the switching speed is reduced.
本発明は、ＨＢＴの構造に若干の改変を加え、前記（１
）乃至（３）に挙げた問題を解消し、スイッチング・ス
ピードを向上しようとする。In the present invention, the structure of HBT is slightly modified, and the above (1)
) to (3), and attempt to improve switching speed.
本発明に依る半導体装置の製造方法では、半絶縁性基板
上に少なくとも一導電型コレクタ層を含み表面を反対導
電型ベース領域が形成された半導体層或いは反対導電型
ベース層とした多層半導体層を形成し、次いで、全面を
覆う絶縁膜を形成してから前記反対導電型ベース領域或
いは前記反対導電型ベース層の一部表面を選択的に露出
する開口を形成し、次いで、前記反対導電型ベース領域
或いは前記反対導電型ベース層のハンド・ギャップより
広いそれを有する一導電型エミッタ層を形成するように
している。In the method for manufacturing a semiconductor device according to the present invention, a semiconductor layer including a collector layer of at least one conductivity type and having a base region of an opposite conductivity type formed on the surface thereof, or a multilayer semiconductor layer having a base layer of an opposite conductivity type is formed on a semi-insulating substrate. forming an insulating film covering the entire surface, forming an opening to selectively expose a part of the surface of the opposite conductivity type base region or the opposite conductivity type base layer; An emitter layer of one conductivity type is formed having a region or a hand gap wider than the hand gap of the base layer of the opposite conductivity type.
このようにすると、エミッタ・ベース接合面積或いはベ
ース・コレクタ接合面積を小さくすることができ、エミ
ッタ容量やコレクタ容量を低下させることが可能となり
、また、ベース領域或いはベース層に於いて実効的なベ
ースとして動作する部分以外を厚くして外部ベース抵抗
を低下させることが可能である。In this way, the emitter-base junction area or base-collector junction area can be reduced, emitter capacitance and collector capacitance can be reduced, and the effective base area in the base region or base layer can be reduced. It is possible to reduce the external base resistance by making the parts other than those that operate as thicker.
第１図は本発明一実施例を説明する為の工程要所に於け
る半導体装置の要部切断側面図を表し、第３図に関して
説明した部分と同部分は同記号で指示しである。FIG. 1 shows a cutaway side view of a main part of a semiconductor device at a key point in the process for explaining one embodiment of the present invention, and the same parts as those explained with reference to FIG. 3 are indicated by the same symbols.
本実施例では、ｎ型ＧａＡＳコレクタ層３を成長させる
までは第３図について説明した従来技術を適用すること
ができるので、その後の工程から説明する。In this embodiment, the conventional technique explained with reference to FIG. 3 can be applied until the n-type GaAS collector layer 3 is grown, so the subsequent steps will be explained.
（ａｌ 化学気相堆積（ｃｈｅｍｉｃａ １ ｖａ
ｐ。(al chemical vapor deposition (chemica 1 va)
p.
ｕｒ ｄｅｐｏｓｉｔｉｏｎ：ＣＶＤ）を適用するこ
とに依り二酸化シリコン（ＳｉＯ２）膜１１を厚さ約５
０００ Ｃ人〕程度に形成する。The silicon dioxide (SiO2) film 11 is deposited to a thickness of approximately 5 cm by applying CVD.
000 C people].
巾）通常のフォト・リソグラフィ技術並びに化学エツチ
ング法を適用することに依り、ＳｉＯ２膜１１のバター
ニングを行い、ベース領域形成予定部分に対応する開口
を形成する。Width) The SiO2 film 11 is patterned by applying ordinary photolithography technology and chemical etching method to form an opening corresponding to the portion where the base region is to be formed.
（ｃｌ 該開口の形成に用いたマスク（図示せず）を
そのままにした状態でイオン注入法を適用することに依
り、ヘリリウム（Ｂｅ）イオン或いはマグネシウム（Ｍ
ｇ’）イオンのデポジション及び活性化を行ってｐ＋型
ヘベー領域１２を形成する。(cl) By applying the ion implantation method while leaving the mask (not shown) used to form the opening, helium (Be) ions or magnesium (M
g') Perform ion deposition and activation to form p+ type Hebe region 12.
この場合に於けるＢｅイオン或いはＭｇイオンのドーズ
量は、例えばＩ Ｘ １０” （ｃｍ−”）とし、ま
た、加速エネルギを２０（ＫｅＶ）とすることができる
。In this case, the dose of Be ions or Mg ions can be set to, for example, I x 10''(cm-''), and the acceleration energy can be set to 20 (KeV).
前記のような工程に代替するものとして、基板に厚さ２
０．００Ｃ人〕程度のＡｌＮ膜を形成してから、その膜
を介してドーズｆｆ１ｌｘ１０＋５（ｃｍ −” ）
、加速エネルギ３０（ＫｅＶ）としてＢｅイオンを注入
するようにしても良い。As an alternative to the above process, the substrate may be coated with a thickness of 2
After forming an AlN film with a thickness of about 0.00 cm, a dose of ff1lx10+5 (cm −”) is applied through the film.
, Be ions may be implanted at an acceleration energy of 30 (KeV).
尚、活性化は後の工程で単独或いは他の熱処理を兼ねて
実施することができる。Note that activation can be performed alone or in combination with other heat treatments in a later step.
ｆｄｌ マスクを除去してから、分子線エピタキシャ
ル成長（ｍｏｌｅｃｕｌａｒ ｂｅａｍ ｅｐｉｔ
ａｘｙ：ＭＢＥ）法を適用することに依り、ｎ型Ａｊｉ
！ＧａＡｓエミッタ層５を厚さ約３０００（人）程度に
形成する。After removing the fdl mask, molecular beam epitaxial growth (molecular beam epitaxial growth) is performed.
axy:MBE) method, n-type Aji
! A GaAs emitter layer 5 is formed to a thickness of about 3,000 layers.
（ｅｌ 通常のフォト・リソグラフィ技術及び適当な
エツチング法を適用することに依り、ｎ型Ａ／ＧａＡｓ
エミツタ層５のパターニングを行う。(el By applying conventional photolithography techniques and appropriate etching methods, n-type A/GaAs
The emitter layer 5 is patterned.
（ｆｌ この後、通常の技法を適用することに依り、
エミッタ電極６、或いは、その他の諸電罹・配線やパッ
シベーション膜などを形成して完成する。尚、この場合
、ベース電極はエミッタ電極６に対して２次元的に形成
されることになり、また、コレクタ電極はＳ ｉ Ｏ２
膜１１及びコレクタ層３をメサ・エツチングしてコンタ
クト層２０表面を選択的に露出させて形成することにな
る。(fl After this, by applying the usual techniques,
The emitter electrode 6 or other electrical conductors, wiring, passivation film, etc. are formed to complete the process. In this case, the base electrode is formed two-dimensionally with respect to the emitter electrode 6, and the collector electrode is formed of SiO2.
The film 11 and the collector layer 3 are mesa-etched to selectively expose the surface of the contact layer 20.
この実施例に依り製造された半導体装置では、ベース・
コレクタ接合面積が小さいのでコレクタ容量が低減され
、また、第３図に見られる従来例に比較するとエミッタ
・ベース接合面積を小さく且つエミッタのフィンガ幅も
小さくすることが可能であるからエミッタ容量も低減さ
れ、更にまた、外部ベース抵抗も小さくすることができ
る。In the semiconductor device manufactured according to this embodiment, the base
Collector capacitance is reduced because the collector junction area is small, and emitter capacitance is also reduced because the emitter-base junction area and emitter finger width can be made smaller compared to the conventional example shown in Figure 3. Moreover, the external base resistance can also be reduced.
第２図は本発明に於ける第２の実施例を説明する為の工
程要所に於ける半導体装置の要部切断側面図を表し、第
１図及び第３図に関して説明した部分と同部分は同記号
で指示しである。FIG. 2 is a cross-sectional side view of a main part of a semiconductor device at a key point in the process for explaining a second embodiment of the present invention, and shows the same part as the part explained with respect to FIGS. 1 and 3. is indicated by the same symbol.
本実施例では、ｐ＋型ＧａＡｓヘベ一層４を成長させる
までは第３図について説明した従来技術を適用すること
ができるので、その後の工程から説明する。In this embodiment, the conventional technique explained with reference to FIG. 3 can be applied until the p+ type GaAs heave layer 4 is grown, so the subsequent steps will be explained.
１ａｌｃＶＤ法を適用することに依り、５ｉ０２膜１１
を厚さ約１０００ Ｃ人〕程度に形成する。By applying the 1alcVD method, the 5i02 film 11
The thickness is approximately 1,000 mm thick.
ｔｂ＋ 通常のフォト・リソグラフィ技術並びに化学
エツチング法を適用することに依り、ＳｉＯ２膜のパタ
ーニングを行い、エミッタ領域形成予定部分に対応する
開口を形成する。tb+ By applying ordinary photolithography technology and chemical etching method, the SiO2 film is patterned to form an opening corresponding to the portion where the emitter region is to be formed.
（Ｃ） 該開口の形成に用いたマスク（図示せず）を
そのままにした状態でｐ＋型ヘベ一層４のエツチングを
行い、深さ約２０００ Ｃ人〕程度の凹所４Ａを形成
する。(C) With the mask (not shown) used to form the opening left in place, the p+ type heave layer 4 is etched to form a recess 4A with a depth of about 2000 mm.
これに依り、ｐ＋型ベース層４は局部的に厚さが１００
０ Ｃ人〕になる。As a result, the p+ type base layer 4 has a local thickness of 100 mm.
0 C people].
（ｄ）マスクを除去してから、ＭＢＥ法を適用すること
に依り、ｎ型Ａ６ＧａＡｓエミッタ層５を厚さ約５００
０ Ｃ人〕程度に形成する。(d) After removing the mask, by applying the MBE method, the n-type A6GaAs emitter layer 5 is formed to a thickness of approximately 500 mm.
0 C people].
（Ｑｌ 通常のフォト・リソグラフィ技術及び適当な
エツチング法を適用することに依り、ｎ型ＡｆｆＱａＡ
ｓエミッタ層５のパターニングを行う。(Ql By applying normal photolithography techniques and appropriate etching methods, n-type AffQaA
Patterning of the s emitter layer 5 is performed.
げ） この後、通常の技法を適用することに依り、エミ
ッタ電極６、或いは、その他の諸電極・配線やパッシベ
ーション膜などを形成して完成する。尚、ベース電極の
形成に関しては第１図に−ついて説明した実施例と同様
であり、また、コレクタ電極に関してはＳ ｉ０２膜１
１、ベース層４、コレクタ層３をメサ・エツチングして
コンタクト層２の表面を選択的に露出させて形成する。(G) After this, the emitter electrode 6, other electrodes/wirings, passivation film, etc. are formed and completed by applying normal techniques. The formation of the base electrode is the same as in the embodiment described with reference to FIG.
1. The base layer 4 and the collector layer 3 are mesa-etched to selectively expose the surface of the contact layer 2.
この実施例に依り製造された半導体装置では、エミッタ
・ベース接合面積が小さく且つエミ・ツタのフィンガ幅
も小さいのでエミッタ容量が低減され、また、エミッタ
・ベース接合直下のベース層以外のベース層は厚いので
外部ベース抵抗の値は低く維持される。In the semiconductor device manufactured according to this embodiment, the emitter capacitance is reduced because the emitter-base junction area is small and the emitter-vine finger width is also small, and the base layer other than the base layer directly under the emitter-base junction is The thickness keeps the value of the external base resistance low.
本発明に依る半導体装置の製造方法では、半絶縁性基板
上に一導電型コレクタ層に反対導電型ベース領域を形成
した後、或いは、咳−導電型コレクタ層上に反対導電型
ベース層を形成した後、その全面を絶縁膜で覆い、その
絶縁膜に開口を形成して前記反対導電型ベース領域或い
は前記反対導電型ベース層の一部表面を露出させ、その
上に咳ベース領域或いはベース層のハンド・ギヤツブよ
り広いそれをもつ一導電型エミッタ層を形成するように
している。In the method for manufacturing a semiconductor device according to the present invention, after forming a base region of an opposite conductivity type on a collector layer of one conductivity type on a semi-insulating substrate, or forming a base layer of an opposite conductivity type on a collector layer of a conductivity type. After that, the entire surface is covered with an insulating film, an opening is formed in the insulating film to expose a part of the surface of the base region of the opposite conductivity type or the base layer of the opposite conductivity type, and a cough base region or the base layer is formed on the base region or the base layer of the opposite conductivity type. An emitter layer of one conductivity type is formed which has a width wider than that of the hand gear.
このような本発明を実施して製造される半導体装置に於
いては、エミッタ・ベース接合面積やエミッタのフィン
ガ幅を小さくすることができるのでエミッタ容量を低減
させることが可能であり、また、ベース・コレクタ接合
面積を小さくすることができるのでコレクタ容量を低減
することが可能であり、更にまた、外部ベース抵抗も小
さくすることができる。In a semiconductor device manufactured by implementing the present invention, the emitter-base junction area and the emitter finger width can be reduced, so the emitter capacitance can be reduced, and the emitter capacitance can be reduced. - Since the collector junction area can be reduced, the collector capacitance can be reduced, and furthermore, the external base resistance can also be reduced.
このような半導体装置に於けるス−（，７チング・スピ
ードが向上していることは云うまでも７ぽい。It goes without saying that the processing speed of such semiconductor devices has been improved.
第１図は本発明一実施例を説明する為の工程要所に於け
る半導体装置の要部切断側面図、第２図は本発明の第２
の実施例を説明する為の工程要所に於ける半導体装置の
要部切断側面図、第３図は従来例を説明する為の工程要
所に於ける半導体装置の要部切断側面図をそれぞれ表し
ている。
図に於いて、■は半絶縁性ＧａＡｓ基板、２はｎ＋型Ｇ
ａＡｓコレクタ・コンタクト層、３はｎ型ＧａＡｓコレ
クタ層、４はｐ＋型ＧａＡｓベース層、４Ａは凹所、５
はｎ型Ａｊ２ＧａＡｓｘミッタ層、６°はエミッタ電極
、７はベース電極、８はコレクタ電極、９は外部ペース
抵抗、１１は５ｉ０２膜、１２はｐ＋型ベース領域をそ
れぞれ示している。
特許出願人 富士通株式会社
代理人弁理士 相 谷 昭 司
代理人弁理士 渡 邊 弘 −
第１図
第２図
第３図FIG. 1 is a cutaway side view of a main part of a semiconductor device at a key point in the process for explaining one embodiment of the present invention, and FIG.
FIG. 3 is a cut-away side view of the main part of a semiconductor device at a key point in the process to explain an embodiment of the present invention, and FIG. represents. In the figure, ■ is a semi-insulating GaAs substrate, 2 is an n+ type G
aAs collector contact layer, 3 is n-type GaAs collector layer, 4 is p + type GaAs base layer, 4A is recess, 5
is an n-type Aj2GaAsx emitter layer, 6° is an emitter electrode, 7 is a base electrode, 8 is a collector electrode, 9 is an external space resistor, 11 is a 5i02 film, and 12 is a p+ type base region. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney: Shoji Aitani Representative Patent Attorney: Hiroshi Watanabe - Figure 1 Figure 2 Figure 3
Claims (1)
み表面を反対導電型ベース領域が形成された半導体層或
いは反対導電型ベース層とした多層半導体層を形成し、
次いで、全面を覆う絶縁膜を形成してから前記反対導電
型ベース領域或いは前記反対導電型ベース層の一部表面
を選択的に露出する開口を形成し、次いで、前記反対導
電型ベース領域或いは前記反対導電型ベース層のバンド
・ギャップより広いそれを有する一導電型エミッタ層を
形成する工程が含まれてなることを特徴とする半導体装
置の製造方法。Forming on a semi-insulating substrate a semiconductor layer including a collector layer of at least one conductivity type and having a base region of an opposite conductivity type formed on the surface thereof, or a multilayer semiconductor layer having a base layer of an opposite conductivity type,
Next, after forming an insulating film covering the entire surface, an opening is formed to selectively expose a part of the surface of the base region of the opposite conductivity type or the base layer of the opposite conductivity type, and then, the base region of the opposite conductivity type or the base layer of the opposite conductivity type is formed. 1. A method of manufacturing a semiconductor device, comprising the step of forming an emitter layer of one conductivity type having a band gap wider than a base layer of an opposite conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24240684A JPS61121361A (en) | 1984-11-19 | 1984-11-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24240684A JPS61121361A (en) | 1984-11-19 | 1984-11-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61121361A true JPS61121361A (en) | 1986-06-09 |
Family
ID=17088661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24240684A Pending JPS61121361A (en) | 1984-11-19 | 1984-11-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61121361A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6218761A (en) * | 1985-07-18 | 1987-01-27 | Matsushita Electric Ind Co Ltd | Hetero junction transistor and manufacture thereof |
| JPS63316473A (en) * | 1987-06-18 | 1988-12-23 | Nippon Telegr & Teleph Corp <Ntt> | Bipolar transistor |
| JP2009206325A (en) * | 2008-02-28 | 2009-09-10 | Hitachi Ltd | Semiconductor device, and manufacturing method thereof |
-
1984
- 1984-11-19 JP JP24240684A patent/JPS61121361A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6218761A (en) * | 1985-07-18 | 1987-01-27 | Matsushita Electric Ind Co Ltd | Hetero junction transistor and manufacture thereof |
| JPS63316473A (en) * | 1987-06-18 | 1988-12-23 | Nippon Telegr & Teleph Corp <Ntt> | Bipolar transistor |
| JP2009206325A (en) * | 2008-02-28 | 2009-09-10 | Hitachi Ltd | Semiconductor device, and manufacturing method thereof |
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