JPS61121084A - Access system for memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access method, and particularly to a dynamic random access memory (Dyna-*ic).
Random Access Memory: Below,
This provides a high-speed and efficient access method for large-capacity memory such as image memory using DIIAM (DIIAM).

[Prior art]

For large-capacity memory, such as memory used for image file systems, the capacity should be as large as possible.
Moreover, it is necessary to enable high-speed and highly efficient access to this large-capacity memory to perform rapid image processing.

From the above point of view, for example, Japanese Patent Application Laid-Open No. 57-114182
The invention of No. 1 is proposed. In this invention, the memory element is
We have proposed an access method that allows data to be written and read in a single access from either the X or Y directions in a two-dimensional memory space arranged in a matrix in the -Y direction. In other words, N is formed by arranging N 1-bit×N memory elements in a direction perpendicular to the bit arrangement direction.
In a square X-Y 22-dimensional memory space of XN bits, the address allocation is converted so that the address assignments are arranged in a direction parallel to the diagonal in the bit array matrix, and the data is written accordingly. Alternatively, the above object is achieved by shifting the data to be read.

Furthermore, in recent years, DRA gates have been increasingly used as memory devices, but writing and reading data, that is, accessing data to DRAMs, is performed using, for example, a row address strobe (Ras Address Strobe).
be (hereinafter referred to as llAs) signal to all DRAM elements, and also sends a column signal to the DRAM element to be accessed.
Address strobe (01LI#l address strobe)
sS probe (hereinafter referred to as CAS) signal. As a result, only the memory element to which both the RAS signal and the CAS signal are applied is enabled and can be accessed.

[Problem that the invention seeks to solve]

However, in the invention of JP-A-57-114182 mentioned above, only a square memory space can be configured, and a fairly large capacity is required to configure an image memory.
The value of is extremely large, and when it is implemented as an actual device, a huge amount of memory elements and circuit devices such as address converters attached to each are required, which poses a difficulty in practical application.

In addition, when using a conventional static RAM other than a DRAM, the address for accessing memory elements arranged in a matrix is an X-Y select signal that instructs row or column designation, and a row or column However, conventional static RAM usually has only one enable terminal, and therefore each RAM is provided with an X-Y select signal to specify the row or column of the code signal. I needed a selector to select the part that specified.

(Structure of the invention) The present invention has been made in view of the above circumstances,
As shown in FIG. 1, a 1 bit×N DRAM element 11E
, ME, . . . are arranged in Lllil in one arbitrary direction and M L×M matrices in a direction perpendicular to this direction to form a three-dimensional memory space of L×MXN bits. Then, a two-dimensional memory space 1 of L x M bits is formed by bits at the same position of each DRAM element ME.
-1. 1-2...1-n are I III memory planes PI, P2...Pn, and each of these N memory planes P is on a <X-Y two-dimensional plane z as shown in FIG. K (I (however, K≦N)) are sequentially arranged in the X direction.

After adopting the above configuration, each Dl? Each memory plane P is designated by the lower address that designates the bit of the AM element 6E, and the RAS terminal and CAS terminal of the DRAM element ME are used as enable terminals, respectively.
By controlling the RAS signal and the CAS signal with the When specifying , the llAs signal is applied to each DRAM element i ME in the specified row, and the CAS signal is applied to all DRAM elements ME, and the DRA11 element 6E to which both signals are applied, that is, the specified I
) RAMi child ME is enabled. On the other hand, when specifying a column, the RAS signal is given to all DRAFI elements ME, and the CA signal is applied to each DRAM element ME in the specified column.
S signal is given, which causes both signals to be given DI
IAM element ME, i.e. DRAM element AE in the specified column
is enabled.

Furthermore, data can be written to the memory configured as described above with one access in either the X or Y direction.
In order to enable Vt output, the DRAM elements 6E arranged diagonally on each memory plane P are connected to the same line of the data bus. To write data to a memory element or read data from each memory element,
In other words, data is written according to the upper address,
Data input/output is performed by shifting the input/output data by a predetermined number of bits according to the row or column to be read.
RAM! Child? Data input/output processing is possible by simply connecting each line of the data bus to the IE.

By adopting the above configuration, the present invention provides a DRAM
It is possible to create a memory structure that is not limited to a square shape, and to shorten access time to enable data writing and reading with higher speed and commercial efficiency. The purpose of this invention is to provide a memory access method that can suppress an increase in the number of devices.

The present invention can move a 1-bit×N DRAM element in any direction (
L pieces in the X direction), and a direction perpendicular to the X direction (Y direction)
A three-dimensional memory space of L×MXN bits arranged in M(II) is constructed, and the DRA?
! The memory configuration is such that a memory plane consisting of a two-dimensional memory space of L×M bits formed in N pieces in the bit arrangement direction of the element is arranged in a two-dimensional space, and a memory plane is arranged in a two-dimensional space in the diagonal direction on the X-Y plane of the three-dimensional memory space. When each DRAM element in a row is connected to the same line of the data bus, each memory plane is specified by specifying the bit of each DRAM element using the lower address, and the row is specified using the upper address. Ha, all DRA? 'A CAS signal is given to the l element and a RAS signal is given to each DRAM element in a specified row, and if a column is specified, all DRA? ! By applying a RAS signal to the element and a CAS signal to each DRAM element in a designated column, a designated row or column in each memory plane is enabled, and the input/output data is transferred to a predetermined bit according to the upper address. The present invention is characterized in that data is written and read by shifting several times, and each DRAM element is refreshed by applying the RAS signal or CAS signal to all DRAM elements while no access is being performed.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 3 is a schematic diagram showing the configuration of an embodiment in which the memory access method according to the present invention is applied to an image file system, and FIG. 4 shows the arrangement of memory elements of the image memory. The schematic diagram shown in FIG. 5 is a circuit diagram showing the connection state between each memory element constituting the image memory and each line of the data bus.

Reference numeral 12 in the figure is an image memory that stores image information as data, and as shown in FIG.
The DRAM element gate E is configured as a three-dimensional memory space of L×M arrays of L×MXN bits, but in this embodiment, as shown in FIG.
AM elements M elements to 6E16 are arranged in a matrix of 4(·L)×4(·6).

Each bit of N[ of each 0RAPI element 11E is sequentially assigned an address from 1 to N (hereinafter referred to as a lower address) in the same direction.

Therefore, 161 m [lRA? N two-dimensional memory spaces of 4 (,L) x 4 (,M) bits are formed by the lower address of the I element and the ME element. Then, each of these two-dimensional memory spaces is divided into memory planes PI, P2,
...Pn, and each memory plane P allows the above-mentioned WI
As shown in Figure 2', each K (hard (however, KIN)
A two-dimensional X-Y plane is formed by arranging the X-Y planes, and actual data processing is performed on this two-dimensional X-Y plane. N at this time
(The arrangement of the memory planes PI-Pn of !l may be rectangular as well as square.

Therefore, when an address is given to the image memory 12, each DRAM element ME corresponding to a lower address therein is
A memory plane P configured by the same bits is selected.

Note that the lower address mentioned above is the 024M controller 16
and the same < 024M controller 16
The signal is input to the memory 12 by a control signal given to the memory 12.

13 in the figure is a memory selector, which selects one row (four DRAM elements in the X direction, C54 bits) or one column (four (m) in the Y direction) in one memory plane P selected as described above. DRAM element (ie, 4 bits) is selected.

Specifically, when an address is given to the memory selector 13, the row designation or column designation in the address is
The select signal specifies the row or column address (
(hereinafter referred to as the upper address), and if a row is specified, I? AS signal to DRA of that row? '
Is the CAS signal sent to all DRAs only to the child ME? If a column is specified, the CAS signal is applied only to the DRAFI element ME of that column, and the RAS signal is applied to all DRAM elements.
Give to Rakuko ME. As a result, one row in the X direction or Y
The above-described processing of the memory selector 13, in which only one column in the direction is selected or readable (enabled), is also controlled by a control signal in the same manner as the DRAM controller 16.

The refresh request circuit 17 is a circuit that refreshes each DRAM element ME that constitutes the memory 12. Since DRAM performs storage depending on whether or not charge is accumulated, the storage contents are periodically read out and rewritten (refreshed) to prevent destruction of the storage contents due to leakage current.

Therefore, the refresh request circuit 17
AM element ME? By applying the As signal, the above-mentioned refresh is performed. However, if the refresh is performed while the access to memo January 2 is being performed,
RA only to the DRAM element FIH that is being accessed
S signal is given to perform refresh, and other DRA
M-element M-element refreshing will not be performed, and their storage contents will be destroyed.

In order to avoid such a situation, the refresh request circuit 17 periodically generates a refresh request signal, and if the memory 12 is not accessed at the time the refresh request circuit generates the refresh request signal, the refresh request signal is immediately generated. DRA? + output to the 024M controller 16, and if an access is being performed, immediately output a refresh request signal to the 024M controller 16 after the access is completed, and the memory 1
Each of the two DRAMs is configured to refresh the fi-child ME.

In the figure, reference numerals 14 and 15 indicate data converters, and the data converter 14 for data input is used when writing data to the image memory 12, and the data converter 1515 for data output is used when reading data.

5 is a circuit diagram showing the connection state between this data converter 14, 15 and each DRAM element MC5 in the image memory 12. 16 oRAMffi child ME 1-1'1E
Reference numeral 16 denotes four DRAM elements each arranged in a diagonal direction (in this embodiment, diagonal direction, ie, 45° direction) on the image memo IJ12. l! 1~HE4, ME5~ME8, ME
9～? One set each of 1E12 and ME13 to ME16 is connected to four lines 081 to 084 of the data bus, respectively. That is, the DRAM fi child MEI.

MB2. MEIL, MgI2 on line 081, DRA
M element? IE2゜MB5. MI! 12. MB15 is on line 0112, DRAF + R child ME3゜MEN, MB
2. MB16 is on line DB3, [) RAMi child? 1
24. l'lE7゜MEIO, MgI2 is line DB4
are connected to the lines DB1. DB2.083 and DB4 are the first .083 and DB4 of the input data converter 14. 2nd, 3rd
and a fourth output terminal OfI.

OT2. OT3 and OT4 and output data converter 15
1st, 2nd. Third and fourth input terminals 1.1 and 2.
Wj are connected to fT3 and fT4, respectively.

The input data converter 14 receives a data signal input from an input terminal ITI or the like. It is configured to be shifted by the number of bits corresponding to the upper address of the address and output from output terminals 0 and 1, etc. That is, DRAI'! of the image memory 12 according to the upper address! When the third row or third column (in this embodiment, a positive integer of j≦4) of the array of elements Mε is specified, the data converter 14 inputs each input terminal Iτi (i・1, 2.3 or 4) is shifted by j-1 bits to each output terminal OTi.
It shifts to +j-+ and comes out.

Specifically, when the data signal input from the input terminal IT1 (or IT2.rT3.IT4) of the input data converter 14 is specified by the upper address, The output terminal 0T1 (or
OT2. It is output from OT3, 0T4). This allows input terminal ITI (or 112.IT3.IT4)
The data signal input from the first row DRAM element M element (or MB2.MB2゜?IE4) or the first
column DRAM element MHI (or.?'l[!5.M
E9゜MB13) respectively. Further, for example, when the second row or second column is designated by the upper address, the data is shifted one bit at a time and output from the output terminal 0T2 (or 0τ3, 04.0T1). This allows input terminal ITI (or 112.1-3.IT
The data signal input from 4) is sent to the DRAM element MR5 (or MB2゜1'lE7.l'1E8) in the second row or 0RAPI Rakuko1'1E2 (or MB2゜MEIO, MB14) in the second column. Each is input.

On the other hand, the output data converter 15 converts the input data l\! The input data converter 14 performs a similar shift, but the direction of the shift is opposite to that of the input data converter 14. That is, when the first row or third column is specified by the upper address in the input data converter 14, the input data signal is shifted by j-1 bits, but the output data converter 15 shifts the input data signal by -(j - 1) It is configured to shift bits.

The operation of the apparatus configured as described above and used to implement the method of the present invention is as follows.

For example, the first memory plane P1 of the image memory 12
When data is written to the first line of the image memo 2 and memory selector 13, the address that specifies
given to. Among these addresses, the lower address "lo" given to the N-image memo January 2 sets the first bit of each of the 16 DRAM elements MEI to ME16 that make up the image memory 12 into a state in which data can be loaded (enabled). Become.

At the same time, an upper address is given to the memory selector 13 and the input data converter 14.

This upper address is composed of an X-Y select signal that specifies the X direction (row) and a code signal that specifies the first row or first column. The CAS signal is sent to all DRAM elements ME.
In addition, each DR of the first row is
A RAS signal is applied to AM elements MEI to ME4. As a result, the four DRAFI elements MH elements Mg2 arranged in the first row of the If image memory 12 are placed in a writable state.

On the other hand, the data converter 14 has input terminals ITI, IT2.
The four data signals input from each of IT3 and IT4 are not shifted according to the code signal of the upper address, but in other words, they are shifted 0 (.J-1.1-1) times to each line DB1. of the data bus. DB2. DB3.
Output to each of 0B4.

The first (or second) input data converter 14
．． Third. 4th) input terminal rT1 (or IT2.I
The data signal input from T3゜IT4) is output from the first (or 1st, 2nd, 3rd, or 4th) output terminal 0-1 (or OT2, OT3, 0T4), and is output from the first DRAFI element MEI (or gate) of the first row, first (or second, third, fourth) The first row of the first memory plane Pl is accessed by 0 or more input to E2.FIε3.?IE4).

Next, when data is loaded into the second row of the first memory plane P1, the DRAM element M
The first bits of E1-11E16 are enabled for data writing, and the input data converter 14 is set to the second bit.
Depending on the upper address that specifies the row, its input terminal ■τ1
．． IT2. IT3. The four data signals input from each IT4 are shifted by j-1=2-1 bits, that is, 1 bit, and output to the output terminals OT2. OT3. Output from each of 4.0 and 1.

Therefore, the first (or second,
Third. 4th) input terminal rT1 (or IT2.IT
3゜IT4) The data signal input from the second (or
@3゜4th. 1st) output terminal 0T2 (or OT3.
0?4.0τl) and is output from the second (
Or 3rd and 4th. 1st) line DB2 (or [
lB3. DRAM element hε1 (or MB
2. MB2. Mg2).

As a result of the above, the second row of the first memory plane P1 is accessed.

Conversely, when the data written in the image memory 12 is read out, the output data converter 15 performs a shift in the opposite direction to the data writing described above and outputs the data.

That is, for example, when the data written in the second row of the first memory plane P1 is written one after another, the first row of each DRIIIM element ME is The bits are made readable, and the four DRAM elements in the second row are selected according to the upper address given to the memory selector 13. IE5 to ME8 become readable.

Then, the memory element ME5 (or MB2. Mg2. MB8) in the second row and first (or second, third, fourth) column
) is stored on the second (or
3rd゜4th. 1st) line DB2 (or DB3
．． DB4. Data converter 1 for output via DBI)
5 input terminal IT2 (or IT3.IT4.rT
l). As mentioned above, since the output data converter 15 performs a shift in the opposite direction to that of the input data converter 14, the data input to the input terminal l72 (or IT3.IT4.ITI) of the output data converter 15 DRA
Data from FI element ME5 (or MB2. Gate E7. Gate E8) is sent to output terminal 0T1 (or OT2. OT3).
．． 0T4).

Although the description is omitted, access to each row (Y direction) on each memory plane P is also possible in the same way as access to each column described above.

Access to the memo 2 made up of the DRAM element ME is performed as described above, during which time the refresh request circuit 17 generates a refresh request signal at a constant cycle. Further, 'The refresh request circuit 17 detects the timing at which data is written to or read from the memory 12, that is, access is performed, using a control signal.

As a result, if the memory 12 is not being accessed at the time the refresh request signal is generated, the refresh request signal is immediately sent to the DR.
AMRAM controller 16 and each DRAM of memory 12
If the A child ME is refreshed and the memory 12 is being accessed at the time the refresh request signal is generated, the refresh request signal is output to the RAM controller 16 when the access is completed. Then, each DRAM element ME of the memory 12 is refreshed.

Since each DRAM element ME of the memory 12 is refreshed in this manner, the stored contents of the memory 12 are not destroyed.

〔effect〕

As described in detail above, according to the present invention, an X or Y Data stored in multiple bits can be read and data stored in multiple bits can be read from any direction with a single access.

It becomes possible to write the evening. Therefore, if the present invention is applied to an image file system or the like that requires a large capacity memory, the image processing speed will be significantly improved compared to the conventional system. Further, since each memory plane obtained by dividing the two-dimensional memory configuration is configured as a three-dimensional memory space, the number of memory elements can be reduced considerably by using a large-capacity DIIAM element. Along with this, each D such as a selector for selecting the arrangement direction of memory elements or an address converter, etc.
The frequency IF device associated with the RAM device may also be reduced. Furthermore, since the memory configuration is such that a plurality of memory planes are arranged on two-dimensional planes, the memory configuration is not limited to a square shape. Since refresh is performed, the contents of the memory are not destroyed.

In the above embodiment, 1 bit x N DRAM elements are arranged in a square shape of L x M - 4 x 4, but if L and M are different numbers and arranged in a rectangular shape, or It goes without saying that even in the case of a number, it is possible to access the memory, that is, to import and read data, by the same processing as in the embodiment described above.

[Brief explanation of the drawing]

The drawings show embodiments of the present invention; FIG. 1 is a schematic diagram showing the configuration of a memory, FIG. 2 is a schematic diagram showing the arrangement of memory planes, and FIG. 3 is a schematic diagram showing an arrangement of memory planes. FIG. 4 is a schematic diagram showing the arrangement of memory elements, and FIG. 5 is a schematic diagram showing the state of connection of each memory element by a data bus. 1... Two-dimensional memory space 2... Between X-Y two-dimensional dimension 12... Image memory 13... Memory selector 14, 15... Data converter ME... DRAF'I element P...・Memory plane patent Applicant: Sanyo Electric Co., Ltd. Representative Patent attorney: Noboru Kono') &? [21 '82 Figure input - No. 312] Kuzu 4 Figure procedure amendment f (self-Q) December 28, 11759

Claims (1)

[Claims] A 1, 1 bit x N DRAM (dynamic random access memory) element can be
A three-dimensional memory space of L×M×N bits is formed by arranging M pieces in a direction (Y direction) orthogonal to the X direction, and the bits at the same address in each DRAM element form a three-dimensional memory space. A memory configuration in which memory planes consisting of two-dimensional memory spaces of L×M bits formed in N pieces in the bit arrangement direction of the DRAM elements in the memory space are arranged in a two-dimensional space, and the X-Y plane of the three-dimensional memory space Each DRAM element arranged diagonally above is connected to the same line of the data bus, each memory plane is specified by specifying the bit of each DRAM element using the lower address, and the row is specified using the upper address. If all DRAM
A CAS (column address strobe) signal is applied to each element, and a RAS (row address strobe) signal is applied to each DRAM element in a specified row.
If a column is specified, a RAS signal is applied to all DRAM elements, and a CAS signal is applied to each DRAM element in the specified column, thereby specifying a specified row or column in each memory plane. are respectively enabled, the input/output data is shifted by a predetermined number of bits according to the upper address, data is written and read, and the RAS signal or CAS signal is sent to all DRAM elements while no access is being performed. Each DRA by giving
A memory access method characterized by refreshing M elements.