JP7427972B2 - Semiconductor storage device, controller, and method - Google Patents

Description

The present disclosure relates to a semiconductor memory device, a controller, and a method.

For example, in neural network calculations, for data having a multidimensional structure, fast and efficient access to adjacent data in each dimension direction is required. By rearranging multidimensionally structured data into one dimension and arranging it on word lines, data access in at least a predetermined dimensional direction can be made more efficient (see, for example, Patent Document 1).

Japanese Patent Application Publication No. 2009-048753

However, in the configuration disclosed in Patent Document 1, the word configuration of data that can be read by one address specification is determined in advance, and it is difficult to realize efficient access to all dimensional data. .

Therefore, the present disclosure proposes a semiconductor storage device, a controller, and a method that enable efficient access to a plurality of pieces of data that are adjacent to each other in any dimensional direction.

A semiconductor memory device according to the present disclosure includes a memory cell array in which data having a multidimensional structure is arranged one-dimensionally on a word line, and a plurality of data adjacent in any dimension direction from the memory cell array in one address. a controller capable of reading by designation; the controller includes an address generation circuit that generates an address on the word line that is a starting point for a read operation; and a controller that performs a predetermined operation on the generated address to determine the read target. It includes an arithmetic circuit that generates addresses on the word line of data adjacent in the dimension direction, and a signal generation circuit that generates a signal including a value used for the arithmetic operation.

1 is a diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present disclosure. 1 is a diagram showing a bank configuration of a semiconductor memory device according to a first embodiment of the present disclosure; FIG. 1 is a diagram illustrating an example of a structure of data to be stored in a semiconductor memory device according to a first embodiment of the present disclosure; FIG. FIG. 2 is a diagram illustrating a correspondence relationship in the arrangement order of data to be stored in the semiconductor memory device according to the first embodiment of the present disclosure. FIG. 3 is a diagram illustrating a read operation of a plurality of pieces of data adjacent in the X-axis direction in the semiconductor memory device according to the first embodiment of the present disclosure. FIG. 3 is a diagram illustrating a read operation of a plurality of pieces of data adjacent in the Y-axis direction in the semiconductor memory device according to the first embodiment of the present disclosure. FIG. 2 is a flow diagram illustrating an example of a read processing procedure in the semiconductor memory device according to Embodiment 1 of the present disclosure. FIG. 7 is a diagram illustrating a read operation of a plurality of data adjacent in the Y-axis direction in a semiconductor memory device according to a comparative example. FIG. 7 is a diagram showing a correspondence relationship in the order of arrangement of data to be stored in a semiconductor memory device according to a second embodiment of the present disclosure. FIG. 7 is a diagram illustrating a read operation of a plurality of data adjacent in the X-axis direction in a semiconductor memory device according to a second embodiment of the present disclosure. FIG. 7 is a diagram illustrating a read operation of a plurality of pieces of data adjacent in the Y-axis direction in a semiconductor memory device according to a second embodiment of the present disclosure. FIG. 7 is a diagram illustrating a read operation of a plurality of data adjacent in the Z-axis direction in a semiconductor memory device according to a second embodiment of the present disclosure. FIG. 7 is a diagram showing the arrangement order of data to be stored in a semiconductor memory device according to another embodiment of the present disclosure.

Embodiments of the present disclosure will be described in detail below based on the drawings. In addition, in each of the following embodiments, the same portions are given the same reference numerals and redundant explanations will be omitted.

[Embodiment 1]
Embodiment 1 will be described below with reference to the drawings.

(Example of configuration of semiconductor memory device)
FIG. 1 is a diagram showing the configuration of a semiconductor memory device 1 according to Embodiment 1 of the present disclosure. The semiconductor memory device 1 of the first embodiment is, for example, MRAM (Magnetresistive Random Access Memory), SRAM (Static RAM), DRAM (Dynamic RAM), or the like.

As shown in FIG. 1, the semiconductor memory device 1 includes a plurality of banks 100. Each bank 100 includes a memory cell array 101 in which a plurality of semiconductor memory elements are arranged, for example, in a two-dimensional array.

Here, the plurality of banks 100 are parallel operation elements that can operate in parallel with each other. That is, while a predetermined semiconductor memory element in the memory cell array 101 included in one bank 100 is in operation, a predetermined semiconductor memory element in the memory cell array 101 included in another bank 100 can be operated.

When the semiconductor memory device 1 is an MRAM, each semiconductor memory element in the memory cell array 101 has a magnetic tunnel junction and stores data by changing the state of magnetization. Further, when the semiconductor memory device 1 is an SRAM, the semiconductor memory element in the memory cell array 101 is configured from a flip-flop circuit that combines a plurality of transistors, and stores data by holding charge. Further, when the semiconductor memory device 1 is a DRAM, the semiconductor memory elements in the memory cell array 101 store data by holding charge in a capacitor.

In the following description, each semiconductor storage element in the memory cell array 101 is assumed to be an SLC (Single Level Cell) capable of storing 1-bit data. However, the semiconductor storage elements in the memory cell array 101 may be MLCs (Multi Level Cells) capable of storing multi-bit data of two or more bits.

FIG. 2 is a diagram showing the configuration of the bank 100 of the semiconductor memory device 1 according to the first embodiment of the present disclosure. As shown in FIG. 2, one bank 100 includes the above-described memory cell array 101 and memory controller 110.

The memory cell array 101 includes, for example, a plurality of bit lines BL extending in parallel to each other in a direction perpendicular to the plane of the paper. Furthermore, the memory cell array 101 includes a plurality of word lines WL that extend in parallel to each other, for example, in the horizontal direction of the paper. Each semiconductor memory element MC is connected to any bit line BL and any word line WL. That is, semiconductor memory elements MC are arranged in an array at each intersection of the bit line BL and word line WL.

The memory controller 110 includes a control section 111, a column decoder (CA Dec) 121, a row decoder (RA Dec) 122, a sense amplifier/write amplifier (SA/WA) 123, and adders (MUX) 131 to 134.

The control unit 111 controls one bank 100 as a whole, including the semiconductor storage elements MC in the memory cell array 101, by controlling the operations of each of the above components in the memory controller 110. The control unit 111 includes an address generation circuit 111a and a signal generation circuit 111b.

When writing and reading data to and from a predetermined semiconductor memory element MC in the memory cell array 101, the address generation circuit 111a generates a column address CA and a row address of the semiconductor memory element MC that is the starting point of the operation among the semiconductor memory elements MC to be operated. Generate address RA. Column address CA is an address that specifies a bit line BL connected to a predetermined semiconductor memory element MC, and is transferred to column decoder 121. Row address RA is an address that specifies word line WL connected to a predetermined semiconductor memory element MC, and is transferred to row decoder 122.

The signal generation circuit 111b generates a signal ai for specifying the remaining semiconductor memory elements MC, excluding the semiconductor memory element MC serving as the starting point, among the semiconductor memory elements MC to be operated. The generated signal ai is added to the column address CA and transferred to the column decoder 121.

The column decoder 121 identifies the corresponding bit line BL based on the column address CA acquired from the control unit 111. Then, the signal ai is transferred to the adders 131 to 134 together with the address information addr of the specified bit line BL.

The row decoder 122 selects a corresponding word line WL based on the row address RA acquired from the control unit 111, and drives the selected word line WL by, for example, applying a predetermined voltage.

The sense amplifier/write amplifier 123 drives a predetermined bit line BL by, for example, applying a predetermined voltage. As a result, the semiconductor memory element MC connected to both the drive bit line BL and the above-mentioned drive word line WL is driven. At the time of writing, data is written to the semiconductor memory element MC. Further, at the time of reading, the data of the semiconductor memory element MC is read to the sense amplifier/write amplifier 123.

Adders 131 to 134 as arithmetic circuits generate addresses of bit lines BL connected to semiconductor memory elements MC to be operated, based on address information addr and signal ai acquired from column decoder 121. Each of the adders 131 to 134 has a configuration in which a plurality of multiplexers are combined, for example, and adds a given predetermined value to the original numerical value. Here, the original value is, for example, a number indicating the bit line BL included in the address information addr, and the predetermined value to be added is included in, for example, the signal ai.

Address information addr is transferred to the first adder 131, and signal ai is not transferred. Therefore, the adder 131 uses the address included in the address information addr as the address of the bit line BL connected to the semiconductor memory element MC to be operated.

The signal ai is applied once to the second adder 132 together with the address information addr. Therefore, the adder 132 adds the value included in the signal ai once to the address included in the address information addr to generate the address of the bit line BL connected to the semiconductor memory element MC to be operated.

The third adder 133 is supplied with the signal ai twice along with the address information addr. Therefore, the adder 133 adds the value included in the signal ai to the address included in the address information addr twice to generate the address of the bit line BL connected to the semiconductor memory element MC to be operated.

The signal ai is applied to the fourth adder 134 three times along with the address information addr. Therefore, the adder 134 adds the value included in the signal ai to the address included in the address information addr three times to generate the address of the bit line BL connected to the semiconductor memory element MC to be operated.

Further, the adders 131 to 134 complete the operation for the semiconductor memory element MC corresponding to the address of the bit line BL generated by the calculation. That is, at the time of writing, data is written to the semiconductor memory element MC connected to the bit line BL corresponding to the address generated by the calculation among all the semiconductor memory elements MC on the drive word line WL. In addition, at the time of reading, the data of all the semiconductor memory elements MC on the drive word line WL are read out to the sense amplifier/write amplifier 123, and among them, the data is connected to the bit line BL corresponding to the address generated by the calculation. Data from semiconductor memory element MC is acquired by each adder 131-134. Adders 131 to 134 transfer the acquired data to control section 111.

Incidentally, the addition of a predetermined value to the bit line number is repeated as many times as the number of bits that the semiconductor memory device can process at one time. Furthermore, when reading data, data read destinations are required for the number of bits that can be processed at one time. Therefore, the same number of adders as the number of bits that can be processed at one time are required. In the example of FIG. 2, the semiconductor memory device 1 of the first embodiment includes four adders 131 to 134. That is, the semiconductor memory device 1 of the first embodiment has a 4-bit word structure and can process 4-bit data at a time.

In addition to the above-described configuration, the memory controller 110 may also include a data array conversion circuit (not shown) that rearranges the individual data read out by the adders 131 to 134, for example.

(Example of data structure of semiconductor storage device)
Next, using FIGS. 3 and 4, the structure that data to be stored in the semiconductor memory device 1 of the first embodiment originally has and the data structure actually stored in the semiconductor memory device 1 will be explained. The correspondence relationship with .

As explained below, data to be stored in the semiconductor memory device 1 has, for example, a multidimensional structure. On the other hand, when stored in the semiconductor memory device 1, these data have a structure in which they are arranged one-dimensionally on one word line, for example.

FIG. 3 is a diagram illustrating an example of a structure of data to be stored in the semiconductor memory device 1 according to the first embodiment of the present disclosure. Note that in the subsequent figures, including FIG. 3, one square represents one bit of data.

As shown in FIG. 3, the original data to be stored has a two-dimensional structure in which individual pieces of data are arranged in a matrix along, for example, the X-axis and the Y-axis. In this way, for data with a multidimensional structure, it is possible to appropriately access multiple pieces of data adjacent in any dimension direction in one read operation, that is, with one address specification. desirable.

That is, for example, if the data has the two-dimensional structure shown in FIG. For example, data surrounded by a solid line in Figure 3) and 4-bit data aligned in the Y-axis direction (for example, data surrounded by a broken line in Figure 3) can be arbitrarily specified and read out as appropriate. is desired. Therefore, as a prerequisite for enabling such a read operation, in the semiconductor memory device 1, data arranged on one word line has a structure as shown in FIG. 4, for example.

FIG. 4 is a diagram illustrating the correspondence of the arrangement order of data to be stored in the semiconductor memory device 1 according to the first embodiment of the present disclosure. The upper part of FIG. 4 shows the original arrangement of the data to be stored, and the lower part of FIG. 4 shows the arrangement of the data stored in the semiconductor memory device 1.

As shown in the lower part of FIG. 4, in the memory cell array 101 of the semiconductor memory device 1, the data of the above two-dimensional structure is distributed to areas from area A to area D allocated to word lines, and is distributed to each corresponding position. The data is stored in a semiconductor memory element located in the area.

Note that the X and Y numbers shown in the lower part of FIG. 4 represent the arrangement positions of the original data on the X axis and the Y axis. The data structure shown in the upper part of FIG. 4 is similar to that shown in FIG. Codes A to D corresponding to ~D were assigned.

According to the example of FIG. 4, for example, 4-bit data adjacent in the X-axis direction and 4-bit data adjacent in the Y-axis direction are equally distributed to areas A to D, respectively. In each area, the same address is given to data arranged at the same position. In other words, data at the same position in each area have the same address on the word line. Data at the same position in each region means data arranged in the same order on word lines in each region. The address on the word line is represented by, for example, the number of the bit line that intersects with the word line.

For example, data corresponding to the third bit line among the bit lines intersecting the word line in area A, that is, data corresponding to the third bit line arranged on the word line, and data corresponding to the third bit line intersecting the word line in area B. Among them, the data corresponding to the third bit line, that is, the data placed third on the word line, is the data placed at the same position in each area A and B, and the address on the word line is are identical to each other.

By arranging each piece of data on the word line as described above, by extracting predetermined data one by one from each of areas A to D, 4-bit data adjacent to each other in any dimension direction can be obtained. Can be done.

Here, 4 bits of data adjacent in any dimension are arranged on the word line at a predetermined period. More specifically, in these data, the addresses on the word lines in areas A to D, that is, the bit line numbers, shift at a predetermined period. To obtain adjacent data in any dimensional direction, when extracting data from each of areas A to D, start from the bit line number corresponding to the 1st bit data, and from that number in each area. It is sufficient to extract data corresponding to bit line numbers shifted by a predetermined period.

In the semiconductor memory device 1 of the first embodiment, the above-described adders 131 to 134 correspond to the areas A to D, respectively, and acquire data read from within the area corresponding to itself.

At this time, the address information addr given to each of the adders 131 to 134 indicates the address on the word line that is the starting point for acquiring data in each area, that is, the bit line number. Then, the signal ai is given to the other adders 132 to 134 except for the first adder 131. The signal ai includes a numerical value to be added to the bit line number serving as the starting point of data acquisition, that is, the period of deviation from the bit line number serving as the starting point.

For example, if the bit line number that is the starting point for data acquisition indicates the third bit line that intersects with the word line in each area, the adder 131 selects one of the data read from area A. Data corresponding to the third bit line of area A is acquired.

Further, the adder 132 obtains, from among the data read from area B, data corresponding to the bit line numbered by adding the number included in the signal ai to the number of the third bit line in area B. Further, the adder 133 adds data corresponding to the bit line number obtained by adding the numerical value included in the signal ai to the third bit line number of the area C twice, out of the data read from the area C. get. Further, the adder 134 adds data, out of the data read from area D, to the bit line numbered by adding the numerical value included in the signal ai to the third bit line number in area D three times. get.

(Example of read operation of semiconductor memory device)
Next, a specific example of the read operation in the semiconductor memory device 1 will be described using FIGS. 5 and 6. Note that in the following description, predetermined data may be indicated by numbers X and Y. These numbers indicate the arrangement positions on the X-axis and Y-axis in the original two-dimensional structure of the data. Note that these numbers do not represent addresses on the word lines.

FIG. 5 is a diagram showing a read operation of a plurality of data adjacent in the X-axis direction in the semiconductor memory device 1 according to the first embodiment of the present disclosure. In FIG. 5, it is assumed that the bit line number that is the starting point of the read operation in each area is the first bit line. In that case, the following operations are performed prior to the operations of adders 131 to 134 shown in FIG.

The address generation circuit 111a of the control unit 111 generates a row address indicating a word line connected to the semiconductor storage element to be read out, and transfers it to the row decoder 122. The row decoder 122 selects and drives the word line indicated by the row address.

Further, the address generation circuit 111a generates a column address indicating the bit line that is the starting point of the read operation.

The signal generation circuit 111b of the control unit 111 generates a signal ai including a numerical value to be added to the bit line number that is the starting point of the read operation, based on the dimensional direction in which the plurality of data to be read are adjacent. In FIG. 5, the plurality of data to be read are adjacent data in the X-axis direction. For data adjacent in the X-axis direction, no deviation occurs in the addresses on the word lines in each area. In other words, the period of deviation from the bit line number serving as the starting point is zero, and the added value included in the signal ai is zero.

The control unit 111 transfers the generated column address and signal ai to the column decoder 121.

On the other hand, the sense amplifier/write amplifier 123 drives a predetermined bit line. The bit lines driven here may be substantially all the bit lines in the memory cell array 101. As a result, the sense amplifier/write amplifier 123 reads all data on the drive word line selected by the row decoder 122.

Based on the column address obtained from the control unit 111, the column decoder 121 generates address information addr that includes a bit line number that designates the first bit line among the bit lines that intersect with the word line in each area. Column decoder 121 adds signal ai to the generated address information addr and transfers it to adders 131-134.

After this, the operations of adders 131 to 134 shown in FIG. 5 are executed.

As shown in FIG. 5, the adder 131 outputs data (X, Y)=(0,0) to (3,3) read from area A based on the address information addr acquired from the column decoder 121. Among them, data (X, Y)=(0,0) corresponding to the first bit line of area A is acquired.

Adder 132 generates an address on the word line of data to be read from area B based on address information addr acquired from column decoder 121 and signal ai. Here, since the addition value zero included in the signal ai is added to the number indicating the first bit line of area B, the bit line number corresponding to the data to be read from area B is the number of the first bit line. The number remains the same. The adder 132 adds data (X, Y) corresponding to the first bit line of area B out of the data (X, Y)=(0,0) to (3,3) read from area B. Get = (0,0).

Adder 133 generates an address on the word line of data to be read from area C based on address information addr acquired from column decoder 121 and signal ai. Here, since the addition value zero included in signal ai is added twice to the number indicating the first bit line of area C, the bit line number corresponding to the data to be read from area C is the first bit line number. The bit line number remains the same. The adder 133 adds data (X, Y) corresponding to the first bit line of area C among the data (X, Y)=(0,0) to (3,3) read from area C. Get = (0,0).

The adder 134 generates the address on the word line of the data to be read from the area D based on the address information addr obtained from the column decoder 121 and the signal ai. Here, since the addition value zero included in the signal ai is added three times to the number indicating the first bit line of area D, the bit line number corresponding to the data to be read from area D is the first bit line number. The bit line number remains the same. The adder 134 selects the data (X, Y) corresponding to the first bit line of the area D from among the data (X, Y)=(0,0) to (3,3) read from the area D. Get = (0,0).

As described above, 4-bit data corresponding to (X, Y)=(0,0), (0,0), (0,0), (0,0) is obtained by the adders 131-134. According to the original data array shown in the upper right corner of FIG. 5, it can be seen that these data are 4-bit data adjacent to each other in the X-axis direction. Adders 131 to 134 transfer these data to control section 111.

FIG. 6 is a diagram showing a read operation of a plurality of pieces of data adjacent in the Y-axis direction in the semiconductor memory device 1 according to the first embodiment of the present disclosure.

Also in FIG. 6, it is assumed that the bit line number that is the starting point of the read operation in each area is the first bit line. In that case, operations similar to those described above are performed prior to the operations of adders 131 to 134 shown in FIG.

However, in FIG. 6, the data to be read is data adjacent to each other in the Y-axis direction. Adjacent data in the Y-axis direction has a cycle in which addresses on word lines in each region are shifted by four. Therefore, the signal generation circuit 111b generates a signal ai that includes 4 as the addition value to the bit line number that is the starting point of the read operation.

As shown in FIG. 6, the adder 131 outputs data (X, Y)=(0,0) to (3,3) read from area A based on the address information addr acquired from the column decoder 121. Among them, data (X, Y)=(0,0) corresponding to the first bit line of area A is acquired.

The adder 132 adds the addition value 4 included in the signal ai to the number indicating the first bit line of the area B based on the address information addr acquired from the column decoder 121 and the signal ai, and adds the addition value 4 included in the signal ai to the number indicating the first bit line of the area B. The number of the fifth bit line is obtained as the bit line number corresponding to the data to be read. The adder 132 adds data (X, Y) corresponding to the fifth bit line of area B among the data (X, Y)=(0,0) to (3,3) read from area B. Get = (0, 1).

The adder 133 adds the addition value 4 included in the signal ai twice to the number indicating the first bit line of the area C based on the address information addr and the signal ai obtained from the column decoder 121, The number of the ninth bit line is obtained as the bit line number corresponding to the data to be read from area C. The adder 133 adds data (X, Y) corresponding to the 9th bit line of area C among the data (X, Y)=(0,0) to (3,3) read from area C. Get = (0, 2).

The adder 134 adds the addition value 4 included in the signal ai three times to the number indicating the first bit line of the area D based on the address information addr and the signal ai obtained from the column decoder 121, As the bit line number corresponding to the data to be read from area D, the number of the 13th bit line is obtained. The adder 134 adds data (X, Y) corresponding to the 13th bit line of the area D from among the data (X, Y)=(0,0) to (3,3) read from the area D. Get = (0, 3).

As described above, 4-bit data corresponding to (X, Y)=(0,0), (0,1), (0,2), (0,3) is obtained by the adders 131-134. According to the original data array shown in the upper right corner of FIG. 6, it can be seen that these data are 4-bit data adjacent in the Y-axis direction. Adders 131 to 134 transfer these data to control section 111.

Note that depending on the data allocation method, the order in which the adders 131 to 134 read out the data may differ from the original data arrangement. In such a case, the order of the read data may be rearranged using the aforementioned data array conversion circuit (not shown) or the like so that the original data array order is achieved.

(Example of read processing of semiconductor storage device)
Next, an example of read processing in the semiconductor memory device 1 will be described using FIG. 7. FIG. 7 is a flow diagram illustrating an example of a read processing procedure in the semiconductor memory device 1 according to the first embodiment of the present disclosure.

As shown in FIG. 7, the address generation circuit 111a of the control unit 111 generates a column address and a row address of data that serve as a starting point for a read operation (step S101).

Further, the signal generation circuit 111b of the control unit 111 generates a signal ai based on the dimensional direction of adjacent data to be read (step S102). For example, if the original data has the two-dimensional structure shown in FIG. 4 described above, and the dimensional direction is the X-axis direction, a signal ai containing zero in the added value is generated. When the dimensional direction is the Y-axis direction, a signal ai containing 4 as an added value is generated.

The control unit 111 transfers the generated column address and signal ai to the column decoder 121. Furthermore, the control unit 111 transfers the generated row address to the row decoder 122 (step S103).

Based on the acquired row address, the row decoder 122 selects and drives the corresponding word line (step S104).

The sense amplifier/write amplifier 123 drives the bit lines (actually, all bit lines in the memory cell array 101) that intersect with the word line selected by the row decoder 122, and reads out all data on the selected word line (step S105). ).

The column decoder 121 generates address information addr including a bit line number, which is an address on the selected word line, based on the obtained column address. The column decoder 121 transfers the generated address information addr to the adders 131 to 134 together with the signal ai (step S106).

The first adder 131 acquires data corresponding to a predetermined bit line number in area A as the first bit data based on the acquired address information addr (step S107).

The (n+1)th adder adds the addition value included in the signal ai to the bit line number included in the acquired address information addr n times to obtain the (n+1)th data word that it should acquire. A bit line number, which is an address on the line, is generated (step S108).

The (n+1)th adder acquires data corresponding to the obtained bit line number from the area corresponding to itself as (n+1)th bit data (step S109).

If the (n+1)th bit data is not the last data to be acquired (step S110: No), the number n is incremented by one (step S111), and the processes of steps S108 to S109 are repeated.

If the (n+1)th bit data is the last data to be acquired (step S110: Yes), the control unit 111 ends the process.

With the above steps, the read processing in the semiconductor memory device 1 is completed.

(Comparative example)
Next, a semiconductor memory device as a comparative example will be described using FIG. 8. FIG. 8 is a diagram illustrating a read operation of a plurality of data adjacent in the Y-axis direction in a semiconductor memory device according to a comparative example.

In the semiconductor memory device of the comparative example, for example, 4 bits of data adjacent in the X-axis direction have the same address. As a result, in the semiconductor memory device of the comparative example, 4-bit data adjacent in the X-axis direction (for example, (X, Y)=(0, 0), etc.) can be read by one address designation. Note that the operation of reading multiple pieces of data with one address specification is also referred to as a burst operation.

However, this means that in the semiconductor memory device of the comparative example, the word configuration of readable adjacent data is fixed in a predetermined dimensional direction. Therefore, from the semiconductor memory device of the comparative example, for example, 4-bit data (X, Y) within the broken line frame adjacent in the Y-axis direction = (0, 0), (0, 1), (0, 2), If an attempt is made to read (0,3), the following processing as shown in FIG. 8 will be required.

That is, in order to read the 1st bit data (X, Y) = (0, 0), the first addressing is performed and the 4 bits adjacent in the X axis direction (X, Y) = (0 , 0).

In order to read the 2nd bit data (X, Y) = (0, 1), perform the second address specification and read the 4 bits of data (X, Y) = (0, 1) adjacent in the X-axis direction. ) is read out.

In order to read the 3rd bit data (X, Y) = (0, 2), address specification is performed for the third time, and 4 bits of data (X, Y) = (0, 2) adjacent in the X-axis direction are read. ) is read out.

In order to read the 4th bit data (X, Y) = (0, 3), address specification is performed for the 4th time, and 4 bits of data (X, Y) = (0, 3) adjacent in the X-axis direction are read. ) is read out.

As described above, 4-bit data adjacent to each other in the Y-axis direction can be obtained, but this requires four address designations, that is, processing for, for example, four clocks. Furthermore, in addition to the necessary 4 bits of data, even 12 bits of extra data are read out.

As described above, the semiconductor memory device of the comparative example may be inefficient in terms of time and power depending on the dimensional direction in which reading is desired.

According to the semiconductor memory device 1 of the first embodiment, the adders 131 to 134 generate addresses on word lines of data adjacent in the dimensional direction to be read. The signal generation circuit 111b of the control unit 111 generates a signal ai including a value necessary for generating the address. As a result, a plurality of pieces of data adjacent to each other in any dimensional direction can be read out with one address designation, that is, one clock process, for example. Further, it is possible to suppress the occurrence of wasteful accesses such as data other than the data to be read being read.

According to the semiconductor memory device 1 of the first embodiment, by having the above configuration, it can be suitably applied to, for example, a memory for storing input data, a memory for storing coefficients, etc. in calculations related to neural networks.

[Embodiment 2]
Embodiment 2 will be described below with reference to the drawings. In the second embodiment, processing of data having a three-dimensional structure will be described.

(Example of data structure of semiconductor storage device)
FIG. 9 is a diagram illustrating the correspondence of the arrangement order of data to be stored in the semiconductor memory device 1 according to the second embodiment of the present disclosure. The upper part of FIG. 9 shows the original arrangement of the data to be stored, the middle part of FIG. 9 shows the data to be stored in a raster arrangement, and the lower part of FIG. It shows the arrangement of data in a stored state.

As shown in the upper part of FIG. 9, in the second embodiment, the original data to be stored in the semiconductor memory device 1 has, for example, a three-dimensional structure. In the upper diagram of FIG. 9, each block constituting a cube representing three-dimensional data represents one bit of data. The numerical values shown in the figure indicate the arrangement positions of each data on the X-axis, Y-axis, and Z-axis. The symbols A to D attached to the individual blocks constituting the cube illustrate to which of the regions A to D on the word line of the semiconductor memory device 1 these data are distributed.

In the semiconductor storage device 1, even for data with such a three-dimensional structure, multiple pieces of data adjacent to each other in any dimension direction (X-axis direction, Y-axis direction, and Z-axis direction) can be batched with a single address specification. can be accessed. As a premise for such a read operation, these data can have a structure as shown in the lower part of FIG. 9, for example, while being stored in the semiconductor memory device 1.

The middle part of FIG. 9 shows the original data arranged in a raster pattern so that the correspondence between the original data arrangement and the data arrangement in the semiconductor memory device 1 can be easily understood. In other words, in the middle row of FIG. 9, each time data is arranged from data X=0 to data Each piece of data is arranged according to the following procedure:

As shown in the lower part of FIG. 9, 4-bit data adjacent in the X-axis direction, 4-bit data adjacent in the Y-axis direction, and 4-bit data adjacent in the Z-axis direction are all located in areas A to A. It will be distributed evenly to D. For example, the same address is assigned to data arranged at the same position in each area.

(Example of read operation of semiconductor memory device)
Next, a read operation in the semiconductor memory device 1 will be described using FIGS. 10 to 12. Note that in the following description, predetermined data may be indicated by X, Y, and Z numbers. These numbers indicate the arrangement positions on the X-axis, Y-axis, and Z-axis in the original three-dimensional structure of the data.

FIG. 10 is a diagram showing a read operation of a plurality of data adjacent in the X-axis direction in the semiconductor memory device 1 according to the second embodiment of the present disclosure. In FIG. 10, it is assumed that the bit line number that is the starting point of the read operation in each area is the first bit line.

Prior to the operation of the adders 131 to 134 shown in FIG. All data on a given word line is acquired.

Note that in FIG. 10, the data to be read is data adjacent to each other in the X-axis direction. For data adjacent in the X-axis direction, addresses on word lines do not change in each region. Therefore, the signal generation circuit 111b generates a signal ai that includes zero as an addition value to the bit line number that is the starting point of the read operation.

As shown in FIG. 10, the adder 131 reads data (X, Y, Z) = (0, 0, 0) ~ ( 3, 3, 3), data (X, Y, Z) = (0, 0, 0) corresponding to the first bit line in area A is acquired.

The adder 132 adds the addition value zero included in the signal ai to the number indicating the first bit line of the area B based on the address information addr and the signal ai acquired from the column decoder 121, and adds the addition value zero included in the signal ai to the number indicating the first bit line of the area B. The number of the first bit line is obtained as the bit line number corresponding to the data to be read. The adder 132 corresponds to the first bit line of area B among the data (X, Y, Z) = (0, 0, 0) to (3, 3, 3) read from area B. Obtain data (X, Y, Z) = (1, 0, 0).

The adder 133 adds the addition value zero included in the signal ai twice to the number indicating the first bit line of the area C based on the address information addr and the signal ai obtained from the column decoder 121, As the bit line number corresponding to the data to be read from area C, the number of the first bit line is obtained. The adder 133 corresponds to the first bit line of area C among the data (X, Y, Z) = (0, 0, 0) to (3, 3, 3) read from area C. Obtain data (X, Y, Z) = (2, 0, 0).

The adder 134 adds the addition value zero included in the signal ai three times to the number indicating the first bit line of the area D based on the address information addr and the signal ai obtained from the column decoder 121, As the bit line number corresponding to the data to be read from area D, the number of the first bit line is obtained. The adder 134 corresponds to the first bit line of the area D among the data (X, Y, Z) = (0, 0, 0) to (3, 3, 3) read from the area D. Obtain data (X, Y, Z) = (3, 0, 0).

With the above, the 4-bit data corresponding to (X, Y, Z) = (0, 0, 0), (1, 0, 0), (2, 0, 0), (3, 0, 0) is It is obtained by adders 131-134. Adders 131 to 134 transfer these data to control section 111.

In the upper right corner of FIG. 10, a cube representing the original data array is shown. In place of the symbols A to D in FIG. 9, the individual blocks constituting the cube are marked on the X-axis, Y-axis, and Z-axis to make it easier to understand the position of the data acquired as described above. A number indicating the sequence position of each data was attached. According to the upper right diagram of FIG. 10, it can be seen that the data acquired as described above is 4-bit data adjacent in the X-axis direction.

FIG. 11 is a diagram showing a read operation of a plurality of data adjacent in the Y-axis direction in the semiconductor memory device 1 according to the second embodiment of the present disclosure.

Also in FIG. 11, it is assumed that the bit line number that is the starting point of the read operation in each area is the first bit line. Prior to the operations of adders 131 to 134 shown in FIG. 11, operations similar to those described above are performed.

Note that in FIG. 11, the data to be read is data adjacent to each other in the Y-axis direction. Data adjacent to each other in the Y-axis direction have a period in which addresses on word lines in each region are shifted by one. Therefore, the signal generation circuit 111b generates a signal ai that includes 1 as an addition value to the bit line number that is the starting point of the read operation.

As shown in FIG. 11, the adder 131 reads data (X, Y, Z) = (0, 0, 0) ~ ( 3, 3, 3), data (X, Y, Z) = (0, 0, 0) corresponding to the first bit line in area A is acquired.

The adder 132 adds the addition value 1 included in the signal ai to the number indicating the first bit line of the area B based on the address information addr and the signal ai acquired from the column decoder 121, and adds the addition value 1 included in the signal ai to the number indicating the first bit line of the area B. The second bit line number is obtained as the bit line number corresponding to the data to be read. The adder 132 corresponds to the second bit line of area B among the data (X, Y, Z) = (0, 0, 0) to (3, 3, 3) read from area B. Obtain data (X, Y, Z) = (0, 1, 0).

The adder 133 adds the addition value 1 included in the signal ai twice to the number indicating the first bit line of the area C based on the address information addr and the signal ai obtained from the column decoder 121, The third bit line number is obtained as the bit line number corresponding to the data to be read from area C. Adder 133 corresponds to the third bit line of area C among the data (X, Y, Z) = (0, 0, 0) to (3, 3, 3) read from area C. Obtain data (X, Y, Z) = (0, 2, 0).

The adder 134 adds the addition value 1 included in the signal ai three times to the number indicating the first bit line of the area D based on the address information addr and the signal ai obtained from the column decoder 121, As the bit line number corresponding to the data to be read from area D, the number of the fourth bit line is obtained. The adder 134 corresponds to the fourth bit line of area D among the data (X, Y, Z) = (0, 0, 0) to (3, 3, 3) read from area D. Obtain data (X, Y, Z) = (0, 3, 0).

With the above, the 4-bit data corresponding to (X, Y, Z) = (0, 0, 0), (0, 1, 0), (0, 2, 0), (0, 3, 0) is It is obtained by adders 131-134. Adders 131 to 134 transfer these data to control section 111.

In the upper right corner of FIG. 11, a cube representing the original data array is shown. According to the upper right diagram of FIG. 11, it can be seen that the data acquired as described above is 4-bit data adjacent in the Y-axis direction.

FIG. 12 is a diagram illustrating a read operation of a plurality of data adjacent in the Z-axis direction in the semiconductor memory device 1 according to the second embodiment of the present disclosure.

Also in FIG. 12, it is assumed that the bit line number that is the starting point of the read operation in each area is the first bit line. Prior to the operations of adders 131 to 134 shown in FIG. 12, operations similar to those described above are performed.

Note that in FIG. 12, the data to be read is data adjacent in the Z-axis direction. Adjacent data in the Z-axis direction has a period in which the addresses on the word line in each region are shifted by four. Therefore, the signal generation circuit 111b generates a signal ai that includes 4 as the addition value to the bit line number that is the starting point of the read operation.

As shown in FIG. 12, the adder 131 reads data (X, Y, Z) = (0, 0, 0) ~ ( 3, 3, 3), data (X, Y, Z) = (0, 0, 0) corresponding to the first bit line in area A is acquired.

The adder 132 adds the addition value 4 included in the signal ai to the number indicating the first bit line of the area B based on the address information addr acquired from the column decoder 121 and the signal ai, and adds the addition value 4 included in the signal ai to the number indicating the first bit line of the area B. The number of the fifth bit line is obtained as the bit line number corresponding to the data to be read. The adder 132 corresponds to the fifth bit line of area B among the data (X, Y, Z) = (0, 0, 0) to (3, 3, 3) read from area B. Obtain data (X, Y, Z) = (0, 0, 1).

The adder 133 adds the addition value 4 included in the signal ai twice to the number indicating the first bit line of the area C based on the address information addr and the signal ai obtained from the column decoder 121, The number of the ninth bit line is obtained as the bit line number corresponding to the data to be read from area C. Adder 133 corresponds to the 9th bit line of area C among the data (X, Y, Z) = (0, 0, 0) to (3, 3, 3) read from area C. Obtain data (X, Y, Z) = (0, 0, 2).

The adder 134 adds the addition value 4 included in the signal ai three times to the number indicating the first bit line of the area D based on the address information addr and the signal ai obtained from the column decoder 121, As the bit line number corresponding to the data to be read from area D, the number of the 13th bit line is obtained. The adder 134 corresponds to the 13th bit line of area D among the data (X, Y, Z) = (0, 0, 0) to (3, 3, 3) read from area D. Obtain data (X, Y, Z) = (0, 0, 3).

With the above, the 4-bit data corresponding to (X, Y, Z) = (0, 0, 0), (0, 0, 1), (0, 0, 2), (0, 0, 3) is It is obtained by adders 131-134. Adders 131 to 134 transfer these data to control section 111.

In the upper right corner of FIG. 12, a cube representing the original data array is shown. According to the upper right diagram of FIG. 12, it can be seen that the data acquired as described above is 4-bit data adjacent in the Z-axis direction.

According to the second embodiment, even for data having a three-dimensional structure, the semiconductor memory device 1 can read data adjacent in any dimension direction all at once with one address designation.

Note that the effects described in this specification are merely examples and are not limiting, and other effects may also exist.

[Other embodiments]
In the first and second embodiments described above, a method of arranging data having a two-dimensional structure and a three-dimensional structure one-dimensionally on a word line has been described. However, the method of arranging these data on the word line is not limited to the method described above. As an example of a method for arranging data with a three-dimensional structure, a method different from that shown in FIG. 9 is shown in FIG.

FIG. 13 is a diagram showing the arrangement order of data to be stored in a semiconductor memory device according to another embodiment of the present disclosure. As shown in FIG. 13, the individual blocks constituting a cube representing three-dimensional data are labeled with symbols A to D in a different arrangement from that in FIG. For example, by arranging each data in areas A to D according to the symbols A to D shown in FIG. 13, a data structure that can be read in any dimension direction can be obtained.

As described above, there may be various variations in the method of arranging original data on word lines.

In the first and second embodiments described above, a method of reading adjacent data in any dimension direction has been described for data having a two-dimensional structure and a three-dimensional structure. However, the original data may have a multidimensional structure of four or more dimensions. After equally distributing the data adjacent to each dimension to each area, the adders 131 to 134 perform calculations based on the signal ai, thereby reading data adjacent to any dimension. becomes possible.

In the first and second embodiments described above, the adders 131 to 134 generate addresses on word lines of data adjacent in any dimension direction. However, the address on the word line may be generated by an arithmetic circuit that performs other operations, such as a subtracter.

Note that the present technology can also have the following configuration.
(1)
a memory cell array in which data having a multidimensional structure is arranged one-dimensionally on word lines;
a controller capable of reading a plurality of data adjacent in any dimension direction from the memory cell array with one address designation;
The controller includes:
an address generation circuit that generates an address on the word line that is a starting point for a read operation;
an arithmetic circuit that performs a predetermined arithmetic operation on the generated address to generate an address on the word line of data adjacent in a dimension direction to be read;
a signal generation circuit that generates a signal including a value used in the calculation;
Semiconductor storage device.
(2)
The plurality of data adjacent to each other in a given dimension are arranged on the word line at a predetermined period,
The semiconductor memory device according to (1) above.
(3)
The signal generation circuit includes:
generating a signal including a period of the plurality of data on the word line;
The arithmetic circuit is
performing an operation on the generated address using the period to generate the address of the data adjacent in the dimension direction of the read target;
The semiconductor memory device according to (2) above.
(4)
the arithmetic circuit is an addition circuit that adds the value to the address;
The semiconductor memory device according to any one of (1) to (3) above.
(5)
the arithmetic circuit is a subtraction circuit that subtracts the value from the address;
The semiconductor memory device according to any one of (1) to (3) above.
(6)
The data has an n-bit word structure,
The period on the word line of the plurality of data adjacent in the first dimension direction is 0,
a period on the word line of a plurality of data adjacent in a second dimension direction orthogonal to the first dimension direction is n;
The semiconductor memory device according to (2) above.
(7)
the data has a two-dimensional structure;
The semiconductor memory device according to (6) above.
(8)
A period on the word line of a plurality of data adjacent in a third dimension direction perpendicular to the first dimension direction and the second dimension direction is 1;
The semiconductor memory device according to (6) above.
(9)
the data has a three-dimensional structure;
The semiconductor memory device according to (8) above.
(10)
A controller capable of reading a plurality of data adjacent in an arbitrary dimension direction from a memory cell array in which data having a multidimensional structure is arranged one-dimensionally on a word line with a single address designation,
an address generation circuit that generates an address on the word line that is a starting point for a read operation;
an arithmetic circuit that performs a predetermined arithmetic operation on the generated address to generate an address on the word line of data adjacent in a dimension direction to be read;
a signal generation circuit that generates a signal including a value used in the calculation;
controller.
(11)
The plurality of data adjacent to each other in a given dimension are arranged on the word line at a predetermined period,
The controller according to (10) above.
(12)
The signal generation circuit includes:
generating a signal including a period of the plurality of data on the word line;
The arithmetic circuit is
performing an operation on the generated address using the period to generate the address of the data adjacent in the dimension direction of the read target;
The controller according to (11) above.
(13)
the arithmetic circuit is an addition circuit that adds the value to the address;
The controller according to any one of (10) to (12) above.
(14)
the arithmetic circuit is a subtraction circuit that subtracts the value from the address;
The controller according to any one of (10) to (12) above.
(15)
The data has an n-bit word structure,
The period on the word line of the plurality of data adjacent in the first dimension direction is 0,
a period on the word line of a plurality of data adjacent in a second dimension direction orthogonal to the first dimension direction is n;
The controller according to (11) above.
(16)
the data has a two-dimensional structure;
The controller according to (15) above.
(17)
A period on the word line of a plurality of data adjacent in a third dimension direction perpendicular to the first dimension direction and the second dimension direction is 1;
The controller according to (15) above.
(18)
the data has a three-dimensional structure;
The controller according to (17) above.
(19)
A method for reading a plurality of data adjacent in an arbitrary dimension direction from a memory cell array in which data having a multidimensional structure is arranged one-dimensionally on a word line by one addressing designation, the method comprising:
generating an address on the word line as a starting point for a read operation;
Performing a predetermined operation on the generated address to generate an address of data adjacent in the dimension direction of the read target,
generate a signal containing a value regarding the dimensional direction of the read target;
performing an operation on the generated address using the value to generate an address of data adjacent in the dimension direction of the read target;
Method.

1 Semiconductor storage device 100 Bank 101 Memory cell array 110 Memory controller 111 Control unit 111a Address generation circuit 111b Signal generation circuit 121 Column decoder 122 Row decoder 123 Sense amplifier/write amplifier 131 to 134 Adder BL Bit line MC Semiconductor memory element WL Word line

Claims (19)

a memory cell array in which data having a multidimensional structure is arranged one-dimensionally on word lines;
a controller capable of reading a plurality of data adjacent in any dimension direction from the memory cell array with one address designation;
The controller includes:
an address generation circuit that generates an address on the word line that is a starting point for a read operation;
an arithmetic circuit that performs a predetermined arithmetic operation on the generated address to generate an address on the word line of data adjacent in a dimensional direction to be read;
a signal generation circuit that generates a signal including a value used in the calculation;
Semiconductor storage device. The plurality of data adjacent to each other in a given dimension are arranged on the word line at a predetermined period,
The semiconductor memory device according to claim 1. The signal generation circuit includes:
generating a signal including a period of the plurality of data on the word line;
The arithmetic circuit is
performing an operation on the generated address using the period to generate the address of the data adjacent in the dimension direction of the read target;
The semiconductor memory device according to claim 2. the arithmetic circuit is an addition circuit that adds the value to the address;
The semiconductor memory device according to claim 1. the arithmetic circuit is a subtraction circuit that subtracts the value from the address;
The semiconductor memory device according to claim 1. The data has an n-bit word structure,
The period on the word line of the plurality of data adjacent in the first dimension direction is 0,
a period on the word line of a plurality of data adjacent in a second dimension direction orthogonal to the first dimension direction is n;
The semiconductor memory device according to claim 2. the data has a two-dimensional structure;
The semiconductor memory device according to claim 6. A period on the word line of a plurality of data adjacent in a third dimension direction perpendicular to the first dimension direction and the second dimension direction is 1;
The semiconductor memory device according to claim 6. the data has a three-dimensional structure;
The semiconductor memory device according to claim 8. A controller capable of reading a plurality of data adjacent in an arbitrary dimension direction from a memory cell array in which data having a multidimensional structure is arranged one-dimensionally on a word line with a single address designation,
an address generation circuit that generates an address on the word line that is a starting point for a read operation;
an arithmetic circuit that performs a predetermined arithmetic operation on the generated address to generate an address on the word line of data adjacent in a dimension direction to be read;
a signal generation circuit that generates a signal including a value used in the calculation;
controller. The plurality of data adjacent to each other in a given dimension are arranged on the word line at a predetermined period,
The controller according to claim 10. The signal generation circuit includes:
generating a signal including a period of the plurality of data on the word line;
The arithmetic circuit is
performing an operation on the generated address using the period to generate the address of the data adjacent in the dimension direction of the read target;
The controller according to claim 11. the arithmetic circuit is an addition circuit that adds the value to the address;
The controller according to claim 10. the arithmetic circuit is a subtraction circuit that subtracts the value from the address;
The controller according to claim 10. The data has an n-bit word structure,
The period on the word line of the plurality of data adjacent in the first dimension direction is 0,
a period on the word line of a plurality of data adjacent in a second dimension direction orthogonal to the first dimension direction is n;
The controller according to claim 11. the data has a two-dimensional structure;
The controller according to claim 15. A period on the word line of a plurality of data adjacent in a third dimension direction perpendicular to the first dimension direction and the second dimension direction is 1;
The controller according to claim 15. the data has a three-dimensional structure;
The controller according to claim 17. A method for reading a plurality of data adjacent in an arbitrary dimension direction from a memory cell array in which data having a multidimensional structure is arranged one-dimensionally on a word line by one addressing designation, the method comprising:
generating an address on the word line as a starting point for a read operation;
Performing a predetermined operation on the generated address to generate an address of data adjacent in the dimension direction of the read target,
generate a signal containing a value regarding the dimensional direction of the read target;
performing an operation on the generated address using the value to generate an address of data adjacent in the dimension direction of the read target;
Method.

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