JP2021117594A - Semiconductor storage device, controller, and method - Google Patents

Abstract

To propose a semiconductor storage device, a controller, and a method capable of efficiently accessing a plurality of data adjacent to each other in an arbitrary dimensional direction.SOLUTION: A semiconductor storage device according to the present disclosure is provided with a memory cell array in which data having a multidimensional structure is arranged one-dimensionally on a word line, and a controller that can read by designating an address once a plurality of data adjacent each other in an arbitrary dimensional direction from the memory cell array, and the controller includes an address generation circuit that generates an address on a word line which is an original point of a read operation, an arithmetic operation circuit that executes a predetermined arithmetic operation for a generated address to generate an address on a word line of adjacent data in a dimensional direction of a reading target, and a signal generation circuit that generates a signal including a value used in the arithmetic operation.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to semiconductor storage devices, controllers, and methods.

For example, in the calculation of a neural network, high-speed and efficient access to adjacent data in each dimensional direction is required for data having a multidimensional structure. By rearranging the data of the multidimensional structure in one dimension and arranging them on the word line, it is possible to improve the efficiency of data access at least in a predetermined dimensional direction (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2009-048753

However, in the configuration disclosed in Patent Document 1, the word configuration of data that can be read by one address designation is determined in advance, and it is difficult to realize efficient access to all dimensional data. ..

Therefore, the present disclosure proposes a semiconductor storage device, a controller, and a method that enable efficient access to a plurality of data adjacent to each other in an arbitrary dimensional direction.

The semiconductor storage device according to the present disclosure includes a memory cell array in which data having a multidimensional structure is arranged one-dimensionally on a word line, and a plurality of data adjacent to each other in an arbitrary dimensional direction from the memory cell array at one time. A controller that can be read by designation is provided, and the controller includes an address generation circuit that generates an address on the word line that is a starting point of a read operation, and a predetermined operation is performed on the generated address to be read. It includes an arithmetic circuit that generates an address on the word line of data adjacent in a dimensional direction, and a signal generation circuit that generates a signal including a value used in the arithmetic.

It is a figure which shows the structure of the semiconductor storage device which concerns on Embodiment 1 of this disclosure. It is a figure which shows the structure of the bank of the semiconductor storage device which concerns on Embodiment 1 of this disclosure. It is a figure which shows an example of the structure which the data to be stored of the semiconductor storage device which concerns on Embodiment 1 of this disclosure has. It is a figure which shows the correspondence | correspondence of the arrangement order of the storage target data of the semiconductor storage device which concerns on Embodiment 1 of this disclosure. It is a figure which shows the reading operation of a plurality of data adjacent to each other in the X-axis direction in the semiconductor storage device which concerns on Embodiment 1 of this disclosure. It is a figure which shows the reading operation of a plurality of data adjacent to each other in the Y-axis direction in the semiconductor storage device which concerns on Embodiment 1 of this disclosure. It is a flow figure which shows an example of the procedure of the read-out process in the semiconductor storage device which concerns on Embodiment 1 of this disclosure. It is a figure which shows the reading operation of a plurality of data adjacent to each other in the Y-axis direction in the semiconductor storage device which concerns on a comparative example. It is a figure which shows the correspondence | correspondence of the arrangement order of the storage target data of the semiconductor storage device which concerns on Embodiment 2 of this disclosure. It is a figure which shows the reading operation of a plurality of data adjacent to each other in the X-axis direction in the semiconductor storage device which concerns on Embodiment 2 of this disclosure. It is a figure which shows the reading operation of a plurality of data adjacent to each other in the Y-axis direction in the semiconductor storage device which concerns on Embodiment 2 of this disclosure. It is a figure which shows the reading operation of a plurality of data adjacent to each other in the Z-axis direction in the semiconductor storage device which concerns on Embodiment 2 of this disclosure. It is a figure which shows the arrangement order of the storage target data of the semiconductor storage device which concerns on other embodiment of this disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the following embodiments, the same parts are designated by the same reference numerals, so that duplicate description will be omitted.

[Embodiment 1]
Hereinafter, the first embodiment will be described with reference to the drawings.

(Configuration example of semiconductor storage device)
FIG. 1 is a diagram showing a configuration of a semiconductor storage device 1 according to the first embodiment of the present disclosure. The semiconductor storage device 1 of the first embodiment is, for example, an MRAM (Magnetristive Random Access Memory), a SRAM (Static RAM), a DRAM (Dynamic RAM), or the like.

As shown in FIG. 1, the semiconductor storage device 1 includes a plurality of banks 100. Each bank 100 includes a memory cell array 101 in which a plurality of semiconductor storage elements are arranged, for example, in a two-dimensional array.

Here, the plurality of banks 100 are parallel operation elements capable of parallel operation with each other. That is, while the predetermined semiconductor storage element in the memory cell array 101 included in one bank 100 is operating, the predetermined semiconductor storage element in the memory cell array 101 included in the other bank 100 can be operated.

Each semiconductor storage element in the memory cell array 101 has a magnetic tunnel junction when the semiconductor storage device 1 is an MRAM, and stores data by changing the state of magnetization. When the semiconductor storage device 1 is an SRAM, the semiconductor storage element in the memory cell array 101 is composed of a flip-flop circuit in which a plurality of transistors are combined, and stores data by holding a charge. When the semiconductor storage device 1 is a DRAM, the semiconductor storage element in the memory cell array 101 stores data by holding a charge in the capacitor.

In the following, each semiconductor storage element in the memory cell array 101 will be described as being an SLC (Single Level Cell) capable of storing 1-bit data. However, the semiconductor storage element in the memory cell array 101 may be an MLC (Multi Level Cell) capable of storing multi-bit data of 2 bits or more.

FIG. 2 is a diagram showing a configuration of a bank 100 of the semiconductor storage device 1 according to the first embodiment of the present disclosure. As shown in FIG. 2, one bank 100 includes the above-mentioned memory cell array 101 and memory controller 110.

The memory cell array 101 includes, for example, a plurality of bit lines BL extending in parallel with each other in the vertical direction of the paper surface. Further, the memory cell array 101 includes, for example, a plurality of word lines WL extending in parallel with each other in the horizontal direction of the paper surface. Each semiconductor storage element MC is connected to either bit line BL and any word line WL. That is, the semiconductor storage elements MC are arranged in an array at each intersection of the bit line BL and the word line WL.

The memory controller 110 includes a control unit 111, a column decoder (CA Dec) 121, a low decoder (RA Dec) 122, a sense amplifier / light amplifier (SA / WA) 123, and an adder (MUX) 131-134.

The control unit 111 controls the entire bank 100 including the semiconductor storage element MC in the memory cell array 101 by controlling the operation of each of the above configurations in the memory controller 110. The control unit 111 includes an address generation circuit 111a and a signal generation circuit 111b.

When writing and reading data to a predetermined semiconductor storage element MC in the memory cell array 101, the address generation circuit 111a includes the column address CA and row of the semiconductor storage element MC that is the starting point of the operation among the semiconductor storage element MCs to be operated. Generate address RA. The column address CA is an address that specifies the bit line BL connected to the predetermined semiconductor storage element MC, and is transferred to the column decoder 121. The low address RA is an address that specifies the word line WL connected to the predetermined semiconductor storage element MC, and is transferred to the low decoder 122.

The signal generation circuit 111b generates a signal ai for identifying the remaining semiconductor storage element MCs, excluding the semiconductor storage element MC that is the starting point, among the semiconductor storage element MCs to be operated. The generated signal ai is added to the above column address CA and transferred to the column decoder 121.

The column decoder 121 identifies the corresponding bit line BL based on the column address CA acquired from the control unit 111. Then, the signal ai is transferred to the adders 131 to 134 together with the address information addr of the specified bit line BL.

The low decoder 122 selects the corresponding word line WL based on the low address RA acquired from the control unit 111, and drives the selected word line WL by, for example, applying a predetermined voltage.

The sense amplifier / light amplifier 123 drives a predetermined bit line BL by, for example, applying a predetermined voltage. As a result, the semiconductor storage element MC connected to both the drive bit line BL and the drive word line WL described above is driven. Then, at the time of writing, data is written to the semiconductor storage element MC. Further, at the time of reading, the data of the semiconductor storage element MC is read out to the sense amplifier / light amplifier 123.

The adders 131 to 134 as the arithmetic circuit generate the address of the bit line BL connected to the semiconductor storage element MC to be operated based on the address information addr and the signal ai acquired from the column decoder 121. The individual adders 131 to 134 have, for example, a configuration in which a plurality of multiplexers are combined, and add a given predetermined value to the original numerical value. Here, the original numerical value is, for example, a number indicating the bit line BL included in the address information addr, and a predetermined value to be added is included in, for example, the signal ai.

The address information addr is transferred to the first adder 131, and the signal ai is not transferred. Therefore, the adder 131 uses the address included in the address information addr as the address of the bit line BL connected to the semiconductor storage element MC to be operated.

The signal ai is given to the second adder 132 once together with the address information addr. Therefore, the adder 132 adds the value included in the signal ai once to the address included in the address information addr to generate the address of the bit line BL connected to the semiconductor storage element MC to be operated.

The signal ai is given to the third adder 133 twice together with the address information addr. Therefore, the adder 133 adds the value included in the signal ai twice to the address included in the address information adddr to generate the address of the bit line BL connected to the semiconductor storage element MC to be operated.

The signal ai is given to the fourth adder 134 three times together with the address information addr. Therefore, the adder 134 adds the value included in the signal ai to the address included in the address information addr three times to generate the address of the bit line BL connected to the semiconductor storage element MC to be operated.

Further, the adders 131 to 134 complete the operation of the semiconductor storage element MC corresponding to the address of the bit line BL generated by the calculation. That is, at the time of writing, data is written to the semiconductor storage element MC connected to the bit line BL corresponding to the address generated by the calculation among all the semiconductor storage element MCs on the drive word line WL. Further, at the time of reading, the data of all the semiconductor storage elements MC on the drive word line WL is read out to the sense amplifier / write amplifier 123, and among them, the data is connected to the bit line BL corresponding to the address generated by the calculation. Data from the semiconductor storage element MC is acquired by each adder 131-134. The adders 131 to 134 transfer the acquired data to the control unit 111.

By the way, the addition of a predetermined value to the bit line number is repeated for the number of bits that the semiconductor storage device can process at one time. Further, when reading data, it is necessary to read data for the number of bits that can be processed at one time. Therefore, an adder having the same number of bits as the number of bits that can be processed at one time is required. In the example of FIG. 2, the semiconductor storage device 1 of the first embodiment includes four adders 131 to 134. That is, the semiconductor storage device 1 of the first embodiment has a 4-bit word configuration and can process 4-bit data at a time.

In addition to the above configuration, the memory controller 110 may include, for example, a data array conversion circuit (not shown) that rearranges the individual data read by the adders 131 to 134.

(Example of data structure of semiconductor storage device)
Next, using FIGS. 3 and 4, a structure originally possessed by the data to be stored in the semiconductor storage device 1 of the first embodiment and a data structure in a state actually stored in the semiconductor storage device 1 The correspondence with and will be explained.

As will be described below, the data to be stored in the semiconductor storage device 1 has, for example, a multidimensional structure. On the other hand, in the state stored in the semiconductor storage device 1, these data have a structure arranged one-dimensionally on, for example, one word line.

FIG. 3 is a diagram showing an example of the structure of the data to be stored in the semiconductor storage device 1 according to the first embodiment of the present disclosure. In the following figures including FIG. 3, one cell represents one bit of data.

As shown in FIG. 3, the original data to be stored has a two-dimensional structure in which individual data are arranged in a matrix along, for example, the X-axis and the Y-axis. In this way, for data having a multidimensional structure, it is possible to access a plurality of data adjacent to each other in an arbitrary dimensional direction in a batch as appropriate by one read operation, that is, one address designation. desirable.

That is, for example, in the case of data having the two-dimensional structure of FIG. 3, as described above, when the semiconductor storage device 1 of the first embodiment has a 4-bit word configuration, the 4-bit data arranged in the X-axis direction ( For example, the data surrounded by the solid line in FIG. 3) and the 4-bit data arranged in the Y-axis direction (for example, the data surrounded by the broken line in FIG. 3) can be arbitrarily specified and read appropriately. Is desired. Therefore, as a precondition for enabling such a read operation, the semiconductor storage device 1 has a structure in which the data arranged on one word line has a structure as shown in FIG. 4, for example.

FIG. 4 is a diagram showing the correspondence relationship of the arrangement order of the storage target data of the semiconductor storage device 1 according to the first embodiment of the present disclosure. The upper part of FIG. 4 shows the original arrangement of the data to be stored, and the lower part of FIG. 4 shows the arrangement of the data stored in the semiconductor storage device 1.

As shown in the lower part of FIG. 4, in the memory cell array 101 of the semiconductor storage device 1, the data of the above-mentioned two-dimensional structure is distributed to the areas from the area A to the area D assigned to the word lines, and each corresponding position. It is stored in a semiconductor storage element arranged in.

The numbers X and Y shown in the lower part of FIG. 4 represent the arrangement positions of the original data on the X-axis and the Y-axis. The data structure shown in the upper part of FIG. 4 is the same as that shown in FIG. 3 described above. The codes A to D corresponding to ~ D were assigned.

According to the example of FIG. 4, for example, the 4-bit data adjacent to the X-axis direction and the 4-bit data adjacent to the Y-axis direction are all evenly distributed to the regions A to D, respectively. Then, in each area, the same address is given to the data arranged at the same position. In other words, in the data at the same position in each region, the addresses on the word lines of the data are equal to each other. The data at the same position in each area means the data arranged in the same order on the word line in each area. The address on the word line is represented by, for example, the number of the bit line intersecting the word line.

For example, among the bit lines that intersect the word line in the area A, the data corresponding to the third bit line, that is, the data that is arranged third on the word line and the bit line that intersects the word line in the area B. Of these, the data corresponding to the third bit line, that is, the data arranged third on the word line is the data arranged at the same position in each of the areas A and B, and the address on the word line is They are the same as each other.

By arranging each data on the word line as described above, if a predetermined data is extracted one by one from each of the regions A to D, 4-bit data adjacent to each other in an arbitrary dimensional direction can be acquired. Can be done.

Here, the 4-bit data adjacent to each other in an arbitrary dimensional direction is arranged on the word line at a predetermined period. More specifically, in these data, the addresses on the word lines in the regions A to D, that is, the bit line numbers are deviated in a predetermined cycle. In order to obtain data adjacent to each other in an arbitrary dimensional direction, when extracting data from each of the areas A to D, starting from the bit line number corresponding to the data of the first bit, in each area, from that number. The data corresponding to the bit line numbers shifted by a predetermined period may be extracted.

In the semiconductor storage device 1 of the first embodiment, the adders 131 to 134 described above correspond to each of the areas A to D, and acquire the data read from the area corresponding to the adder 131 to 134.

At this time, the address information addr given to each adder 131 to 134 indicates an address on a word line, that is, a bit line number, which is a starting point when acquiring data in each area. Then, signals ai are given to the adders 132 to 134 other than the first adder 131. The signal ai includes a numerical value to be added to the bit line number that is the starting point of data acquisition, that is, a period of deviation from the bit line number that is the starting point.

For example, when the bit line number that is the starting point of data acquisition indicates the third bit line that intersects the word line in each area, the adder 131 is among the data read from the area A. The data corresponding to the third bit line of the area A is acquired.

Further, the adder 132 acquires the data corresponding to the bit line of the number obtained by adding the numerical value included in the signal ai to the number of the third bit line of the area B among the data read from the area B. Further, the adder 133 adds the data corresponding to the bit line of the number obtained by adding the numerical value included in the signal ai twice to the number of the third bit line of the area C among the data read from the area C. get. Further, the adder 134 adds the data corresponding to the bit line of the number obtained by adding the numerical value included in the signal ai to the number of the third bit line of the area D three times among the data read from the area D. get.

(Example of read operation of semiconductor storage device)
Next, the read operation in the semiconductor storage device 1 will be described with reference to FIGS. 5 and 6 with specific examples. In the following description, predetermined data may be indicated by X and Y numbers. These numbers indicate the array positions on the X and Y axes in the original two-dimensional structure of the data. Note that these numbers do not represent addresses on the word line.

FIG. 5 is a diagram showing a reading operation of a plurality of data adjacent to each other in the X-axis direction in the semiconductor storage device 1 according to the first embodiment of the present disclosure. In FIG. 5, it is assumed that the bit line number that is the starting point of the read operation in each area is the first bit line. In that case, the following operations are performed prior to the operations of the adders 131 to 134 shown in FIG.

The address generation circuit 111a of the control unit 111 generates a low address indicating a word line connected to the semiconductor storage element to be read out, and transfers the low address to the low decoder 122. The row decoder 122 selects and drives the word line indicated by the row address.

Further, the address generation circuit 111a generates a column address indicating a bit line that is a starting point of a read operation.

The signal generation circuit 111b of the control unit 111 generates a signal ai including a numerical value to be added to the bit line number that is the starting point of the read operation based on the adjacent dimensional directions of the plurality of data to be read. In FIG. 5, the plurality of data to be read are data adjacent to each other in the X-axis direction. In the data adjacent to each other in the X-axis direction, there is no deviation in the address on the word line in each region. That is, the period of deviation from the starting bit line number is zero, and the added value included in the signal ai is zero.

The control unit 111 transfers the generated column address and signal ai to the column decoder 121.

On the other hand, the sense amplifier / light amplifier 123 drives a predetermined bit line. The bit lines to be driven here may be substantially all the bit lines in the memory cell array 101. As a result, the sense amplifier / light amplifier 123 reads out all the data on the drive word line selected by the low decoder 122.

The column decoder 121 generates address information addr including a bit line number that specifies the first bit line among the bit lines that intersect the word line in each area based on the column address acquired from the control unit 111. The column decoder 121 adds a signal ai to the generated address information addr and transfers it to the adders 131 to 134.

After that, the operations of the adders 131 to 134 shown in FIG. 5 are executed.

As shown in FIG. 5, the adder 131 reads data (X, Y) = (0,0) to (3,3) from the area A based on the address information adddr acquired from the column decoder 121. Among them, the data (X, Y) = (0,0) corresponding to the first bit line of the area A is acquired.

The adder 132 generates an address on the word line of data to be read from the area B based on the address information addr and the signal ai acquired from the column decoder 121. Here, since the addition value zero included in the signal ai is added to the number indicating the first bit line of the area B, the bit line number corresponding to the data to be read from the area B is the first bit line. It remains a number. The adder 132 is the data (X, Y) corresponding to the first bit line of the area B among the data (X, Y) = (0,0) to (3,3) read from the area B. = (0,0) is acquired.

The adder 133 generates an address on the word line of data to be read from the area C based on the address information addr and the signal ai acquired from the column decoder 121. Here, since the addition value zero included in the signal ai is added twice to the number indicating the first bit line of the area C, the bit line number corresponding to the data to be read from the area C is the first. It remains the bit line number. The adder 133 is the data (X, Y) corresponding to the first bit line of the area C among the data (X, Y) = (0,0) to (3,3) read from the area C. = (0,0) is acquired.

The adder 134 generates an address on the word line of data to be read from the area D based on the address information addr and the signal ai acquired from the column decoder 121. Here, since the addition value zero included in the signal ai is added three times to the number indicating the first bit line of the area D, the bit line number corresponding to the data to be read from the area D is the first. It remains the bit line number. The adder 134 is the data (X, Y) corresponding to the first bit line of the area D among the data (X, Y) = (0,0) to (3,3) read from the area D. = (0,0) is acquired.

As described above, the 4-bit data corresponding to (X, Y) = (0,0), (0,0), (0,0), (0,0) is acquired by the adders 131 to 134. According to the original data array shown in the upper right of FIG. 5, it can be seen that these data are 4-bit data adjacent to each other in the X-axis direction. The adders 131 to 134 transfer these data to the control unit 111.

FIG. 6 is a diagram showing a reading operation of a plurality of data adjacent to each other in the Y-axis direction in the semiconductor storage device 1 according to the first embodiment of the present disclosure.

Also in FIG. 6, it is assumed that the bit line number that is the starting point of the read operation in each area is the first bit line. In that case, an operation similar to the above-described operation is performed prior to the operation of the adders 131 to 134 shown in FIG.

However, in FIG. 6, the data to be read is data adjacent to each other in the Y-axis direction. The data adjacent to each other in the Y-axis direction has a period in which the addresses on the word line in each region are shifted by four. Therefore, the signal generation circuit 111b generates a signal ai including 4 as an addition value to the bit line number that is the starting point of the read operation.

As shown in FIG. 6, the adder 131 reads data (X, Y) = (0,0) to (3,3) from the area A based on the address information adddr acquired from the column decoder 121. Among them, the data (X, Y) = (0,0) corresponding to the first bit line of the area A is acquired.

The adder 132 adds the addition value 4 included in the signal ai to the number indicating the first bit line of the area B based on the address information addr and the signal ai acquired from the column decoder 121, and starts from the area B. The fifth bit line number is obtained as the bit line number corresponding to the data to be read. The adder 132 is the data (X, Y) corresponding to the fifth bit line of the area B among the data (X, Y) = (0,0) to (3,3) read from the area B. = (0,1) is acquired.

The adder 133 adds the addition value 4 included in the signal ai twice to the number indicating the first bit line of the area C based on the address information addr and the signal ai acquired from the column decoder 121. The 9th bit line number is obtained as the bit line number corresponding to the data to be read from the area C. The adder 133 is the data (X, Y) corresponding to the ninth bit line of the area C among the data (X, Y) = (0,0) to (3,3) read from the area C. = (0,2) is acquired.

The adder 134 adds the addition value 4 included in the signal ai three times to the number indicating the first bit line of the area D based on the address information addr and the signal ai acquired from the column decoder 121. The 13th bit line number is obtained as the bit line number corresponding to the data to be read from the area D. The adder 134 is the data (X, Y) corresponding to the 13th bit line of the area D among the data (X, Y) = (0,0) to (3,3) read from the area D. = (0,3) is acquired.

As described above, the 4-bit data corresponding to (X, Y) = (0,0), (0,1), (0,2), (0,3) is acquired by the adders 131 to 134. According to the original data array shown in the upper right of FIG. 6, it can be seen that these data are 4-bit data adjacent to each other in the Y-axis direction. The adders 131 to 134 transfer these data to the control unit 111.

Depending on the data allocation method, the data reading order by the adders 131 to 134 may be different from the original data array. In such a case, the order of the read data may be changed so as to be in the original data arrangement order by a data arrangement conversion circuit or the like (not shown) described above.

(Example of read processing of semiconductor storage device)
Next, an example of read processing in the semiconductor storage device 1 will be described with reference to FIG. 7. FIG. 7 is a flow chart showing an example of a read processing procedure in the semiconductor storage device 1 according to the first embodiment of the present disclosure.

As shown in FIG. 7, the address generation circuit 111a of the control unit 111 generates a column address and a row address of data that are the starting points of the read operation (step S101).

Further, the signal generation circuit 111b of the control unit 111 generates a signal ai based on the dimensional direction of the adjacent data to be read (step S102). For example, when the original data has the two-dimensional structure shown in FIG. 4 and the dimensional direction is the X-axis direction, a signal ai including zero in the added value is generated. When the dimensional direction is the Y-axis direction, a signal ai including 4 in the added value is generated.

The control unit 111 transfers the generated column address and signal ai to the column decoder 121. Further, the control unit 111 transfers the generated row address to the row decoder 122 (step S103).

The row decoder 122 selects and drives a word line corresponding to the acquired row address based on the acquired row address (step S104).

The sense amplifier / write amplifier 123 drives a bit line (practically, all bit lines in the memory cell array 101) intersecting the word line selected by the low decoder 122, and reads out all the data on the selected word line (step S105). ).

The column decoder 121 generates the address information addr including the bit line number which is the address on the selected word line based on the acquired column address. The column decoder 121 transfers the generated address information addr together with the signal ai to the adders 131 to 134 (step S106).

The first adder 131 acquires the data corresponding to the predetermined bit line number of the area A as the data of the first bit based on the acquired address information addr (step S107).

The (n + 1) th adder adds the added value included in the signal ai n times to the bit line number included in the acquired address information adddr, and is the word of the (n + 1) th data to be acquired by itself. A bit line number, which is an address on the line, is generated (step S108).

The (n + 1) th adder acquires the data corresponding to the obtained bit line number from the region corresponding to itself as the data of the (n + 1) th bit (step S109).

If the data in the (n + 1) bit th is not the last data to be acquired (step S110: No), the number of n is incremented by one (step S111), and the processes of steps S108 to S109 are repeated.

When the data in the (n + 1) bit th is the last data to be acquired (step S110: Yes), the control unit 111 ends the process.

As a result, the read process in the semiconductor storage device 1 is completed.

(Comparison example)
Next, the semiconductor storage device of the comparative example will be described with reference to FIG. FIG. 8 is a diagram showing a read operation of a plurality of data adjacent to each other in the Y-axis direction in the semiconductor storage device according to the comparative example.

In the semiconductor storage device of the comparative example, for example, 4-bit data adjacent to each other in the X-axis direction have the same address. As a result, in the semiconductor storage device of the comparative example, 4-bit data (for example, (X, Y) = (0,0), etc.) adjacent to each other in the X-axis direction can be read by specifying the address once. The operation of reading a plurality of data by specifying one address is also referred to as a burst operation.

However, this means that in the semiconductor storage device of the comparative example, the word configuration of readable adjacent data is fixed in a predetermined dimensional direction. Therefore, from the semiconductor storage device of the comparative example, for example, 4-bit data (X, Y) = (0,0), (0,1), (0,2), in a broken line frame adjacent to the Y-axis direction. When trying to read (0,3), the following processing as shown in FIG. 8 is required.

That is, in order to read the first bit data (X, Y) = (0,0), the first address is specified, and the 4-bit data (X, Y) = (0) adjacent in the X-axis direction is specified. , 0) is read.

In order to read the second bit data (X, Y) = (0,1), the second address is specified, and the 4-bit data (X, Y) = (0,1) adjacent in the X-axis direction is specified. ) Is read.

In order to read the 3rd bit data (X, Y) = (0,2), the 3rd address is specified, and the 4 bit data (X, Y) = (0,2) adjacent in the X axis direction is specified. ) Is read.

In order to read the 4th bit data (X, Y) = (0,3), the 4th address is specified, and the 4 bit data (X, Y) = (0,3) adjacent in the X axis direction is specified. ) Is read.

As described above, 4-bit data adjacent to each other in the Y-axis direction can be obtained, but it requires four address designations, that is, processing for, for example, four clocks. In addition to the required 4-bit data, even 12-bit extra data is read out.

As described above, the semiconductor storage device of the comparative example may be inefficient in terms of time and power depending on the dimensional direction to be read.

According to the semiconductor storage device 1 of the first embodiment, the adders 131 to 134 generate addresses on the word line of data adjacent to each other in the dimensional direction to be read. The signal generation circuit 111b of the control unit 111 generates a signal ai including a value necessary for generating the address. As a result, a plurality of data adjacent to each other in an arbitrary dimensional direction can be read by one address specification, that is, for example, one clock process. In addition, it is possible to suppress the occurrence of unnecessary access such as reading data other than the data to be read.

According to the semiconductor storage device 1 of the first embodiment, by providing the above configuration, it can be suitably applied to, for example, a memory for storing input data, a memory for storing coefficients, and the like in an operation related to a neural network.

[Embodiment 2]
Hereinafter, the second embodiment will be described with reference to the drawings. In the second embodiment, processing of data having a three-dimensional structure will be described.

(Example of data structure of semiconductor storage device)
FIG. 9 is a diagram showing the correspondence relationship of the arrangement order of the storage target data of the semiconductor storage device 1 according to the second embodiment of the present disclosure. The upper part of FIG. 9 shows the original arrangement of the storage target data, the middle part of FIG. 9 shows the raster arrangement of the storage target data, and the lower part of FIG. 9 shows the semiconductor storage device 1. Shows an array of data in the stored state.

As shown in the upper part of FIG. 9, in the second embodiment, the original data to be stored in the semiconductor storage device 1 has, for example, a three-dimensional structure. In the upper figure of FIG. 9, each block constituting the cube representing the three-dimensional data represents data of one bit at a time. The numerical values shown in the figure indicate the arrangement position of each data on the X-axis, the Y-axis, and the Z-axis. Reference numerals A to D attached to the individual blocks constituting the cube exemplify which region A to D of the regions A to D on the word line of the semiconductor storage device 1 the data is distributed to.

In the semiconductor storage device 1, even for data having such a three-dimensional structure, a plurality of data adjacent to an arbitrary dimensional direction (X-axis direction, Y-axis direction, and Z-axis direction) can be collectively designated by one address. Can be accessed. As a premise of such a read operation, these data can have a structure as shown in the lower part of FIG. 9, for example, in a state of being stored in the semiconductor storage device 1.

The middle part of FIG. 9 shows a raster array of the original data so that the correspondence between the original data array and the data array in the semiconductor storage device 1 can be easily grasped. That is, the middle row of FIG. 9 is deviated by one in the Y-axis direction each time data X = 0 to data X = 3, and one in the Z-axis direction when data Y = 0 to data Y = 3. Each data is arranged by the procedure of shifting.

As shown in the lower part of FIG. 9, the 4-bit data adjacent to the X-axis direction, the 4-bit data adjacent to the Y-axis direction, and the 4-bit data adjacent to the Z-axis direction are all regions A to A to It is evenly distributed to D. Then, for example, the same address is assigned to the data arranged at the same position in each area.

(Example of read operation of semiconductor storage device)
Next, the read operation in the semiconductor storage device 1 will be described with reference to FIGS. 10 to 12. In the following description, predetermined data may be indicated by X, Y, and Z numbers. These numbers indicate the arrangement positions on the X-axis, Y-axis, and Z-axis in the original three-dimensional structure of the data.

FIG. 10 is a diagram showing a read-out operation of a plurality of data adjacent to each other in the X-axis direction in the semiconductor storage device 1 according to the second embodiment of the present disclosure. In FIG. 10, it is assumed that the bit line number that is the starting point of the read operation in each area is the first bit line.

Prior to the operation of the adders 131 to 134 shown in FIG. 10, the control unit 111 generates a column address, a row address, and a signal ai, transfers them to the column decoder 121 and the row decoder 122, and transfers the sense amplifier / light amplifier 123. All data on the predetermined word line is acquired by.

In FIG. 10, the data to be read is data adjacent to each other in the X-axis direction. As for the data adjacent to each other in the X-axis direction, the address on the word line does not change in each region. Therefore, the signal generation circuit 111b generates a signal ai including zero as an addition value to the bit line number that is the starting point of the read operation.

As shown in FIG. 10, the adder 131 has data (X, Y, Z) = (0,0,0) to (0,0,0) read from the area A based on the address information adddr acquired from the column decoder 121. Of 3, 3, 3), the data (X, Y, Z) = (0,0,0) corresponding to the first bit line of the area A is acquired.

The adder 132 adds the addition value zero included in the signal ai to the number indicating the first bit line of the area B based on the address information addr and the signal ai acquired from the column decoder 121, and starts from the area B. The number of the first bit line is obtained as the bit line number corresponding to the data to be read. The adder 132 corresponds to the first bit line of the area B among the data (X, Y, Z) = (0,0,0) to (3,3,3) read from the area B. Data (X, Y, Z) = (1,0,0) is acquired.

The adder 133 adds the addition value zero included in the signal ai twice to the number indicating the first bit line of the region C based on the address information addr and the signal ai acquired from the column decoder 121. The first bit line number is obtained as the bit line number corresponding to the data to be read from the area C. The adder 133 corresponds to the first bit line of the area C among the data (X, Y, Z) = (0,0,0) to (3,3,3) read from the area C. Data (X, Y, Z) = (2,0,0) is acquired.

Based on the address information addr and the signal ai acquired from the column decoder 121, the adder 134 adds the addition value zero included in the signal ai to the number indicating the first bit line of the area D three times. The first bit line number is obtained as the bit line number corresponding to the data to be read from the area D. The adder 134 corresponds to the first bit line of the area D among the data (X, Y, Z) = (0,0,0) to (3,3,3) read from the area D. Data (X, Y, Z) = (3,0,0) is acquired.

As a result, the 4-bit data corresponding to (X, Y, Z) = (0,0,0), (1,0,0), (2,0,0), (3,0,0) can be obtained. Obtained by adders 131-134. The adders 131 to 134 transfer these data to the control unit 111.

The cube representing the original data array is shown in the upper right of FIG. Instead of the symbols A to D in FIG. 9, the individual blocks constituting the cube are on the X-axis, the Y-axis, and the Z-axis so that the position of the acquired data as described above can be easily grasped. Numbers indicating the arrangement position of each data are given. According to the upper right figure of FIG. 10, it can be seen that the data acquired as described above is 4-bit data adjacent in the X-axis direction.

FIG. 11 is a diagram showing a reading operation of a plurality of data adjacent to each other in the Y-axis direction in the semiconductor storage device 1 according to the second embodiment of the present disclosure.

Also in FIG. 11, it is assumed that the bit line number that is the starting point of the read operation in each area is the first bit line. Prior to the operation of the adders 131 to 134 shown in FIG. 11, the same operation as described above is performed.

In FIG. 11, the data to be read is data adjacent to each other in the Y-axis direction. The data adjacent to each other in the Y-axis direction has a period in which the addresses on the word lines in each region are shifted by one. Therefore, the signal generation circuit 111b generates a signal ai including 1 as an addition value to the bit line number that is the starting point of the read operation.

As shown in FIG. 11, the adder 131 has data (X, Y, Z) = (0,0,0) to (0,0,0) read from the area A based on the address information adddr acquired from the column decoder 121. Of 3, 3, 3), the data (X, Y, Z) = (0,0,0) corresponding to the first bit line of the area A is acquired.

The adder 132 adds the addition value 1 included in the signal ai to the number indicating the first bit line of the area B based on the address information addr and the signal ai acquired from the column decoder 121, and starts from the area B. The second bit line number is obtained as the bit line number corresponding to the data to be read. The adder 132 corresponds to the second bit line of the area B among the data (X, Y, Z) = (0,0,0) to (3,3,3) read from the area B. Data (X, Y, Z) = (0,1,0) is acquired.

The adder 133 adds the addition value 1 included in the signal ai twice to the number indicating the first bit line of the area C based on the address information addr and the signal ai acquired from the column decoder 121. The third bit line number is obtained as the bit line number corresponding to the data to be read from the area C. The adder 133 corresponds to the third bit line of the area C among the data (X, Y, Z) = (0,0,0) to (3,3,3) read from the area C. Data (X, Y, Z) = (0,2,0) is acquired.

The adder 134 adds the addition value 1 included in the signal ai three times to the number indicating the first bit line of the area D based on the address information addr and the signal ai acquired from the column decoder 121. The fourth bit line number is obtained as the bit line number corresponding to the data to be read from the area D. The adder 134 corresponds to the fourth bit line of the area D among the data (X, Y, Z) = (0,0,0) to (3,3,3) read from the area D. Data (X, Y, Z) = (0,3,0) is acquired.

As a result, the 4-bit data corresponding to (X, Y, Z) = (0,0,0), (0,1,0), (0,2,0), (0,3,0) can be obtained. Obtained by adders 131-134. The adders 131 to 134 transfer these data to the control unit 111.

The cube representing the original data array is shown in the upper right corner of FIG. According to the upper right figure of FIG. 11, it can be seen that the data acquired as described above is 4-bit data adjacent in the Y-axis direction.

FIG. 12 is a diagram showing a reading operation of a plurality of data adjacent to each other in the Z-axis direction in the semiconductor storage device 1 according to the second embodiment of the present disclosure.

Also in FIG. 12, it is assumed that the bit line number that is the starting point of the read operation in each area is the first bit line. Prior to the operation of the adders 131 to 134 shown in FIG. 12, the same operation as described above is performed.

In FIG. 12, the data to be read is data adjacent to each other in the Z-axis direction. The data adjacent to each other in the Z-axis direction has a period in which the addresses on the word line in each region are shifted by four. Therefore, the signal generation circuit 111b generates a signal ai including 4 as an addition value to the bit line number that is the starting point of the read operation.

As shown in FIG. 12, the adder 131 has data (X, Y, Z) = (0,0,0) to (0,0,0) read from the area A based on the address information adddr acquired from the column decoder 121. Of 3, 3, 3), the data (X, Y, Z) = (0,0,0) corresponding to the first bit line of the area A is acquired.

The adder 132 adds the addition value 4 included in the signal ai to the number indicating the first bit line of the area B based on the address information addr and the signal ai acquired from the column decoder 121, and starts from the area B. The fifth bit line number is obtained as the bit line number corresponding to the data to be read. The adder 132 corresponds to the fifth bit line of the area B among the data (X, Y, Z) = (0,0,0) to (3,3,3) read from the area B. Data (X, Y, Z) = (0,0,1) is acquired.

The adder 133 adds the addition value 4 included in the signal ai twice to the number indicating the first bit line of the area C based on the address information addr and the signal ai acquired from the column decoder 121. The 9th bit line number is obtained as the bit line number corresponding to the data to be read from the area C. The adder 133 corresponds to the ninth bit line of the area C among the data (X, Y, Z) = (0,0,0) to (3,3,3) read from the area C. Data (X, Y, Z) = (0,0,2) is acquired.

The adder 134 adds the addition value 4 included in the signal ai three times to the number indicating the first bit line of the area D based on the address information addr and the signal ai acquired from the column decoder 121. The 13th bit line number is obtained as the bit line number corresponding to the data to be read from the area D. The adder 134 corresponds to the 13th bit line of the area D among the data (X, Y, Z) = (0,0,0) to (3,3,3) read from the area D. Data (X, Y, Z) = (0,0,3) is acquired.

As a result, the 4-bit data corresponding to (X, Y, Z) = (0,0,0), (0,0,1), (0,0,2), (0,0,3) can be obtained. Obtained by adders 131-134. The adders 131 to 134 transfer these data to the control unit 111.

The cube representing the original data array is shown in the upper right corner of FIG. According to the upper right figure of FIG. 12, it can be seen that the data acquired as described above is 4-bit data adjacent in the Z-axis direction.

According to the second embodiment, the semiconductor storage device 1 can collectively read data having a three-dimensional structure and adjacent data in an arbitrary dimensional direction with a single address designation.

It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

[Other Embodiments]
In the above-described first and second embodiments, a method of arranging data having a two-dimensional structure and a three-dimensional structure in one dimension on a word line has been described. However, the method of arranging these data on the word line is not limited to the one described above. As an example of the data arrangement method of the three-dimensional structure, a method different from that of FIG. 9 is shown in FIG.

FIG. 13 is a diagram showing an arrangement order of data to be stored in the semiconductor storage device according to another embodiment of the present disclosure. As shown in FIG. 13, the individual blocks constituting the cube representing the three-dimensional data are designated by reference numerals A to D in a different arrangement from that in FIG. For example, by arranging each data in the regions A to D according to the reference numerals A to D attached to FIG. 13, a data structure that can be read in an arbitrary dimensional direction can be obtained.

In this way, there can be various variations in the method of arranging the original data on the word line.

In the above-described first and second embodiments, a method of reading data adjacent to each other in an arbitrary dimensional direction has been described for data having a two-dimensional structure and a three-dimensional structure. However, the original data may have a multidimensional structure of four or more dimensions. Data adjacent to each dimensional direction is evenly distributed to each region, and then the above adders 131 to 134 perform calculations based on the signal ai to read out data adjacent to any dimensional direction. Is possible.

In the above-described first and second embodiments, the address on the word line of the data adjacent to each other in an arbitrary dimensional direction is generated by the adders 131 to 134. However, the address on the word line may be generated by an arithmetic circuit that performs other arithmetic such as a subtractor.

The present technology can also have the following configurations.
(1)
A memory array in which data with a multidimensional structure is arranged in one dimension on a word line,
A controller capable of reading a plurality of data adjacent to each other in an arbitrary dimensional direction from the memory cell array with a single address designation is provided.
The controller
An address generation circuit that generates an address on the word line that is the starting point of the read operation,
An arithmetic circuit that performs a predetermined operation on the generated address to generate an address on the word line of data adjacent to the dimension direction to be read.
A signal generation circuit that generates a signal including a value used in the calculation is provided.
Semiconductor storage device.
(2)
The plurality of data adjacent to each other in an arbitrary dimensional direction are arranged on the word line at a predetermined period.
The semiconductor storage device according to (1) above.
(3)
The signal generation circuit
Generate a signal containing the period of the plurality of data on the word line.
The arithmetic circuit
The generated address is subjected to an operation using the period to generate the address of the data adjacent to the dimension direction to be read.
The semiconductor storage device according to (2) above.
(4)
The arithmetic circuit is an addition circuit that adds the value to the address.
The semiconductor storage device according to any one of (1) to (3) above.
(5)
The arithmetic circuit is a subtraction circuit that subtracts the value from the address.
The semiconductor storage device according to any one of (1) to (3) above.
(6)
The data has an n-bit word structure and has an n-bit word structure.
The period of the plurality of data adjacent to each other in the first dimensional direction on the word line is 0, and the period is 0.
The period of a plurality of data adjacent to the second dimensional direction orthogonal to the first dimensional direction on the word line is n.
The semiconductor storage device according to (2) above.
(7)
The data has a two-dimensional structure.
The semiconductor storage device according to (6) above.
(8)
The period of a plurality of data adjacent to the third dimensional direction orthogonal to the first dimensional direction and the second dimensional direction on the word line is 1.
The semiconductor storage device according to (6) above.
(9)
The data has a three-dimensional structure.
The semiconductor storage device according to (8) above.
(10)
A controller that can read multiple data adjacent to each other in an arbitrary dimensional direction with a single address specification from a memory array in which data having a multidimensional structure is arranged one-dimensionally on a word line.
An address generation circuit that generates an address on the word line that is the starting point of the read operation,
An arithmetic circuit that performs a predetermined operation on the generated address to generate an address on the word line of data adjacent to the dimension direction to be read.
A signal generation circuit that generates a signal including a value used in the calculation is provided.
controller.
(11)
The plurality of data adjacent to each other in an arbitrary dimensional direction are arranged on the word line at a predetermined period.
The controller according to (10) above.
(12)
The signal generation circuit
Generate a signal containing the period of the plurality of data on the word line.
The arithmetic circuit
The generated address is subjected to an operation using the period to generate the address of the data adjacent to the dimension direction to be read.
The controller according to (11) above.
(13)
The arithmetic circuit is an addition circuit that adds the value to the address.
The controller according to any one of (10) to (12).
(14)
The arithmetic circuit is a subtraction circuit that subtracts the value from the address.
The controller according to any one of (10) to (12).
(15)
The data has an n-bit word structure and has an n-bit word structure.
The period of the plurality of data adjacent to each other in the first dimensional direction on the word line is 0, and the period is 0.
The period of a plurality of data adjacent to the second dimensional direction orthogonal to the first dimensional direction on the word line is n.
The controller according to (11) above.
(16)
The data has a two-dimensional structure.
The controller according to (15) above.
(17)
The period of a plurality of data adjacent to the third dimensional direction orthogonal to the first dimensional direction and the second dimensional direction on the word line is 1.
The controller according to (15) above.
(18)
The data has a three-dimensional structure.
The controller according to (17) above.
(19)
This is a method of reading a plurality of data adjacent to each other in an arbitrary dimensional direction from a memory array in which data having a multidimensional structure is arranged one-dimensionally on a word line by specifying one address.
Generate an address on the word line that is the starting point of the read operation,
A predetermined operation is performed on the generated address to generate an address of data adjacent to the dimension direction to be read.
Generates a signal containing values for the dimensional direction to be read
An operation using the value is performed on the generated address to generate an address of data adjacent to the dimension direction to be read.
Method.

1 Semiconductor storage device 100 Bank 101 Memory cell array 110 Memory controller 111 Control unit 111a Address generation circuit 111b Signal generation circuit 121 Column decoder 122 Low decoder 123 Sense amplifier / write amplifier 131-134 Adder BL bit line MC semiconductor storage element WL word line

Claims (19)

A memory array in which data with a multidimensional structure is arranged in one dimension on a word line,
A controller capable of reading a plurality of data adjacent to each other in an arbitrary dimensional direction from the memory cell array with a single address designation is provided.
The controller
An address generation circuit that generates an address on the word line that is the starting point of the read operation,
An arithmetic circuit that performs a predetermined operation on the generated address to generate an address on the word line of data adjacent to the dimension direction to be read.
A signal generation circuit that generates a signal including a value used in the calculation is provided.
Semiconductor storage device. The plurality of data adjacent to each other in an arbitrary dimensional direction are arranged on the word line at a predetermined period.
The semiconductor storage device according to claim 1. The signal generation circuit
Generate a signal containing the period of the plurality of data on the word line.
The arithmetic circuit
The generated address is subjected to an operation using the period to generate the address of the data adjacent to the dimension direction to be read.
The semiconductor storage device according to claim 2. The arithmetic circuit is an addition circuit that adds the value to the address.
The semiconductor storage device according to claim 1. The arithmetic circuit is a subtraction circuit that subtracts the value from the address.
The semiconductor storage device according to claim 1. The data has an n-bit word structure and has an n-bit word structure.
The period of the plurality of data adjacent to each other in the first dimensional direction on the word line is 0, and the period is 0.
The period of a plurality of data adjacent to the second dimensional direction orthogonal to the first dimensional direction on the word line is n.
The semiconductor storage device according to claim 2. The data has a two-dimensional structure.
The semiconductor storage device according to claim 6. The period of a plurality of data adjacent to the third dimensional direction orthogonal to the first dimensional direction and the second dimensional direction on the word line is 1.
The semiconductor storage device according to claim 6. The data has a three-dimensional structure.
The semiconductor storage device according to claim 8. A controller that can read multiple data adjacent to each other in an arbitrary dimensional direction with a single address specification from a memory array in which data having a multidimensional structure is arranged one-dimensionally on a word line.
An address generation circuit that generates an address on the word line that is the starting point of the read operation,
An arithmetic circuit that performs a predetermined operation on the generated address to generate an address on the word line of data adjacent to the dimension direction to be read.
A signal generation circuit that generates a signal including a value used in the calculation is provided.
controller. The plurality of data adjacent to each other in an arbitrary dimensional direction are arranged on the word line at a predetermined period.
The controller according to claim 10. The signal generation circuit
Generate a signal containing the period of the plurality of data on the word line.
The arithmetic circuit
The generated address is subjected to an operation using the period to generate the address of the data adjacent to the dimension direction to be read.
The controller according to claim 11. The arithmetic circuit is an addition circuit that adds the value to the address.
The controller according to claim 10. The arithmetic circuit is a subtraction circuit that subtracts the value from the address.
The controller according to claim 10. The data has an n-bit word structure and has an n-bit word structure.
The period of the plurality of data adjacent to each other in the first dimensional direction on the word line is 0, and the period is 0.
The period of a plurality of data adjacent to the second dimensional direction orthogonal to the first dimensional direction on the word line is n.
The controller according to claim 11. The data has a two-dimensional structure.
The controller according to claim 15. The period of a plurality of data adjacent to the third dimensional direction orthogonal to the first dimensional direction and the second dimensional direction on the word line is 1.
The controller according to claim 15. The data has a three-dimensional structure.
The controller according to claim 17. This is a method of reading a plurality of data adjacent to each other in an arbitrary dimensional direction from a memory array in which data having a multidimensional structure is arranged one-dimensionally on a word line by specifying one address.
Generate an address on the word line that is the starting point of the read operation,
A predetermined operation is performed on the generated address to generate an address of data adjacent to the dimension direction to be read.
Generates a signal containing values for the dimensional direction to be read
An operation using the value is performed on the generated address to generate an address of data adjacent to the dimension direction to be read.
Method.

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