JP2001243793A - Test pattern generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor test device being compact and having high test efficiency. SOLUTION: A scrambler 12 is formed by a logic circuit being programmable such as FPGA. When a semiconductor memory 50 is tested, the prescribed conversion regulation in converting logic address to a physical address is read out from a conversion program storage device 14, the conversion regulation is converted to HDL data forming a logic circuit in the scrambler 12 by a write data generating circuit 16. The HDL data is written in the scrambler 12 by a write-in circuit 18, and the logic circuit is structured. Thereby, a logic address from an ALPG 10 is converted to a physical address by the scrambler 12 and is supplied to a semiconductor memory 50 to be tested, and a test is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a test pattern generator, and more particularly to, for example, a DRAM (Dynamic random ac).
The present invention relates to a test pattern generator suitable for use in a semiconductor test apparatus for testing a semiconductor memory such as a cess memory.

[0002]

2. Description of the Related Art For example, in a semiconductor test apparatus for testing a semiconductor memory such as a DRAM, it has been confirmed that the value of one cell is not affected by the value of the surrounding cells in the physical arrangement of each memory cell of the semiconductor memory. For this purpose, predetermined data is written to and read from each memory cell, and whether or not the read data is normal is checked. In this case, for example, a DRAM serving as a semiconductor memory to be tested has a unique physical address corresponding to a cell arrangement for each memory, with respect to a logical address commonly used for the memories according to the manufacturer or type. For this reason, a semiconductor test apparatus that tests various semiconductor memories requires a test pattern generator that converts a common logical address into a physical address corresponding to each semiconductor memory under test and supplies the physical address.

Conventionally, as a test pattern generator applied to the above-described semiconductor test apparatus, for example, there has been one shown in FIG. 7 or FIG. The test pattern generator shown in FIG. 7 generates an ALPG (algorithmic logic pattern generator) that generates a regular logical address AX according to the test order and predetermined data to be written to the semiconductor memory under test.
tor) 100 and the logical address AX from the ALPG 100
RAM (random access memory) (SCRAM) 10 for storing an address scramble table for converting the data into a physical address BX of the corresponding semiconductor memory under test.
2, a conversion program storage device 104 in which a predetermined conversion rule corresponding to the semiconductor memory under test is stored in advance, and a control circuit including a logical operation circuit for generating an address scramble table to be stored in the scramble RAM 102 based on the conversion rule And a control circuit 106 for controlling writing of the generated scramble table to the scramble RAM 102 and input / output of the data.

In such a configuration, first, before starting the test, a conversion program representing a predetermined conversion rule for converting a logical address of the semiconductor memory 500 to be tested into a physical address is generated, and the conversion program is stored. Apparatus 1
04 in advance. Next, when testing
The control circuit 106 reads the conversion program stored in the conversion program storage device 104, activates the logical operation circuit based on the conversion program, and generates an address scramble table. The generated address scramble table is transmitted from the control circuit 106 to the scramble RA.
The data is sequentially written to M102, so that the test can be started.

Next, when the test is started, ALPG10
0 is activated, and logical addresses AX corresponding to the test order are sequentially generated and supplied to the scramble RAM 102. Next, the scramble R receiving the logical address AX
The AM 102 reads the corresponding physical address BX from the address scramble table based on the value and supplies the read physical address BX to the semiconductor memory under test 500. As a result, predetermined physical addresses of the semiconductor memory under test 500 are sequentially accessed, and data writing or reading from the ALPG 100 is executed, and the normality of each memory cell of the semiconductor memory under test 500 is tested.

In the test pattern generator shown in FIG. 7, if the semiconductor memory under test has a large capacity, a large capacity of the scramble RAM 102 is required. For example, when testing a (16M × 4) -bit semiconductor memory, a 24-bit logical address A
A RAM for storing address scramble data (16M × 24 bits) for converting X to a 24-bit physical address BX is required. In this case, scramble RAM
The RAM used for the RAM 104 is a static RAM (SRAM) or a flash EEPROM (electr
rically erasable and programmable ROM). For example, when a 512K × 16-bit SRAM is applied, 64 scrambling RAMs 104
RAM was needed.

Therefore, the test pattern generator shown in FIG. 8 has a configuration in which selectors 200 and 202 are used to reduce the number of RAMs. First selector 200
Is a selection circuit using 12 logics of 24-bit input and 1-bit output, selects 12 bits (RX) from a 24-bit logical address AX, and supplies the selected address to the scrambling RAM 204 for row address. Similarly, the second selector 202 is a selection circuit using 12 pieces of 24to1 logic, and 12 bits (C
X) to select a scramble R for column address generation
Supply to AM206. Each scramble RAM
204 and 206 are formed of, for example, 512K × 16-bit SRAM.

In this case, the control circuit 208 switches the selectors 200 and 202 based on the conversion program to select the bit RX used for the row address conversion and the bit CX used for the column address from the logical address AX. The scrambling table 204 for converting the selection bit RX from the first selector 200 into the physical address RBX of the row address is stored in the row address scrambling memory 204, and the second selector is stored in the column address scrambling memory 206. 2
A scramble table for converting a selection bit CX from 02 into a physical address CBX of a column address is stored.

[0009]

As described above, FIG.
According to the conventional technique shown in the above, when the capacity of the semiconductor memory under test increases, the data amount of the address scramble table stored in the scramble RAM 102 increases, the number of SRAMs used increases, and the device becomes larger. There was a problem. Further, when the data amount of the scramble table increases, it takes a long time to perform the calculation and write the data, and there is a problem that the test efficiency is deteriorated.

On the other hand, in the circuit shown in FIG.
8 has to execute both the switching control of the selectors 200 and 202 and the data control of the scramble RAMs 204 and 206, and there is a problem in that the control thereof is complicated. In addition, there is a problem that the conversion rule from the logical address to the physical address in the scramble RAMs 204 and 206 is restricted, so that it may not be applicable to a complicated conversion pattern. Furthermore, when the capacity of the semiconductor memory under test becomes large, the number of logics of the selectors 200 and 202 increases, and there is a problem that the device becomes large.

The present invention has been made in view of the above circumstances. Even when the capacity of a semiconductor memory under test is increased, it is not necessary to increase the size of the apparatus and the test can be efficiently executed. It is an object to provide a test pattern generator that can perform the test.

[0012]

According to the present invention, there is provided a test pattern generator for generating a predetermined test pattern corresponding to each device under test when testing the device under test. In the generator, a logic pattern generating means for generating a regular logic pattern common to each device under test in accordance with a predetermined algorithm; Pattern conversion means for converting a combination of a plurality of logic gates into a logic circuit which can be freely rearranged, and a logic pattern common to each device under test from the logic pattern generation means. The prescribed conversion rule when converting to the prescribed test pattern corresponding to each device under test is The conversion rule storage means and the conversion rule corresponding to the device under test are read from the conversion rule storage means, and construction data for constructing a combination of logic gates of the pattern conversion means is generated based on the conversion rule. It is characterized by including data generating means and data rewriting means for supplying construction data from the data generating means to the pattern converting means to execute rearrangement of logic gates according to the device under test.

In this case, the test pattern generator according to the present invention is used as an address generator for generating an address signal for accessing and testing each address of a semiconductor memory having a predetermined address space as a device under test. And the test pattern generating means includes:
A logical address common to the semiconductor memory to be the device under test is generated in a predetermined order, and the pattern conversion means converts the logical address from the test pattern generation means to a physical address corresponding to each semiconductor memory to be the device under test. Convert it.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a test pattern generator according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a test pattern generator according to the present invention. The test pattern generator according to the present embodiment is, for example, a dynamic random access memory (DRAM).
and a pattern generator applied to a semiconductor test apparatus for testing a semiconductor memory such as a semiconductor memory under test. In particular, in this embodiment, a scrambler for converting a logical address AX from the ALPG 10 into a physical address BX corresponding to the semiconductor memory under test. The main feature of the bra 12 is that it is formed by a logic circuit that can freely rearrange a combination of a plurality of logic gates.

More specifically, as shown in FIG. 1, the test pattern generator according to the present embodiment has an ALPG (algorithmic logic unit).
ogic patern generator) 10, a scrambler 12,
It includes a conversion program storage device 14, a write data generation circuit 16, and a data write control circuit 18.

The ALPG 10 is a logic pattern generation circuit for regularly generating a predetermined logic pattern according to a predetermined algorithm. In this embodiment, for example, a logic address AX common to an N-bit semiconductor memory is reduced to a predetermined number of bits. Is a logical address generation circuit sequentially generated from address 0 to address N. Further, as described later, the data line includes a data line which generates data to be written to the semiconductor memory under test together with the logical address AX and takes in the data from the semiconductor memory under test when reading data. An address line for supplying the logical address AX is connected to the scrambler 12.

The scrambler 12 uses the logical address AX from the ALPG 10 as the target semiconductor memory 50 to be tested.
Is a logic circuit that converts a combination of a plurality of logic gates freely, for example, an FPGA.
(field programmable gate array) or PLD (pro
A programmable logic circuit such as a grammable logic device is advantageously applied.

More specifically, as shown in FIG. 2, for example, the scrambler 12 of this embodiment has a logic circuit including a logic gate LG having two inputs and one output, a flip-flop FF, and a plurality of selectors SE. Logical module LM including a plurality of logical blocks LB with block LB as a minimum unit
Are integrated circuits mounted with a storage circuit MM such as an SRAM in which control data for controlling connection between modules and blocks and input / output of data is stored. As control data for programming a combination of logic gates by defining connections between blocks and between modules, for example, HDL (hardware descriptor)
n language) data etc. are advantageously applied.

Returning to FIG. 1, the conversion program storage device 1
Reference numeral 4 denotes a conversion rule storage circuit in which a predetermined conversion rule for converting the logical address AX into the physical address BX by the scrambler 12 is stored in advance. In the present embodiment, a combination of logic gates in the scrambler 12 is used. For example, a source program for generating HDL data at the time of constructing is stored. The source program representing the conversion rule is read out by the write data generation circuit 16 during the test.

The write data generation circuit 16 is a data generation circuit that generates construction data for constructing a combination of logic gates in the scrambler 12 based on the conversion rule from the conversion program storage circuit 14. Then, for example, HDL data for constructing a combination of logic gates is generated by a source program read from the conversion program storage circuit 14. The generated HDL data is supplied to the write control circuit 18.

The write control circuit 18 writes, for example, HDL data generated by the write data generation circuit 16 at the time of the test into the storage circuit MM of the scrambler 12, and
This is a data rewriting circuit that executes the rearrangement of the logic gate.

Next, the operation of the test pattern generator according to the present embodiment will be described with reference to FIGS. In addition,
3 to 5, in order to facilitate understanding of the operation of the test pattern generator according to the present embodiment, a case where the semiconductor memory under test 50 has a (4 × 4) bit address space will be described as an example. I do.

First, before starting the test, the logical address AX to the semiconductor memory 50 to be tested is changed to the physical address BX.
A conversion program representing a predetermined conversion rule when converting to is generated and stored in the conversion program storage device 14 in advance. In this case, the logical address AX is represented by four bits (X0, X1, Y0, Y1) as shown in FIG. 4, and the addresses from address 0 to address 16 are sequentially and regularly output. As shown in FIG. 5, the physical address BX is represented by four bits (BX0, BX1, BY0, BY1), and the value of the ninth and subsequent BX0 bits differs from the X0 bit of the logical address AX. It has become.

That is, the BX0 bit of the physical address BX is a value obtained by inverting the X0 bit when the value of the Y1 bit of the logical address AX becomes "1". The other bits BX1, BY0 and BY1 of the physical address BX have the same values as the corresponding X1, Y0 and Y1 bits of the logical address AX. Thus, the conversion equation from each bit of the logical address AX to each bit BX0, BX1, BY0, BY1 of the physical address BX is as shown in FIG.
It is represented as In this FIG. 6, Exor is:
Indicates exclusive OR.

Next, the conversion program representing the above conversion rule is stored in the conversion program storage device 1 at the time of testing.
4 to the write data generation circuit 16. As a result, the write data generation circuit 16 performs the exclusive OR operation on the X0 bit and the Y1 bit of the logical address AX and inputs the logical address A
It generates HDL data for constructing the second to fourth logic gates that output the X1, Y0, and Y1 bits of X as they are, and supplies the result to the write control circuit 18.

Next, the write control circuit 18 having received the HDL data writes the HDL data into the storage circuit MM of the scrambler 12. Thereby, as shown in FIG.
A first logic gate G1 which inputs the X0 bit and Y1 bit of the logical address AX to the scrambler 12 and takes an exclusive OR thereof and outputs the result as the BX0 bit of the physical address BX;
The second to fourth logic gates G2, G3, and G4 that output the BX1, BY0, and BY1 bits of the physical address BX with the 0 and Y1 bits as they are are constructed. In this case, the second to fourth logic gates G2, G
Transfer gates 3 and G4 output the input data as they are.

When the logic circuit of the scrambler 12 is constructed as described above, the test can be started. Next, when the test is started, the ALPG 10 is activated,
As shown in FIG. 4, the logical addresses AX are sequentially generated and supplied to the scrambler 12, and the respective addresses AX
At the same time, data D1 to D16 are generated and sequentially supplied to the semiconductor memory under test 50.

Next, in the scrambler 12 to which the logical address AX has been input, the first logical gate G1 performs an exclusive OR operation on the X0 bit and the Y1 bit of the logical address AX, and converts the value to the physical address BX. The BX0 bit is supplied to the semiconductor memory under test 50, and the second logic gate G2
The X1 bit of the logical address AX to the physical address BX
Is supplied to the semiconductor memory under test 50 as the BX1 bit of Similarly, in the third logical gate G3, the Y0 bit of the logical address AX is set to the BY0 bit of the physical address BX, and in the fourth logical gate G4, the Y0 of the logical address AX is set.
One bit is supplied to the semiconductor memory under test 50 as the BY1 bit of the physical address BX.

As a result, the logical address AX corresponds to the physical address BX shown in FIG.
And are sequentially supplied to the semiconductor memory 50 under test. The semiconductor memory under test 50 receiving the physical address BX
In this case, the BX0 and BX1 bits are decoded by the column address decoder 500, a control signal for activating the column address represented by the result is supplied to the memory cell 504, and the BY0 and BY1 bits are converted to the row address decoder 502. And a control signal for activating the row address represented by the result is applied to memory cell 504.
Are supplied sequentially. As a result, the cells specified by the column and row addresses are sequentially accessed, and the data D1 to D16 supplied from the ALPG 10 are written in the respective cells.

Next, when data D1 to D16 are written in each of the memory cells 504 of the semiconductor memory under test 50, a logical address AX for reading data from the ALPG 10 is generated in the same manner as described above. Then
As described above, the logical address AX is stored in the scrambler 12.
Is converted into a physical address BX and supplied to the semiconductor memory under test 50 to access each of the memory cells 504. As a result, data D1 to D16 are sequentially read from the accessed cell and
0, the written data and the read data are compared to check whether each cell of the semiconductor memory under test 50 is normal.

Thereafter, if the physical address of the semiconductor memory under test is the same, the logical address AX from the ALPG 10 is converted into the physical address BX by the scrambler 12 formed in the same manner as described above, and Test the memory. On the other hand, when testing another semiconductor memory under test having a different physical address, a conversion program representing the conversion rule is written in the conversion program storage device 14 as described above, and the write data generation circuit 16 is written based on the conversion program. Generates the construction data represented by the conversion rule, and writes the construction data to the scrambler 12 via the write control circuit 18. Thereby, each logic gate for converting the logical address AX from the ALPG 10 into the physical address BX corresponding to the semiconductor memory under test is constructed in the scrambler 12, and the test according to the semiconductor memory under test is performed.

As described above, according to the test pattern generator of the present embodiment, the scrambler 1 formed of a logic circuit in which a combination of a plurality of logic gates can be freely rearranged.
Since the logical address AX from the ALPG 10 is converted into the physical address BX corresponding to the semiconductor memory 50 under test in 2, the conversion can be performed freely and at high speed. Further, a scrambler 1 according to the semiconductor memory under test is used.
When the rearrangement of the two logic gates is performed, the construction data according to the conversion rule can be executed in a short time by one rewriting, and the test can be efficiently performed when testing various semiconductor memories under test. Can be performed. Further, when testing a large-capacity semiconductor memory under test, it is highly integrated in the scrambler 12, for example, F
By applying PGA, it is possible to reduce the size of the device and efficiently execute the test with low power consumption.

In the above embodiment, the case where a logical address to a semiconductor memory such as a DRAM as a device under test is converted into a physical address has been described as an example.
The present invention may be applied to a test pattern generator for testing another semiconductor device, for example, a logic LSI or the like.

[0034]

As described above, according to the test pattern generator of the present invention, the logic pattern generation means is formed by the pattern conversion means formed by a logic circuit capable of freely changing the combination of a plurality of logic gates. Is converted into a predetermined test pattern corresponding to each device under test, so that the conversion can be performed freely and at high speed. Further, when the logic gates of the pattern conversion means are rearranged in accordance with the device under test, the construction data according to the conversion rule can be executed in a short time by one rewriting, and various devices under test can be executed. The test can be executed efficiently when testing. Further, by applying a highly integrated, for example, FPGA as the pattern conversion means, it is possible to obtain excellent effects such as downsizing of the device and efficient execution of the test with low power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a test pattern generator according to the present invention.

FIG. 2 is a circuit configuration diagram showing a main part of the test pattern generator according to the embodiment of FIG.

FIG. 3 is a block diagram for explaining an operation of the test pattern generator according to the embodiment of FIG. 1;

FIG. 4 is a diagram for explaining an operation of the test pattern generator according to the embodiment of FIG. 1;

FIG. 5 is a diagram for explaining an operation of the test pattern generator according to the embodiment of FIG. 1;

FIG. 6 is a diagram showing a conversion formula from a logical address to a physical address of the test pattern generator of the embodiment of FIG. 1;

FIG. 7 is a block diagram showing an example of a conventional test pattern generator.

FIG. 8 is a block diagram showing an example of a conventional test pattern generator.

[Explanation of symbols]

 Reference Signs List 10 ALPG 12 Scrambler 14 Conversion program storage device 16 Write data generation circuit 18 Data write control circuit

Claims (2)

[Claims] 1. A test pattern generator for generating a predetermined test pattern corresponding to each device under test when testing the device under test, comprising: a regular logic pattern common to each device under test according to a predetermined algorithm. And a pattern conversion means for converting the logic pattern from the logic pattern generation means into a predetermined test pattern corresponding to each device under test, comprising a combination of a plurality of logic gates. A pattern conversion means (12) formed of a logic circuit capable of freely re-arranging the logic patterns, and a predetermined test pattern corresponding to each device under test by converting a logic pattern common to each device under test from the logic pattern generation means. Conversion rule storage means (14) in which a predetermined conversion rule for converting to a conversion rule is stored; Data generating means (16) for reading a conversion rule corresponding to a device under test from the stage and generating construction data for constructing a combination of logic gates of the pattern conversion means based on the conversion rule; A data rewriting means (18) for supplying construction data from the means to the pattern conversion means and executing rearrangement of logic gates according to a device under test. 2. The test pattern generator according to claim 1, wherein said test pattern generator accesses each address of a semiconductor memory having a predetermined address space as a device under test to test. An address generator for generating a signal, wherein the logical pattern generating means generates a logical address common to a semiconductor memory to be a device under test in a predetermined order according to a test; A test pattern generator for converting a logical address from a pattern generating means into a physical address corresponding to each semiconductor memory to be a device under test.