SU1108507A1 - Storage with multiformat data access - Google Patents

Abstract

A STORAGE DEVICE WITH DIFFICULTY ACCESS TO DATA, containing a call type register, an address register, a first modulo two, a matrix memory block, a multiplexer and a data register, the output of the type register of appeals is connected to one of the inputs of the first modulo two, the Output of which connected to the first address input of the matrix memory block; the output of the register of the address is connected to the second input of the first modulo two adder and the second address input of the matrix memory block, the information output of which is I differ from the input of the multiplexer, the output of which is connected to the input of the data register; In order to expand the application area of the device by providing three-dimensional data access, additional matrix memory blocks and multiplexers are entered into it, the column number register, the second and third modulators two, the mode trigger, the memory matrix number register these, the first and second decoders, with the first address inputs of additional matrix memory blocks connected to the output of the first modulo adder two, the second address inputs to the output of the address register and to the first input of the second adder Two of them, the output of which is connected to the input of the first decoder, with the first control inputs of the multiplexers and with the first input of the third modulo two adder, the output of which is connected to the second control inputs of the multiplexers, the information outputs of the additional multiplexers are connected to the inputs of the data register, the information inputs - to the corresponding outputs of the additional matrix memory blocks, the direct output of the mode trigger is connected to the second input of the third modulo Q two and the gate input ne This decoder, the outputs of which are connected to the third address inputs of the matrix memory blocks, the inverse of the output of the mode trigger is connected to the gate input of the second decoder, the input of which is connected to the output of the memory matrix number register, and the outputs are connected to the fourth address inputs of the matrix memory blocks, the output of the register number of the column is connected to the second input of the second adder modulo two.

Description

f1 The invention relates to computing technology, in particular, to hiUHaiOBgHM devices, and can be used in specialized storage systems and digital image processing, as well as in associative computing systems. A multi-format data access memory device is known that contains a memory block and diagonal addressing tools that allow storing two-dimensional binary arrays with the possibility of parallel access to their rows and columns. The disadvantage of this device is high hardware costs. The closest technical solution to the invention is an associative a memory device containing a register of the type of references, an address register, a modulo two adder, a multiplexer block, a data register and a memory block, The output of the register of the reference type is connected to one of the inputs of the modulo two adder, the output of which is connected to the first 1M address input of the memory block, the output of the register of the address register is connected to the control input of the data multiplexer unit, the second input of the modulo two adder and the second address input of the memory block ti, the output of which is connected via a multiplexer unit with a data register. The memory block of this device is built on integrated memory chips with a capacity of Z bits each, where R 1,2,3, .... Dp information storage is used W memory integrated circuits (). To implement multi-format (to rows and columns) access, elements of a memorized matrix (binary array W W) are placed in an integrated memory chip in such a way that all elements of any row or column fall into different memory chips. This provides the ability to simultaneously select an arbitrary row or column. To describe the correspondence between the elements of the memorized matrix, the integral numbers of the memory chips, and the addresses in them, we introduce the following notation: J, I is the column number, rows of the memorized matrix: J O-J- (W-I); (W-1); N is the number of the integrated memory chip, N Or (W-l); A-R is the bit address that determines the selection of a bit in one memory chip, S is the type of access, S O is (W-1). Specific values of J, I, N, A, S can be considered as binary vectors and denoted respectively J, I, N А, S. In the following, we use the bitwise operations of the conjunction L, disjunction V, addition modulo two @ and negation - over binary vectors. Each binary element of the memorized matrix with coordinates I, J is stored in a memory chip, the code of which is determined from the relation: © J Two buses X and Y are used to feed the addresses to the memory chips. The bus X supplies the address code (X) with the device address register, and the Y bus receives the code (Y) from the output of an adder modulo two, to the input of which X and S are entered, i.e. Y S. Such a connection provides S with various methods of addressing, and at 3,000 ... .0 a reference occurs to the rows of the memorized matrix, and when S.S 111 ... 1 - to the columns of the memorized matrix. The row and column number is given by code X. Expression (1), which defines the distribution of row elements (columns) across memory chips, indicates that the order of the elements on the data bus of the memory block is different for different rows (columns). This order for the row (column) with the number I (J) is determined by the corresponding dyadic (modulo two) shift. In order to ensure unambiguous ordering when sampling any row (column) in a device, a data multiplexer consisting of logjW groups is used. Each group implements a permutation of row (column) elements corresponding to the dyadic shift of a certain 2 °, 2 2, ..., order . The inclusion control of data multiplexer groups is controlled depending on the state of the bits in the address register 21. A disadvantage of this device is the impossibility of implementation

a three-dimensional storage medium in which, along with multi-format accesses to the elements of the memory bit-matrix, access to words whose K-bits are distributed in the bit-memory matrices is allowed, which limits the scope of application of the device.

The aim of the invention is to expand the scope of storage device with multi-format access to data by providing the ability to store three-dimensional bit data array (two-dimensional array of multi-bit data) and organize three-dimensional access to them: to rows and columns of any matrix, as well as words dy, which are distributed in all memory matrices.

The goal is achieved by the fact that in a memory device with multi-format data access, containing a register of the type of accesses, a register-address, the first modulo two adder, a multiplexer, a data register and a matrix memory block, the output of the register of the type of accesses connected to one of the the inputs of the first modulo-two adder, the output of which is connected to the first address input of the matrix memory block, the output of the address register is connected to the second input of the first modulo-two adder and the second address input of the matrix memory block, the formation output of which is connected to the multiplexer input, the output of which is connected to the data register input, additional matrix memory blocks and multiplexers are entered, the column number register, the second and third modulo-two adders, the mode trigger, the memory matrix number register and the first and second decoders The first address inputs of the additional matrix memory blocks are connected to the output of the first modulo-two adder, the second address inputs to the output of the address register and to the first input. second modulo two, the output of which is connected to the input of the first decoder, with the first control inputs of the multiplexers and with the first input of the third modulator two, the output of which is connected to the second control inputs

multiplexers, the information outputs of the additional multiplexers are connected to the data register inputs, the information inputs to the corresponding outputs of the additional matrix memory blocks, the direct output of the mode trigger is connected to the second input of the third modulo two and the gate inputs of the first decoder, the outputs of which are connected to the third address the inputs of the matrix memory blocks, the inverse output of the mode trigger is connected to the gate input of the second depotfratora, whose input is connected to the output of the register Omera of the memory matrix, and the outputs are connected to the fourth address inputs of the matrix memory blocks, the output of the register of the column number is connected to the second input of the second modulo-two adder.

FIG. 1 shows a block diagram of the device; in fig. 2 - three main types of requests corresponding to the three-dimensional organization of data access; in fig. 3 is a diagram of the orhH3ai9iH resolution signals in a matrix memory block; FIG. 4 - connection scheme of control inputs of multiplexers.

A memory device with multi-format data access (see FIG. T) contains a type 1 register

5 hits, the first adder 2 modulo two, register 3 addresses, matrix memory blocks A, multiplexers 5, data register 6, first decoder 7, register 8 column numbers,

0 second adder 9 modulo two, trigger 10 mode, the third adder 11 modulo two, register number 12 matrix, the second decoder 13.

D5 Consider the operation of the device in the mode of addressing the rows (columns) of the matrix 1 to 1 (see Fig. 2 a, b). Before starting, the trigger 10 of the operation mode is set to O.

jQ. is set the type of call (code S is written in register of type 1 calls), sets the address of the call (code X is written in register 3 of addresses), sets the number of matrill to which the call should occur (code to write to register 12), and zero register 8 column numbers. The kth output of the decoder 13 permits operation with the corresponding memory matrix. The scheme of enabling signals inside the memory block may be, for example, such as shown at 4 mg. 3, i.e. containing the element OR 1A and the memory chip 15 (circuit for dl). At the same time, the first address input of blocks 4 receives a code, and the second - code X, which is stored in the address register 3. It is determined which code is fed in the considered mode to the control inputs of the multiplexers. The control inputs of each elementary multiplexer are designated 16-23 and are part of multiplexer 5,, fgjj, fp (fig. These inputs are connected to the corresponding buses L 1 (1,) t which are the second control inputs of the multiplexer, if The bits of the matrix number code., KC-I, ..., KO are one, and the remaining inputs are connected to the corresponding buses, which are o-1 to-2 first control inputs of the multiplexers. This connection is described by the expression: F () Since NJ, where there are 3 addresses in the register, the code that is in register 8, the column number (in this mode J 0 ... 0), and the code received on the output of the second adder 9 for fashion two, then N X. In addition, L and N ® Q, where L is the code at the output of the third adder And modulo two, and the code obtained by replicating the output of the trigger 10 of the operation mode by R bits (in the considered case Q O ... 0). Consequently, L - X. 1 X and N Substituting the values of X in (2 ), get F Xlf This means that the information on the data register falls into a correctly ordered form. Consider the second mode of operation, referring to the K-bit word placed in the K memory matrices (see Fig. 2c). Preliminary, the trigger 10 of the operation mode is set to 1, in the register 8 of the column number the code J is entered, and in the address register 3 the code of the row 1, at the intersection of which the search word is found. In addition, the zero register is a type 1 case. It is known that the block number in which the bit is placed at the intersection of the j-ro column and the i-th row is determined from the expression NG ® J The operation of adding the column number code 5 and the code of row number I is performed by the second adder 9 through module two. The decoder 7, the input of which receives the code N, enables the operation of the circuitry of all memory blocks with the number N, and the code in register 1 of the type S 00 ... O, and the code 1 of the row number provides the address corresponding to the first line to this block. Codes that match multiplexers are determined. Since L - Q, where ... 1 (in this mode), then L N razhesh {e (2) has the form F N) V (K N). From (3). An example for W 8, 1 3, 3 4 is illustrated in FIG. 4. The use of the proposed storage device with multi-format data access allows building up memory matrices and working with a two-dimensional array of multi-bit data, using all the handling methods for any bit layer as in the prototype. In addition, the device allows to refer to words whose bits are placed in all memory matrices. It can be used in systems of digital image processing or other multidimensional information arrays where there is a need to refer to both a single word and the string or the pillar of any bit layer of an array of words. In this case, the number of memory accesses can be significantly reduced. The device allows to obtain qualitatively new possibilities of automatic (without using processor resources) conversion of presentation forms due to a small increase in equipment.

data. Thus, for example, a memory device storing a two-dimensional array of multi-word words, in addition to the possibility of address sampling of a word, makes it possible to refer to any bit slice of a set of words constituting a row or column of a two-dimensional array.

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Claims (1)

A MEMORY DEVICE WITH MULTI-FORMATTED DATA ACCESS, containing a call type register, an address register, a first adder modulo two, a matrix memory block, a multiplexer and a data register, the output of a call type register being connected to one of the inputs of the first adder modulo two, the output of which is connected with the first address input of the matrix memory block, the output of the address register is connected to the second input of the first adder modulo two and the second address input of the matrix memory block, the information output of which is connected to multiplexer house, the output of which is connected to the input of the data register, characterized in that, in order to expand the scope of the device by providing three-dimensional access to data, additional matrix memory blocks and multiplexers, a column number register, second and third adders are introduced into it module two, mode trigger, register of memory matrix number, first and second decoders, the first address inputs of additional matrix memory blocks connected to the output of the first adder modulo two, the second address inputs - to the output of the address register and to the first input of the second adder modulo two, the output of which is connected to the input of the first decoder, with the first control inputs of the multiplexers and the first input of the third adder modulo two, the output of which is connected to the second control inputs of the multiplexers the outputs of the additional multiplexers are connected to the inputs of the data register, the information inputs are connected to the corresponding outputs of the additional matrix memory blocks, the direct output of the mode trigger is connected to the second by the third adder modulo two and the gate input of the first decoder, the outputs which are connected to the third address inputs of the matrix memory blocks, the inverse output of the mode trigger is connected to the gate input of the second decoder, the input of which is connected to the register output of the memory matrix number, and the outputs are connected to the fourth address inputs of the matrix blocks of memory, the output of the column number register is connected to the second input 1108507 A second adder modulo two. f 1108507