JPS61121072U - - Google Patents
Info
- Publication number
- JPS61121072U JPS61121072U JP488585U JP488585U JPS61121072U JP S61121072 U JPS61121072 U JP S61121072U JP 488585 U JP488585 U JP 488585U JP 488585 U JP488585 U JP 488585U JP S61121072 U JPS61121072 U JP S61121072U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- pulse
- circuit
- synchronization
- obtaining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Synchronizing For Television (AREA)
Description
第1図及び第2図は夫々本考案回路の第1実施
例のブロツク系統図及び信号波形図、第3図及び
第4図は夫々本考案回路の第2実施例のブロツク
系統図及び信号波形図、第5図及び第6図は夫々
従来回路の一例のブロツク系統図及び信号波形図
である。
1……複合同期信号入力端子、7,12〜15
……モノマルチ、10……出力端子、11,16
……パルス検出回路。
1 and 2 are block system diagrams and signal waveform diagrams, respectively, of the first embodiment of the circuit of the present invention, and FIGS. 3 and 4 are block system diagrams and signal waveform diagrams, respectively, of the second embodiment of the circuit of the present invention. 5 and 6 are a block system diagram and a signal waveform diagram, respectively, of an example of a conventional circuit. 1...Composite synchronization signal input terminal, 7, 12-15
...Mono multi, 10...Output terminal, 11, 16
...Pulse detection circuit.
Claims (1)
に夫々対応したパルスを得るパルス検出回路と、
該パルス検出回路の出力の各パルスに同期して水
平同期信号期間の略5/8のパルス幅の第1の信
号を得る回路と、上記複合同期信号の各パルスに
同期して該水平同期信号期間の略3/4のパルス
幅の第2の信号を得る回路と、該第1の信号と該
第2の信号との積によりフレーム検出信号を得る
回路とよりなるフレーム信号検出回路。 a pulse detection circuit that is supplied with a composite synchronization signal and obtains pulses corresponding to respective vertical synchronization pulse positions;
a circuit for obtaining a first signal having a pulse width of approximately 5/8 of the horizontal synchronization signal period in synchronization with each pulse of the output of the pulse detection circuit; and a circuit for obtaining the horizontal synchronization signal in synchronization with each pulse of the composite synchronization signal. A frame signal detection circuit comprising: a circuit for obtaining a second signal having a pulse width of approximately 3/4 of a period; and a circuit for obtaining a frame detection signal by multiplying the first signal and the second signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP488585U JPS61121072U (en) | 1985-01-18 | 1985-01-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP488585U JPS61121072U (en) | 1985-01-18 | 1985-01-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61121072U true JPS61121072U (en) | 1986-07-30 |
Family
ID=30480886
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP488585U Pending JPS61121072U (en) | 1985-01-18 | 1985-01-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61121072U (en) |
-
1985
- 1985-01-18 JP JP488585U patent/JPS61121072U/ja active Pending