JPS6112091A - Multilayer circuit board and method of producing same - Google Patents

Multilayer circuit board and method of producing same

Info

Publication number
JPS6112091A
JPS6112091A JP59131169A JP13116984A JPS6112091A JP S6112091 A JPS6112091 A JP S6112091A JP 59131169 A JP59131169 A JP 59131169A JP 13116984 A JP13116984 A JP 13116984A JP S6112091 A JPS6112091 A JP S6112091A
Authority
JP
Japan
Prior art keywords
glass
circuit board
multilayer circuit
multilayer
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59131169A
Other languages
Japanese (ja)
Inventor
戸崎 博己
平吉 種井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59131169A priority Critical patent/JPS6112091A/en
Publication of JPS6112091A publication Critical patent/JPS6112091A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Landscapes

  • Laminated Bodies (AREA)
  • Glass Compositions (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は多層回路基板及びその製造方法に関する。特に
、ガラスセラミック質絶縁材料を用いた多層回路基板及
びその製造方法に関するものである。′この種の多層回
路基板は、例えば多数のLSIチップを搭載する高集積
化した回路基板として利用される。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multilayer circuit board and a method for manufacturing the same. In particular, the present invention relates to a multilayer circuit board using a glass-ceramic insulating material and a method for manufacturing the same. 'This type of multilayer circuit board is used, for example, as a highly integrated circuit board on which a large number of LSI chips are mounted.

〔発明の背景〕[Background of the invention]

LSIチップを搭載する基板は、従来、アルミナを主材
とする原料シートつまり所謂グリーンシートにタングス
テン等の高融点金属の導体を厚膜技術によシ印刷形成し
、これを積層して多層のグリーンシートとして、これを
約1500℃の高温非酸化雰囲気にて焼結して製造され
ている。
Conventionally, the substrate on which an LSI chip is mounted is made by printing a conductor of a high-melting point metal such as tungsten on a raw material sheet mainly made of alumina, or a so-called green sheet, using thick film technology, and then laminating these sheets to form a multilayer green sheet. It is manufactured as a sheet by sintering this in a high temperature non-oxidizing atmosphere at about 1500°C.

しかしこのようなアルミナ系多層配線基板では、近年特
に情報処理装置の分野等で望まれている演算処理の高速
化に対応するのには充分でないという問題がある。アル
ミナは比誘電率が比較的高く、微細配線タングステン導
体は配線抵抗が高いため、その多層層内の配線を伝播す
る信号遅延時間は、一段と高まった演算処理の高速化の
要求に応え難いからである。このことから、電気抵抗の
低い金属による配線と、誘電率の低い絶縁材料が必要と
されている。
However, such alumina-based multilayer wiring boards have a problem in that they are not sufficient to meet the demands for high-speed arithmetic processing, which has been desired in recent years, particularly in the field of information processing devices. Alumina has a relatively high relative dielectric constant, and fine-wiring tungsten conductors have high wiring resistance, so the signal delay time propagating through the wiring within the multilayer layer is difficult to meet the ever-increasing demands for faster calculation processing. be. For this reason, metal wiring with low electrical resistance and insulating materials with low dielectric constant are required.

上記事情を背景として、高導電性金属即ちAg。Against the background of the above circumstances, highly conductive metals, namely Ag.

Au−、Cu 、 Ag/Pa等約1000℃近辺に融
点を持つ材料を配線に用いることができるように、多層
基板として、絶縁材料にガラス及び結晶化ガラスを用い
ることが提案されている(特開昭51−127112号
)。 また、特開昭54−111517号においては、
α−1−シェラ、イト(MgOIIA1203・S i
 02 )やβ−スIノーメン(Li2O・Al2Os
・5in) を主結晶とする結晶化ガラスセラミックス
が開示されている。これら技術は確かに成る面で従来の
アルミナ系多層基板より有利と考えられる。例えばα−
1−ジェライトやβ−スポジュメンは、その熱膨張係数
が加〜50X10”7℃の範囲にあり、Siチップ(L
SI) o熱膨張係数(約30 X 10−77℃)に
ほぼ合致させることができ、熱膨張の差に由来する接続
部の温度サイクルによる応力破壊を抑えることができる
。またこれらの基板は抗折強度が高く、1500 ky
/cy1以上であシ、これは一般的なガラスの抗折強度
の倍以上あり、これによ5LSIチツプ及び基板に接続
される入出力ビンの基板からの剥離破壊を抑えることが
可能となる。
It has been proposed to use glass and crystallized glass as insulating materials for multilayer substrates so that materials with melting points around 1000°C, such as Au-, Cu, and Ag/Pa, can be used for wiring. (No. 127112, 1973). In addition, in Japanese Patent Application Laid-Open No. 54-111517,
α-1-Sierra, Ito (MgOIIA1203・S i
02 ) and β-sinomen (Li2O・Al2Os
A crystallized glass ceramic whose main crystal is 5in) has been disclosed. These technologies are certainly considered to be more advantageous than conventional alumina-based multilayer substrates. For example α−
1-gelite and β-spodumene have thermal expansion coefficients in the range of +50 x 10"7°C, and are suitable for Si chips (L).
SI) o It is possible to almost match the coefficient of thermal expansion (approximately 30 x 10-77°C), and it is possible to suppress stress fracture due to temperature cycling of the connection portion due to the difference in thermal expansion. In addition, these substrates have high bending strength, 1500 ky
/cy1 or more, which is more than double the bending strength of general glass, making it possible to suppress peeling damage from the substrate of the input/output bin connected to the 5LSI chip and the substrate.

しかしながら、前記した演算処理の高速化という点で考
えるといガラスセラミックスの比誘電率は未だ高く、よ
って多層配線を伝播する信号遅延時間は、未だ充分には
その要求に応え難い。理想的には比誘電率を5以下にし
たく、あるいFi5〜6前後に抑えたいのであるが、こ
の要請は満たされていないのが現状である。また、その
熱膨張率は艶X 10−7/’C以下であυ、140 
X 10 ’/℃以上の” e Ag + Cu 、 
Ag/Pa等の配線導体や、表面層の端子の剥離を生じ
易いという問題がある。よって、LSIとして一般的な
Siチップを用いても、その熱膨張係数である約30X
10−7/”Cと余9差がなくて温度サイクルによって
も接続部に応力破壊が生じず、かつ140 X 10−
7/’C以上の熱膨張係数を有する上記高導電性金属と
も余シ差がなく端子剥離を生じにくい、有利なガラスセ
ラミックス絶縁材料が望まれている。
However, when considering the above-mentioned speed-up of arithmetic processing, the dielectric constant of glass ceramics is still high, and therefore the signal delay time propagating through multilayer wiring still cannot sufficiently meet the demand. Ideally, it would be desirable to have a dielectric constant of 5 or less, or to keep Fi around 5 to 6, but at present this requirement is not met. In addition, its coefficient of thermal expansion is less than X 10-7/'C, υ, 140
X 10'/℃ or more" e Ag + Cu,
There is a problem in that wiring conductors such as Ag/Pa and terminals on the surface layer are likely to peel off. Therefore, even if a general Si chip is used as an LSI, its coefficient of thermal expansion is approximately 30X.
10-7/"C and 9% difference, stress failure does not occur in the connection part even with temperature cycles, and 140 x 10-
An advantageous glass-ceramic insulating material is desired, which has a coefficient of thermal expansion of 7/'C or more, is similar to the above-mentioned highly conductive metals, and is less likely to cause terminal peeling.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、極めて低い誘電率のガラスセラミック
ス絶縁材料を用いることにより信号伝播の遅延速度が極
めて小さくて高速処理に充分対応でき、かつ高抗折性で
強度が高く、熱膨張係数も適当な範囲に選ぶことができ
る、有利な多層回路基板及びその製造方法を提供するに
ある。
The purpose of the present invention is to use a glass-ceramic insulating material with an extremely low dielectric constant, so that the delay speed of signal propagation is extremely small, which is sufficient for high-speed processing, and which has high bending properties, high strength, and an appropriate coefficient of thermal expansion. An object of the present invention is to provide an advantageous multilayer circuit board that can be selected within a wide range of options, and a method for manufacturing the same.

〔発明の概要〕[Summary of the invention]

この目的を達成するため、本願発明の多層回路基板は、
S i 02を66〜79wt%、Li2Oを9〜20
wt% 、 Ad203を3〜10wt%、K2Oを1
〜3wt%およびTj 04あるいはP2O5を3wt
%含むガラス質材料70〜40 w t%に、石英ガラ
ス加〜60 w t%を混合した材料をガラスセラミッ
ク質絶縁材料として用いて回路を多層化して構成する。
In order to achieve this objective, the multilayer circuit board of the present invention includes:
66-79 wt% Si02, 9-20 wt% Li2O
wt%, Ad203 at 3-10 wt%, K2O at 1
~3wt% and 3wt Tj 04 or P2O5
A circuit is multilayered using a material obtained by mixing 70 to 40 wt% of a glass material containing 70 to 40 wt% of silica glass and 60 wt% of silica glass as a glass-ceramic insulating material.

このガラスセラミック質材料は、誘電率が低く、高抗折
性で、熱膨張率も適当な範囲にあり、上記目的にかなう
ものである。
This glass-ceramic material has a low dielectric constant, high refraction, and a coefficient of thermal expansion within an appropriate range, and thus satisfies the above objectives.

本願の他の発明は、このような混合物材料を750〜8
50℃の温度で熱処理して、ガラスセラミック質絶縁材
料として用いる。     −゛へ石英ガラスは極めて
低い比誘電率(約4)と、低い熱膨張係数(約5 X 
10 ”/”C)を有するので、この構成によシ上記ガ
ラス質と石英ガラスとを混合すると、誘電率を低くする
ことができ、またこれにより、熱膨張率を所望の値に調
整することができる。
Another invention of the present application is to use such a mixture material in a range of 750 to 8
It is heat-treated at a temperature of 50° C. and used as a glass-ceramic insulating material. -゛Quartz glass has an extremely low dielectric constant (approximately 4) and a low coefficient of thermal expansion (approximately 5
10"/"C), so by mixing the above-mentioned glass and silica glass with this structure, the dielectric constant can be lowered, and thereby the coefficient of thermal expansion can be adjusted to a desired value. I can do it.

本願の更に別の発明は、上記のような多層配線基板の製
造方法であシ、上記ガラス質と石英ガラスとの混合物を
750〜850℃の結晶析出温度で熱処理し、けい酸リ
チウム(Li2O・2S102)を析出させて結晶化ガ
ラスとし、これをガラスセラミック質絶縁材料として用
い回路を多層化して多層回路基板を得る方法である。こ
の方法によれば、加熱温度は高導電性金属の融点よりも
小さいので、信号伝播を高速化する多層回路基板の製法
として有利である。
Still another invention of the present application is a method for manufacturing a multilayer wiring board as described above, in which a mixture of the glassy material and quartz glass is heat-treated at a crystal precipitation temperature of 750 to 850°C, and lithium silicate (Li2O. In this method, 2S102) is precipitated to form crystallized glass, and this is used as a glass-ceramic insulating material to form a multilayer circuit to obtain a multilayer circuit board. According to this method, since the heating temperature is lower than the melting point of the highly conductive metal, it is advantageous as a method for manufacturing a multilayer circuit board that speeds up signal propagation.

〔発明の実施例〕[Embodiments of the invention]

以下゛、本発明の一実施例について、図面を参照して説
明する。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

本実施例により得られる多層配線基板は、その−例が添
付図面に断面図にて示す構造になっており、図の如くガ
ラスセラミンク質から成る絶縁材料lに所望の配線2が
形成されて回路が多層化されておシ、この配線2は、ビ
ン接続端子3を介してビン5と接続され、また、LSI
接続端子4を介してLSI6と接続されることにより、
LSI6を搭載するようになっている。本実施例で得ら
れるガラスセラミ−ツク質絶縁材料は、例えばこのよう
な構造の多層配線基板として具化化されるのである。
The multilayer wiring board obtained in this example has a structure as shown in the cross-sectional view in the attached drawing, and as shown in the figure, desired wiring 2 is formed on an insulating material l made of glass ceramic. The circuit is multilayered, and this wiring 2 is connected to the bin 5 via the bin connection terminal 3, and the LSI
By being connected to the LSI 6 via the connection terminal 4,
It is equipped with LSI6. The glass-ceramic insulating material obtained in this example is embodied, for example, as a multilayer wiring board having such a structure.

本実施例のガラスセラミックス質絶縁材料は、S 10
2 、 Li2O、Alz 03 、 KlI O、及
びP2O5またけT i 02を成分としてその組成が
第1表の51〜A7に掲げるようにして形成したガラス
質に、石英ガラスを混合して得られたものを用いる。本
実施例においては、このようなガラス質材料を750〜
850℃の温度で熱処理してガラスセラミック質絶縁材
料として用い、かつ、この場合、この熱処理においてけ
い酸リチウム(Ls、 0・2SiO2)を主結晶とし
て析出させて、結晶化ガラスにして用いる。
The glass-ceramic insulating material of this example is S 10
2, Li2O, Alz03, KlIO3, and P2O5-straddling Ti02 as components and the composition was formed as listed in 51 to A7 in Table 1, and vitreous material was mixed with silica glass. use something In this example, such a glassy material is used at 750~
It is heat-treated at a temperature of 850° C. and used as a glass-ceramic insulating material, and in this case, in this heat treatment, lithium silicate (Ls, 0.2SiO2) is precipitated as a main crystal and used as crystallized glass.

本実施例の多層配線基板は、次に述べるI〜■の工程に
よシ、製造する。
The multilayer wiring board of this example is manufactured according to the steps I to (2) described below.

工程Iニガラス粉末の作成 第1表に示す組成となるよう、5IO2,Li2O。Step I: Preparation of Nigarasu powder 5IO2, Li2O so as to have the composition shown in Table 1.

’−13203r K29 + P2O5(またはTi
02)を酸化物あるいは炭酸塩として秤量し、混合後、
白金るつぼに投入して1400℃にて溶融させる。 こ
れを、急冷し、粉砕して、平均粒径1.5μmのガラス
粉末を作成する。
'-13203r K29 + P2O5 (or Ti
02) as an oxide or carbonate, and after mixing,
It is put into a platinum crucible and melted at 1400°C. This is rapidly cooled and pulverized to create a glass powder with an average particle size of 1.5 μm.

工程■:グリ・−ンシートの作成 ここでは、平均粒径1.0μmの石英ガラスの所定量(
30−60W t%)を上記ガラス粉に加えて混合し、
ポリビニルブチラール樹脂を加えて更に混合し、可塑剤
・揮発性溶剤を加えて混線後、脱気処理してスリップを
作成する。上記ガラス質(結晶化ガラス)粉末と石英ガ
ラスとの配合割合は第2表に示す通シであシ、また、本
実施例の扁1〜A8の各側で使用のガラス質の組成は、
第1表に記載の嵐で特定した。
Process ■: Creation of green sheet Here, a predetermined amount of quartz glass with an average particle size of 1.0 μm (
30-60W t%) is added to the above glass powder and mixed,
Polyvinyl butyral resin is added and further mixed, a plasticizer/volatile solvent is added, crosstalk is performed, and a slip is created by degassing. The blending ratio of the vitreous (crystallized glass) powder and quartz glass is as shown in Table 2, and the composition of the vitreous material used on each side of flats 1 to A8 in this example is as follows:
It was identified by the storms listed in Table 1.

次いでこのスリップをドクターブレード法により2リエ
ステル等のフィルム上に塗布・乾燥してガラスのグリー
ンシートを作成し、このグリーンシートに回路上必要な
導通孔と印刷積層位置決め用基準孔を形成する。
Next, this slip is applied onto a film of 2-reester or the like by a doctor blade method and dried to create a glass green sheet, and conductive holes necessary for the circuit and reference holes for positioning the printing layer are formed in this green sheet.

工程■:導体ペーストの印刷とシート積層金粉末に、エ
チルセルロースとポリビニルブチラール樹脂を溶融した
ビヒクルを加えて、導体ペースト作成した。これをシー
トに形成した孔に印刷充填するとともに、必要な配線回
路を形成する。
Step (2): Printing and laminating a conductive paste and sheet A conductive paste was prepared by adding a vehicle in which ethyl cellulose and polyvinyl butyral resin were melted to the gold powder. This is printed and filled into holes formed in the sheet, and necessary wiring circuits are formed.

また、LSIおよび入出力ビンが接続される端子は、A
g/Pdの啄−スト印刷して形成する。
Also, the terminal to which the LSI and input/output bin are connected is A
It is formed by block printing of g/Pd.

所定の回路・やタンを印刷したグリーンシートを順次重
ね合わせ、所定の外形に切断しつつ、加圧・加熱(12
0℃)して積層体を作成する。
Green sheets with predetermined circuits and tongues printed on them are stacked one on top of the other, cut into a predetermined shape, and then pressurized and heated (12
0° C.) to create a laminate.

工程■:焼結 積層体を次に示す温度条件で焼結した。毎時200℃で
400℃まで昇温し、1時間保持してシートおよびペー
ストの樹脂物を分解除去する。次いで毎時200℃で軟
化温度まで昇温して領分保持し、゛ここで結晶析出のた
めの核形成を行なう。そして、毎時200℃で結晶温度
まで昇温しでI分保持し、ガラスシートの焼結を行なっ
た。
Step (2): The sintered laminate was sintered under the following temperature conditions. The temperature is raised to 400°C at a rate of 200°C per hour and held for 1 hour to decompose and remove the resinous materials in the sheet and paste. Next, the temperature is raised to a softening temperature at 200° C. per hour and maintained, and nucleation for crystal precipitation is performed here. Then, the glass sheet was sintered by increasing the temperature to the crystallization temperature at 200° C. per hour and holding it for 1 minute.

結晶温度は第2表のA ]−A 8の各々につき、同表
に示す温度とした。なおこの場合、結晶温度はこれに限
られず、例えば750〜850℃の間で選択できる。こ
の温度は、ここで用いる高導電性金属の融点よシも充分
に低い。
The crystallization temperature was set to the temperature shown in Table 2 for each of A] to A8 in Table 2. In this case, the crystallization temperature is not limited to this, and can be selected, for example, from 750 to 850°C. This temperature is also sufficiently lower than the melting point of the highly conductive metal used here.

工程V : LSIチップ及び入出力ビンの接続金メッ
キしたエバールの入出力ビンを基板の裏面にAu/Sn
はんだで接合し、LSIチップをPb/Snはんだで接
合して、多層化配線基板を形成する。
Process V: Connection of LSI chip and input/output bin Gold-plated Eval input/output bin is attached to the back side of the board with Au/Sn.
The LSI chips are bonded with solder and the LSI chips are bonded with Pb/Sn solder to form a multilayer wiring board.

上記工程で得られ次ガラスセラミックの諸特性を、その
組成とともに、第2表に示す。本実施例によれば、比誘
電率は5以下とすることができ1極めて低誘電率の絶縁
材料として得ることができ、演算処理の高速化等への対
処として有効である。
The various properties of the glass ceramic obtained in the above process are shown in Table 2 along with its composition. According to this example, the dielectric constant can be set to 5 or less, and an insulating material with an extremely low dielectric constant can be obtained, which is effective for increasing the speed of arithmetic processing.

また熱膨張係数はおよそ50〜70 X 10−77 
”Cの範囲にあシ、約30 X 1o−7/ *cであ
るStチップと余p差がなく、接続部の接着性が良く、
その応力破壊なども生じない。従来のアルミナ基板と同
等のLSIチップ接続寿命が得られる。かつ、従来のガ
ラスセラミックに比して熱膨張係数が大きいので、高導
電性金属との接続性も良好である。よって、使用するチ
ップや配線材料に応じて、最適なものを選択使用するこ
とができる。更に抗折強度も充分である。
Also, the coefficient of thermal expansion is approximately 50-70 x 10-77
``The reeds are in the range of C, there is no difference in extra p from the St chip which is approximately 30 x 1o-7/*c, and the adhesiveness of the connection part is good.
Such stress failure does not occur. LSI chip connection life equivalent to that of conventional alumina substrates can be obtained. Moreover, since it has a larger thermal expansion coefficient than conventional glass ceramics, it has good connectivity with highly conductive metals. Therefore, the optimum one can be selected and used depending on the chip and wiring material used. Furthermore, the bending strength is also sufficient.

〔発明の効果〕〔Effect of the invention〕

上述の如く本、発明の多層回路基板は、低誘電率の絶縁
材料を用いたので、信号伝播を高速化できるとともに、
高抗折強度によシビン接合強度を向上できる。かつ、熱
膨張係数を適切な範囲にとることができるので、信号伝
播を一層高速化すべく、高導電性の材料で配線すること
が充分可能であシ、あ・つ、使用するチップとの接続性
も良好な範囲で選択使用することができるものである。
As mentioned above, since the multilayer circuit board of the present invention uses an insulating material with a low dielectric constant, it is possible to speed up signal propagation, and
The shear joint strength can be improved due to the high flexural strength. In addition, since the coefficient of thermal expansion can be set within an appropriate range, it is possible to conduct wiring using highly conductive materials in order to further speed up signal propagation. It can be used selectively within a range of good properties.

また、本発明の多層回路基板の製造方法は、高導電性金
属の融点以下での焼結によシ回路基板を製造できるので
、高速信号伝播の多層回路基板の生産に有利である。
Further, the method for manufacturing a multilayer circuit board of the present invention is advantageous in producing a multilayer circuit board for high-speed signal propagation, since the circuit board can be manufactured by sintering at a temperature below the melting point of a highly conductive metal.

なお、当然のことではあるが、本発明は前述した実施例
にのみ限定されるものではない。
It should be noted that, as a matter of course, the present invention is not limited only to the embodiments described above.

【図面の簡単な説明】[Brief explanation of the drawing]

添付図面は、本発明の一実施例に係る多層配線基板の断
面図である。
The accompanying drawing is a sectional view of a multilayer wiring board according to an embodiment of the present invention.

Claims (1)

【特許請求の範囲】 1、SiO_2を66〜79wt%、Li_2Oを9〜
20wt%、Al_2O_3を3〜10wt%、K_2
Oを1〜3wt%およびTiO_4あるいはP_2O_
5を3wt%含むガラス質材料70〜40wt%に、石
英ガラス30〜60wt%を混合した材料をガラスセラ
ミック質絶縁材料として用いて回路を多層化したことを
特徴とする多層回路基板。 2、前記ガラス質材料と石英ガラスとはともに粉末とし
て混合したことを特徴とする特許請求の範囲第1項に記
載の多層回路基板。 3、SiO_2を66〜79wt%、Li_2Oを9〜
20wt%、Al_2O_3を3〜10wt%、K_2
Oを1〜3wt%およびTiO_4あるいはP_2O_
5を3wt%含むガラス質材料90〜40wt%に、石
英ガラス30〜60wt%を混合した材料を750〜8
50℃の温度で熱処理してガラスセラミック絶縁材料と
して用い回路を多層化したことを特徴とする多層配線基
板。 4、前記ガラス質材料と石英ガラスとはともに粉末とし
て混合したことを特徴とする特許請求の範囲第3項に記
載の多層回路基板。 5、前記熱処理においてけい酸リチウム(Li_2O・
2SiO_2)を主結晶として析出させることを特徴と
する特許請求の範囲第3項または第4項に記載の多層配
線基板。 6、SiO_2を66〜79wt%、Li_2Oを9〜
20wt%、Al_2O_3を3〜10wを%、K_2
Oを1〜3wt%およびTiO_4あるいはP_2O_
5を3wt%含むガラス質材料に、石英ガラスを混合し
た材料を750〜850℃の結晶析出温度で熱処理し、
けい酸リチウム(Li_2O・2SiO_2)を析出さ
せて結晶化ガラスとし、これをガラスセラミック質絶縁
材料として用い回路を多層化したことを特徴とする多層
回路基板の製造方法。
[Claims] 1. 66 to 79 wt% of SiO_2, 9 to 79 wt% of Li_2O
20wt%, 3-10wt% of Al_2O_3, K_2
1 to 3 wt% O and TiO_4 or P_2O_
1. A multilayer circuit board characterized in that a circuit is multilayered using a material obtained by mixing 30 to 60 wt% of quartz glass with 70 to 40 wt% of a glassy material containing 3 wt% of silica glass as a glass ceramic insulating material. 2. The multilayer circuit board according to claim 1, wherein the glassy material and quartz glass are both mixed as powder. 3. 66-79 wt% SiO_2, 9-79 wt% Li_2O
20wt%, 3-10wt% of Al_2O_3, K_2
1 to 3 wt% O and TiO_4 or P_2O_
750 to 8
A multilayer wiring board characterized in that it is heat treated at a temperature of 50°C and used as a glass ceramic insulating material to form a multilayer circuit. 4. The multilayer circuit board according to claim 3, wherein the glassy material and quartz glass are both mixed as powder. 5. Lithium silicate (Li_2O・
The multilayer wiring board according to claim 3 or 4, characterized in that 2SiO_2) is precipitated as a main crystal. 6. 66-79 wt% SiO_2, 9-79 wt% Li_2O
20wt%, 3~10w% of Al_2O_3, K_2
1 to 3 wt% O and TiO_4 or P_2O_
A material obtained by mixing quartz glass with a glassy material containing 3 wt% of 5 is heat-treated at a crystal precipitation temperature of 750 to 850 °C,
A method for manufacturing a multilayer circuit board, characterized in that lithium silicate (Li_2O.2SiO_2) is precipitated to form crystallized glass, and this is used as a glass-ceramic insulating material to form a multilayer circuit.
JP59131169A 1984-06-27 1984-06-27 Multilayer circuit board and method of producing same Pending JPS6112091A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59131169A JPS6112091A (en) 1984-06-27 1984-06-27 Multilayer circuit board and method of producing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59131169A JPS6112091A (en) 1984-06-27 1984-06-27 Multilayer circuit board and method of producing same

Publications (1)

Publication Number Publication Date
JPS6112091A true JPS6112091A (en) 1986-01-20

Family

ID=15051618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59131169A Pending JPS6112091A (en) 1984-06-27 1984-06-27 Multilayer circuit board and method of producing same

Country Status (1)

Country Link
JP (1) JPS6112091A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62279938A (en) * 1986-05-29 1987-12-04 富士通株式会社 Glass-ceramic substrate
JPH03204995A (en) * 1989-10-27 1991-09-06 Matsushita Electric Ind Co Ltd Manufacture of ceramic multilayered board
US5458709A (en) * 1991-04-12 1995-10-17 Fujitsu Limited Process for manufacturing multi-layer glass ceramic substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62279938A (en) * 1986-05-29 1987-12-04 富士通株式会社 Glass-ceramic substrate
JPH03204995A (en) * 1989-10-27 1991-09-06 Matsushita Electric Ind Co Ltd Manufacture of ceramic multilayered board
US5458709A (en) * 1991-04-12 1995-10-17 Fujitsu Limited Process for manufacturing multi-layer glass ceramic substrate

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