JPS61120428A - Method of processing silicon substrate - Google Patents

Method of processing silicon substrate

Info

Publication number
JPS61120428A
JPS61120428A JP24173284A JP24173284A JPS61120428A JP S61120428 A JPS61120428 A JP S61120428A JP 24173284 A JP24173284 A JP 24173284A JP 24173284 A JP24173284 A JP 24173284A JP S61120428 A JPS61120428 A JP S61120428A
Authority
JP
Japan
Prior art keywords
diffusion
phosphorus
silicon
film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24173284A
Other languages
Japanese (ja)
Inventor
Nobuyuki Izawa
伊沢 伸幸
Toshihiko Suzuki
利彦 鈴木
Yasaburo Kato
加藤 弥三郎
Hiroshi Sato
弘 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP24173284A priority Critical patent/JPS61120428A/en
Publication of JPS61120428A publication Critical patent/JPS61120428A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Abstract

PURPOSE:To obtain clean surfaces on a substrate having an oxygen concentration of 6X10<17>atm/cm<3> or less, by diffusing an impurity having getter action into the first and second surfaces of the substrate and then removing the impurity diffusion layers. CONSTITUTION:P is diffused in the mirror finished faces (100) of a P type Si substrate 11 having a concentration of oxygen of 6X10<17>atm/cm<3> or less so as to provide N<+> type layers 13 on both the front and rear surfaces. These surfaces are covered with protection layers 14 of pure polysilicon, and the N<+> type lasers 13 are completely removed by mirror polishing them on one side thereof. According to this method, in which P is not locally concentrated and no residual diffusion layer 13 is left, clean surfaces of Si can be obtained with simplified processes. By using such substrates, the device manufacturing yield can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はシリコンウェハ等のシリコン基板の処理方法、
特にリン等によるゲッタリング処理法に関するものであ
る。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for processing a silicon substrate such as a silicon wafer,
In particular, it relates to a gettering treatment method using phosphorus or the like.

〔背景技術とその問題点〕[Background technology and its problems]

半導体素子製造におけるゲッタリング処理法は、使用さ
れる結晶の無転位化と共に重要になってきている。結晶
内部に存在する金属等の不純物及び各種プロセスで導入
される各種の汚染物が、有転位結晶に比して、無転位結
晶においてはより敏感に影響し結晶欠陥の発生、キャリ
ヤライフタイムの低下につながワていた。この為、ウェ
ハ裏面等に故意に欠陥を発生させ、この欠陥領域に上記
各種の汚染物をゲッターする方法がとられていた。
Gettering processing methods in the manufacture of semiconductor devices are becoming more important as the crystals used are becoming dislocation-free. Impurities such as metals existing inside the crystal and various contaminants introduced in various processes affect crystals without dislocations more sensitively than crystals with dislocations, causing crystal defects and reducing carrier lifetime. It was connected to. For this reason, a method has been adopted in which a defect is intentionally generated on the back surface of the wafer, and the various contaminants mentioned above are gettered in the defect area.

例えばCOD固体撮像棄子、  MOS−LSI C大
規模集積回路)、バイポーラIC等のシリコンデバイス
の製造工程においては、シリコンウェハ自体の欠陥及び
製造工程中にシリコンウェハに導入される重金属汚染、
結晶欠陥等を低減する目的で、ゲッタリング処理をシリ
コンウェハの裏面、内部に施している。ゲッタリング法
としては、サンドブラスト、イオン注入、リン拡散等の
ゲッタリングCIExtrinsic Getter)
と、結晶自体の酸素析出にともなう結晶内部の欠陥によ
るゲッタリング(Intrinsic Getter)
がある、この中ではゲッタリング効果として一番強く且
つ持続性のあるリンゲッタリング法が用いられている。
For example, in the manufacturing process of silicon devices such as COD solid-state imaging devices, MOS-LSI C large-scale integrated circuits), and bipolar ICs, defects in the silicon wafer itself and heavy metal contamination introduced into the silicon wafer during the manufacturing process,
Gettering treatment is performed on the back surface and inside of the silicon wafer in order to reduce crystal defects and the like. Gettering methods include sandblasting, ion implantation, phosphorus diffusion, etc. (CIExtrinsic Getter)
and gettering (intrinsic getter) due to defects inside the crystal due to oxygen precipitation in the crystal itself.
Of these methods, the ring gettering method is used because it has the strongest and most sustainable gettering effect.

しかし、通常のリンゲッタリング法では、シリコンウェ
ハの表面を保護層で覆って裏面にリンを拡散するとき、
保護層のピンホール或はリン拡散中のリンの異常拡散(
メルトスルー)により表面のシリコン中に局部的にリン
が拡散される。例えばCOD固体撮像素子ではこの局部
的なリンの拡散が画像欠陥の原因となる為に、この防止
法が必要である。
However, in the normal phosphorus gettering method, when the front surface of the silicon wafer is covered with a protective layer and phosphorus is diffused to the back surface,
Pinholes in the protective layer or abnormal phosphorus diffusion during phosphorus diffusion (
Phosphorus is locally diffused into the silicon surface by melt-through. For example, in a COD solid-state image pickup device, this local diffusion of phosphorus causes image defects, so a prevention method is necessary.

第1図はCOD固体撮像素子に用いられている従来のリ
ンゲッタリング処理方法の一例である。
FIG. 1 is an example of a conventional ring-gettering processing method used in a COD solid-state image sensor.

之は先づ、第1図Aに示すように例えは(100)面の
P形シリコンウェハ(11の表面にリン拡散時の保護膜
となる厚さ1.0μm程度の5if2膜(2)を堆積す
る。この5t02膜(2)のピンホール減少対策として
HCl雰囲気中、1100℃の熱酸化による5102M
臭(厚さ1800人)と420℃(7) CV D S
tOJjM (厚す8000人)の2層を堆積し、シリ
コンウェハ(1)の裏面の5t02膜を除去している0
次に、第1図Bに示すようにシリコンウェハ(1)の裏
面にリンを拡散してリン拡散層(3;を形成する。従来
工程では1100℃、60分のリン拡散を行い、表面濃
度がI X IQ21rx−3以上になっている。次に
第1図Cに示すようにリンのウェハ表面への外部拡散を
防止する為に、Si3N+膜(厚さ600人程1)と純
粋な多結晶シリコン膜(厚さ2500人程度1の保護層
(4)を堆積する。この保護層(勾は減圧CVD法を用
いると両面に堆積する。次に、第1図りに示すようにシ
リコンウェハ(1)の表面に堆積された保護層(4)及
び5t02膜(2)をエツチング除去してシリコン表面
(1a)を臨まず。
First, as shown in Fig. 1A, a 5if2 film (2) with a thickness of about 1.0 μm is coated on the surface of a P-type silicon wafer (11) with a (100) plane. As a measure to reduce pinholes in this 5t02 film (2), 5102M was deposited by thermal oxidation at 1100°C in an HCl atmosphere.
Odor (1800 people thick) and 420℃ (7) CV D S
Two layers of tOJjM (8000 layers thick) are deposited and the 5t02 film on the back side of the silicon wafer (1) is removed.
Next, as shown in FIG. 1B, phosphorus is diffused onto the back surface of the silicon wafer (1) to form a phosphorus diffusion layer (3).In the conventional process, phosphorus diffusion is performed at 1100°C for 60 minutes, and the surface concentration is IXIQ21rx-3 or higher.Next, as shown in Figure 1C, in order to prevent the external diffusion of phosphorus to the wafer surface, a Si3N+ film (about 600mm thick) and a pure multilayer film were used. A protective layer (4) of crystalline silicon film (about 2500 mm thick) is deposited on both sides using low pressure CVD. Next, as shown in the first diagram, a silicon wafer (4) is deposited. The protective layer (4) and the 5t02 film (2) deposited on the surface of 1) are removed by etching so as not to expose the silicon surface (1a).

しかるに、かかる従来のリンゲッタリング処理方法にお
いては、次の様な問題点があった。まず、リン拡散を行
う際のウェハ表面のS i(h 1JIi (2)のピ
ンホールが問題である。 5iOd臭(2)を一層構造
とした場合には膜厚と共にピンホールは減少するもO個
/−にはならない、さらに熱酸化(H(J雰囲気中)に
よるS iOz膜とCV D 5i02の2層構造にし
てもピンホールは完全になくならない、またリン拡散時
の5i02膜(2)にピンホールがなくても、リン拡散
時に5iOJ臭(2)の表面にリンの粉末等が付着して
メルトスルーの様な異名拡散を生じることがある。従7
てマスク効果のある保−膜の選択が重要となるが、適当
なものがないのが現状である。また、第1図りの工程で
は、ウェハ表面側の保護層(4)及びS 1Q21臭(
2)を全面完全に除去する必要があるが、保護層(滲を
構成する5taN4Ill!及び多結晶シリン膜の膜厚
の不均一性やごみにより一部局部的に残ることがある。
However, such conventional ring-gettering processing methods have the following problems. First, there is a problem with the pinholes of S i (h 1JIi (2)) on the wafer surface when performing phosphorus diffusion.If the 5iOd odor (2) is made into a single layer structure, the pinholes will decrease with the film thickness, but O In addition, pinholes do not completely disappear even if a two-layer structure of SiOz film and CVD 5i02 is formed by thermal oxidation (H (in J atmosphere)), and the 5i02 film (2) during phosphorus diffusion Even if there are no pinholes in the 5iOJ odor (2), phosphorus powder may adhere to the surface of the 5iOJ odor (2) during phosphorus diffusion, resulting in heterogeneous diffusion such as melt-through.
Therefore, it is important to select a protective film that has a masking effect, but at present there is no suitable material. In addition, in the step of the first drawing, the protective layer (4) on the wafer surface side and the S1Q21 odor (
2) must be completely removed from the entire surface, but some may remain locally due to non-uniformity in the thickness of the protective layer (5taN4Ill! and polycrystalline syringe film constituting the ooze) and dust.

、S i(h i*(2)も同様なことがある。, S i (h i *(2)) may also be similar.

また膜を堆積し、除去する工程が増加するとシリコン表
面の清浄度を保つことが困難となり、従ってこのような
工程の増加は出来るだけ避けたいところである。さらに
、従来工程ではリンゲッタリング処理の為に8工程必要
であり、工程が長(なる。
Furthermore, as the number of steps for depositing and removing films increases, it becomes difficult to maintain the cleanliness of the silicon surface, so it is desirable to avoid increasing the number of steps as much as possible. Furthermore, in the conventional process, eight steps are required for the ring gettering process, which makes the process long.

以上の様な原因により現実のCOD固体撮像素子では、
工程改善の努力を行っても完全な方法はなく、リンのと
び込みによる白黒点、S i(h I!!、5t3N+
膜等の残りによるパターン欠陥が発生していた。
Due to the above reasons, in actual COD solid-state image sensors,
Even if efforts are made to improve the process, there is no perfect method.
Pattern defects were caused by remaining film, etc.

この欠点を少なくする方法として、次の方法がある。即
ち保護膜なしでウェハ両面に拡散を行ない、その後片面
をポリッシング等により拡散層を削除する方法である。
The following methods can be used to reduce this drawback. That is, this is a method in which diffusion is performed on both sides of the wafer without a protective film, and then the diffusion layer is removed by polishing or the like on one side.

この方法は前記方法に比し、工程の簡略化、ピンホール
による拡散等の心配はない。しかし、この場合、高濃度
拡散により拡散層(2〜5μ程度)より深い所に結晶欠
陥領域が発生しく約10μ)かつチコクラルスキー法に
よって得られたシリコン結晶に多く含まれる酸素のため
、結晶内部に欠陥が発生し、ポリッシング深さを変えて
も、動作領域を形成することの出来る良質の結晶領域が
殆んど存在しない事が判明した。
Compared to the above-described method, this method simplifies the process and eliminates concerns about diffusion due to pinholes. However, in this case, due to high concentration diffusion, a crystal defect region occurs deeper than the diffusion layer (approximately 10μ), and the silicon crystal obtained by the Czycochralski method contains a large amount of oxygen. It was found that defects were generated internally and that even if the polishing depth was varied, there was almost no good quality crystalline region that could form an active region.

そこで、拡散温度でのSi中の酸素の飽和溶解度に着目
し、飽和溶解度以下の酸素含有量を有するシリコン基体
にゲッター処理を施すことにより、酸素の析出により結
晶内部に欠陥が発生する事を防止する。
Therefore, we focused on the saturation solubility of oxygen in Si at the diffusion temperature and performed getter treatment on a silicon substrate with an oxygen content below the saturation solubility to prevent defects from occurring inside the crystal due to oxygen precipitation. do.

〔発明の目的〕[Purpose of the invention]

本発明は上述のような欠点を解消した半導体基体の処理
方法を提供するものである。
The present invention provides a method for processing semiconductor substrates that eliminates the above-mentioned drawbacks.

〔発明の概要〕[Summary of the invention]

本発明は、酸素濃度が6 X 10” ato伽/d以
下のシリコン基板の第1及び第2主面に夫々ゲッタ作用
のある不純物を拡散した後、前記第1主面側を上記不純
物の拡散層が除去されるまで研磨する。
In the present invention, after impurities having a getter function are diffused into the first and second main surfaces of a silicon substrate having an oxygen concentration of 6 x 10" ato/d or less, the impurities are diffused onto the first main surface side. Polish until the layer is removed.

この発明のゲッタリング処理方法では、不純物の局部的
なとび込みがない上に、膜の残りもなく、半導体基体の
表面が清浄になる。
In the gettering treatment method of the present invention, there is no local penetration of impurities, and there is no remaining film, resulting in a clean surface of the semiconductor substrate.

〔実施例〕〔Example〕

以下、第2図を参照して本発明の実施例について説明す
る。
Hereinafter, embodiments of the present invention will be described with reference to FIG.

本例においては、半導体基体例えば(100)面で酸素
濃度が4 X 1017atovas/−のP形シリコ
ンウェハ(11)を用意する。この場合、シリコンウェ
ハ(11)はラップし、ケミカルエツチング仕上げのウ
ェハを用いる。片面鏡面研磨した通常のウェハを用いて
もよいが、再度鏡面研磨することになるので、両面ケミ
カルエツチング仕上げの方がコスト的に有利である。鏡
面研磨前のシリコンウェハを用いる為にシリコンウェハ
の厚さは研磨量分だけ厚くしておく必要がある。例えば
3インチのウェハは、最終仕上げの厚さが400μmな
ので450μm前後にしておく必要がある。
In this example, a semiconductor substrate, for example, a P-type silicon wafer (11) having a (100) plane and an oxygen concentration of 4×10 17 atovas/− is prepared. In this case, the silicon wafer (11) is lapped and a chemically etched wafer is used. An ordinary wafer with mirror polishing on one side may be used, but since mirror polishing is required again, chemical etching finish on both sides is more cost-effective. Since a silicon wafer before mirror polishing is used, the thickness of the silicon wafer must be increased by the amount of polishing. For example, a 3-inch wafer has a final finished thickness of 400 μm, so it needs to be around 450 μm.

而し°て、第2図Aに示すようにこのシリコンウェハ(
11)の表裏両主面にリンを拡散してN+形広拡散層1
3)を形成する。この時の温度は1100℃で時間は6
0分である。
Then, as shown in Figure 2A, this silicon wafer (
11) Diffuse phosphorus on both the front and back principal surfaces to form an N+ type wide diffusion layer 1
3) Form. The temperature at this time was 1100℃ and the time was 6
It is 0 minutes.

次に、第2図Bに示すようにシリコンウェハ(11)の
両生面上に減圧CVD法によってSi3N+膜と多結晶
シリコン膜の2層構造あるいは純粋な多結晶シリコン膜
による保護層(14)を堆積する。
Next, as shown in FIG. 2B, a protective layer (14) with a two-layer structure of Si3N+ film and polycrystalline silicon film or a pure polycrystalline silicon film is formed on both sides of the silicon wafer (11) by low pressure CVD. accumulate.

なお、常圧CVD法では裏面側だけに堆積すればよい。Note that in the normal pressure CVD method, it is sufficient to deposit only on the back side.

次で、第2図Cに示すようにシリコンウェハ(11)の
片面即ち表面側を鏡面Vr磨する。このときの研磨量は
リンの拡散層(14)を十分除去するにたる量である。
Next, as shown in FIG. 2C, one side, that is, the front side, of the silicon wafer (11) is mirror-polished. The amount of polishing at this time is sufficient to sufficiently remove the phosphorus diffusion layer (14).

かかるリンゲッタリング処理法によれば、シリコンウェ
ハ(11)の両主面にリンを拡散し、さらに保護層(1
4)を堆積した後に、表面側をリンの拡散層(13)が
除去されるまで鏡面研磨するので、本質的に従来の如き
リンの局部的なとび込みがなくなり、また5t02.5
bN4等の膜の残りもなく、清浄なシリコン表面が得ら
れる。また工程を簡略化することができ、歩留りの向上
を図ることができる。従って、COD固体撮像素子に適
用した場合、リンのとび込みによる白黒点、5iO2r
 Si3N+等の膜の残りによるパターン欠陥の発生は
なくなる。
According to this phosphorus gettering treatment method, phosphorus is diffused onto both main surfaces of the silicon wafer (11), and the protective layer (11) is further coated with the protective layer (11).
After depositing 4), the surface side is mirror-polished until the phosphorus diffusion layer (13) is removed, which essentially eliminates the local penetration of phosphorus as in the conventional method.
A clean silicon surface is obtained without any residual film such as bN4. Further, the process can be simplified and the yield can be improved. Therefore, when applied to a COD solid-state image sensor, black and white spots due to phosphorus absorption, 5iO2r
Pattern defects caused by remaining films such as Si3N+ are no longer generated.

尚、上側ではゲッタ作用のある不純物としてリンを用い
たが、リン以外の不純物でも良い。
Although phosphorus was used as an impurity having a getter effect on the upper side, impurities other than phosphorus may be used.

本発明の基本構成は上述の如くであるが、実施に際して
は次の2点に注意する必要がある。1つは鏡面研磨後に
観察される積層欠陥であり、もう1つはスリップライン
の発生である。本発明ではリン拡散を行った後、シリコ
ン表面を研磨してシリコン内部を表面として使用する。
Although the basic configuration of the present invention is as described above, it is necessary to pay attention to the following two points when implementing it. One is stacking faults observed after mirror polishing, and the other is the occurrence of slip lines. In the present invention, after performing phosphorus diffusion, the silicon surface is polished and the interior of the silicon is used as the surface.

通常用いられているCZ結晶で本処理方法を行うと、シ
リコン結晶中の酸素濃度が高い為にリン拡散時(基本的
には酸化しても同じ)にシリコン中の酸素が析出をおこ
し、欠陥核あるいは積層欠陥の核となる。
If this treatment method is applied to a commonly used CZ crystal, the oxygen in the silicon will precipitate during phosphorus diffusion (basically the same as oxidation) due to the high oxygen concentration in the silicon crystal, resulting in defects. It becomes the nucleus or the nucleus of a stacking fault.

この析出はシリコン中の酸素濃度に依存し酸素濃度が高
い程析出量が多くなる。この為に本発明に用いるシリコ
ンウェハ(11)は酸素濃度が低く制御されたものを使
用する必要がある。使用するシリコンウェハ(11)の
酸素濃度は6 X 101017ato/crll以下
の範囲が好ましい。
This precipitation depends on the oxygen concentration in silicon, and the higher the oxygen concentration, the greater the amount of precipitation. For this reason, the silicon wafer (11) used in the present invention must have a controlled low oxygen concentration. The oxygen concentration of the silicon wafer (11) used is preferably in the range of 6 x 101017ato/crll or less.

一方酸素濃度がI X 10” atotas/cd以
上の酸素濃度を有するシリコン基板に同様の処理を施し
た場合、欠陥密度は102〜103個/−であった。
On the other hand, when a silicon substrate having an oxygen concentration of I x 10'' atotas/cd or more was subjected to the same treatment, the defect density was 102 to 103 defects/-.

1100℃でのシリコン中の酸素の溶解度はほぼ4×1
01” atones/c11上述の推測と一致する。
The solubility of oxygen in silicon at 1100℃ is approximately 4×1
01” atones/c11 This agrees with the above speculation.

両面拡散を行なうとウェハ端部にも拡散が行なわれる。When double-sided diffusion is performed, diffusion is also performed at the edges of the wafer.

拡散領域は拡散不純物のアウトディフュージョンを防ぐ
ため、適当な保護膜が形成されて各プロセスを経ていく
、端部に形成される保護膜は、端部形状の複雑さ、取扱
い時の各種衝撃等により破損され易い。従って端部拡散
部が露出され、拡散不純物のアウトディフュージョンが
起り、動作領域に不要不純物として拡散され支障をきた
すことがある。
In order to prevent out-diffusion of diffused impurities, an appropriate protective film is formed on the diffusion region before going through each process. Easily damaged. Therefore, the end diffusion portion is exposed, and out-diffusion of diffused impurities occurs, which may cause problems by being diffused into the operating region as unnecessary impurities.

本発明はこれを避けるため、両面拡散を行った後、ウェ
ハ端部を機械的又は化学研磨等の手段を用い、拡散層を
除去したのち、上記工程に入ることにより、着るしく製
造プロセスの安定化がはかれ、素子の歩留り向上、特性
向上がはかられた。
In order to avoid this, the present invention is designed to stabilize the manufacturing process by performing double-sided diffusion, removing the diffusion layer by mechanically or chemically polishing the edge of the wafer, and then entering the above process. As a result, improvements in device yield and characteristics were achieved.

〔発明の効果〕〔Effect of the invention〕

上述せる本発明のゲッタリング処理方法によれば、不純
物の局部的なとび込みがない上に、膜の残りもなく、清
浄な半導体基体表面が得られる。
According to the above-described gettering treatment method of the present invention, a clean semiconductor substrate surface can be obtained without impurities locally infiltrating and without any remaining film.

また、工程が簡略化され、歩留りが向上する。従って、
CCD固体撮像素子、  MOS−LS1.バイポーラ
IC等の半導体デバイスの製造に適用して好適ならしめ
るものである。
Moreover, the process is simplified and the yield is improved. Therefore,
CCD solid-state image sensor, MOS-LS1. This makes it suitable for application to the manufacture of semiconductor devices such as bipolar ICs.

【図面の簡単な説明】[Brief explanation of drawings]

第1rI!JA−Dは従来のゲッタリング処理方法の例
を示す工程図、第2図A−Cは本発明によるゲッタリン
グ処理方法の例を示す工程図である。 (1)(11)はシリコンウェハ、+3)(13)はリ
ン拡散層、(41(14)は保護層である。 第1図
1st rI! JA-D are process diagrams showing an example of a conventional gettering processing method, and FIGS. 2A-2C are process diagrams showing an example of a gettering processing method according to the present invention. (1) (11) are silicon wafers, +3 (13) are phosphorus diffusion layers, (41 (14) are protective layers.

Claims (1)

【特許請求の範囲】[Claims]  酸素濃度が6×10^1^7atoms/cm^3以
下のシリコン基板の第1及び第2主面に夫々ゲッタ作用
のある不純物を拡散する工程と、前記第1主面の前記不
純物拡散層を除去する工程を有してなるシリコン基板の
処理方法。
a step of diffusing an impurity having a getter function into the first and second main surfaces of a silicon substrate having an oxygen concentration of 6×10^1^7 atoms/cm^3 or less, and forming the impurity diffusion layer on the first main surface. A method for processing a silicon substrate, comprising a step of removing it.
JP24173284A 1984-11-16 1984-11-16 Method of processing silicon substrate Pending JPS61120428A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24173284A JPS61120428A (en) 1984-11-16 1984-11-16 Method of processing silicon substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24173284A JPS61120428A (en) 1984-11-16 1984-11-16 Method of processing silicon substrate

Publications (1)

Publication Number Publication Date
JPS61120428A true JPS61120428A (en) 1986-06-07

Family

ID=17078712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24173284A Pending JPS61120428A (en) 1984-11-16 1984-11-16 Method of processing silicon substrate

Country Status (1)

Country Link
JP (1) JPS61120428A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04218921A (en) * 1990-07-05 1992-08-10 Toshiba Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04218921A (en) * 1990-07-05 1992-08-10 Toshiba Corp Manufacture of semiconductor device

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